Texas Instruments TPS2231MRGPR, TPS2231MRGPR-2, TPS2231MRGPR-3, TPS2231PW, TPS2231PWP User Manual

RGP PW PWP DAP

AUXIN

3.3VIN

1.5VIN

AUXOUT

3.3VOUT

1.5VOUT

PERST

CPPE

CPUSB

SHDN
STBY
SYSRST
OC

TPS2231

Host Connector

ExpressCard Connector

GND RCLKEN

REFCLK+
REFCLK−

Express Card

Host

Power

Source

Host
Chip

Set/Lock

Circuits

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TPS2231
TPS2236

.................................................................................................................................................. SLVS536J –JULY 2004–REVISED SEPTEMBER 2009

ExpressCard™ POWER INTERFACE SWITCH

Check for Samples: TPS2231 TPS2236

1

FEATURES

23

• Meets the ExpressCard™ Standard

• Available in a 20-pin TSSOP, a 20-pin QFN, or
24-pin PowerPAD™ HTSSOP (Single)

(ExpressCard|34 or ExpressCard|54) • Available in a 32-pin PowerPAD™ HTSSOP

• Compliant with the ExpressCard™

(Dual)

Compliance Checklists

• Fully Satisfies the ExpressCard™
Implementation Guidelines

• Supports Systems with WAKE Function

• TTL-Logic Compatible Inputs

• Short Circuit and Thermal Protection

• –40°C to 85°C Ambient Operating

APPLICATIONS

• Notebook Computers

• Desktop Computers

• Personal Digital Assistants (PDAs)

• Digital Cameras

• TV and Set Top Boxes

Temperature Range

DESCRIPTION

The TPS2231 and TPS2236 ExpressCard power interface switches provide the total power management solution
required by the ExpressCard specification. The TPS2231 and TPS2236 ExpressCard power interface switches
distribute 3.3 V, AUX, and 1.5 V to the ExpressCard socket. Each voltage rail is protected with integrated
current-limiting circuitry.

The TPS2231 supports systems with single-slot ExpressCard|34 or ExpressCard|54 sockets. The TPS2236
supports systems with dual-slot ExpressCard sockets.

End equipment for the TPS2231 and TPS2236 include notebook computers, desktop computers, personal digital
assistants (PDAs), and digital cameras.

1

2PowerPAD is a trademark of Texas Instruments.
3ExpressCard is a trademark of Personal Computer Memory Card International Association.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2004–2009, Texas Instruments Incorporated

TPS2231
TPS2236

SLVS536J –JULY 2004–REVISED SEPTEMBER 2009..................................................................................................................................................

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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AVAILABLE OPTIONS

T

A

NUMBER OF CHANNELS

TSSOP PowerPAD HTSSOP QFN

PACKAGED DEVICES

–40°C to 85°C Single TPS2231PW TPS2231PWP TPS2231MRGP-1

Dual TPS2236DAP

(1) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2231PWPR).
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(3) The TPS2231MRGP is identical to the TPS2231 with the exception of the PowerPAD dimensions. See the Thermal Pad Mechanical

data portion of this data sheet for specific information. The thermal pad for the TPS2231MRGP and TPS2231MRGP-1 is 2,2 mm × 2,2
mm; the thermal pad for the TPS2231RGP is 2,7 mm × 2,7 mm.

(4) The TPS2231MRGP-1 is identical to the TPS2231MGRP with the exception that the orientation of the part in the reel is rotated 180°.

See the Package Materials Information portion of this data sheet for specific information.

(5) The TPS2231MRGP-2 is identical to the TPS2231MRGP with the exception that the orientation of the part in the reel is rotated 90° and

does not have an internal pull-up resistor between AUX IN and SYSRST. See the Package Materials Information portion of this data
sheet for specific information.

(6) The TPS2231MRGP-3 is identical to the TPS2231MRGP with the exception that the 1.5VIN and 3.3VIN UVLO circuits are independent.

(1) (2)

TPS2231RGP

TPS2231MRGP

TPS2231MRGP-2
TPS2231MRGP-3

(3)

(4)
(5)
(6)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

V

I

Input voltage range for card
power

Logic input/output voltage –0.3 to 6 V

V

O

Output voltage range V

Continuous total power dissipation See Dissipation Rating Table

I

O

Output current I

OC sink current 10 mA
PERST sink/source current 10 mA

T

J

T

stg

Operating virtual junction temperature range –40 to 120 °C
Storage temperature range –55 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

ESD

Electrostatic discharge
protection

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

I(3.3VIN)

V

I(1.5VIN)

V

I(AUXIN)

V

O(3.3VOUT)
O(1.5VOUT)

V

O(AUXOUT)

I

O(3.3VOUT)
O(AUXOUT)

I

O(1.5VOUT)

Human body model TPS2236, all pins except
(HBM) MIL-STD-883C PERSTx and OCx

Charge device model (CDM) 500 V

(1)

TPS223x UNIT

–0.3 to 6 V
–0.3 to 6 V
–0.3 to 6 V

–0.3 to 6 V
–0.3 to 6 V
–0.3 to 6 V

Internally limited
Internally limited
Internally limited

TPS2231

2 kV

TPS2236, PERSTx and OCx 1.5 kV

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TPS2236

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DISSIPATION RATINGS (Thermal Resistance = °C/W)

PowerPAD not soldered down

(1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface), (The table is assuming that the maximum junction

(2) This device is mounted on a JEDEC JESO51.5 high-k board (2 signal, 2 plane). The values assume a maximum junction temperature of

RECOMMENDED OPERATING CONDITIONS

V

I(3.3VIN)

V

I(1.5VIN)

V

I(AUXIN)

I

O(3.3VOUT)

I

O(1.5VOUT)

I

O(AUXOUT)

T

J

.................................................................................................................................................. SLVS536J –JULY 2004–REVISED SEPTEMBER 2009

PACKAGE

PW (20)

PWP (24)

RGP (20)

DAP (32)

DAP (32)

(1)

(1)

(2)

(1)

(1)

TA≤ 25°C DERATING FACTOR TA= 70°C TA= 85°C

POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING

704.2 mW 7.41 mW/°C 370.6 mW 259.5 mW
3153 mW 33.19 mW/°C 1659.5 mW 1161.6 mW

3277.5 mW 34.5 mW/°C 1725 mW 1207.3 mW

993.4 mW 10.46 mW/°C 522.8 mW 366 mW

4040.8 mW 42.55 mW/°C 2126.8 mW 1488.7 mW

temperature is 120°C). The power pad on the device must be soldered down to the power pad on the board if best thermal performance
is needed.

120°C.

MIN MAX UNIT

3.3VIN is only required for its respective functions 3 3.6

Input voltage 1.5VIN is only required for its respective functions 1.35 1.65 V

AUXIN is required for all circuit operations 3 3.6

0 1.3 A

Continuous output current TJ= 120°C 0 650 mA

0 275 mA

Operating virtual junction temperature –40 120 °C

ELECTRICAL CHARACTERISTICS

TJ= 25°C, V
V

I(/SYSRST)

POWER SWITCH

R

(DIS_FET)

I

OS

= 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)

Power switch 1.5VIN to 1.5VOUT With two switches
resistance on for dual

Discharge resistance on 3.3V/1.5V/AUX outputs V

Short-circuit
output current

Thermal
shutdown

Current-limit
response time

I(3.3VIN)

= V

(1)

= 3.3 V, V

I(AUXIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

3.3VIN to 3.3VOUT with two switches
on for dual

AUXIN to AUXOUT with two switches
on for dual

I

OS(3.3VOUT)

I

OS(1.5VOUT)

I

OS(AUXOUT)

Trip point, T

Hysteresis 10

From short to the 1stthreshold within 1.1
times of final current limit, TJ= 25°C

I(1.5VIN)

(steady-state value) 1.35 2 2.5 A
(steady-state value) TJ(–40, 120°C]. Output powered into a short 0.67 1 1.3 A

(steady-state value) 275 450 600 mA

J

= 1.5 V, V

, V

I(/SHDNx)

TJ= 25°C, I = 1300 mA each 45
TJ= 100°C, I = 1300 mA each 68
TJ= 25°C, I = 650 mA each 46
TJ= 100°C, I = 650 mA each 70
TJ= 25°C, I = 275 mA each 120
TJ= 100°C, I = 275 mA each 200

= 0 V, I

I(/SHDNx)

Rising temperature, not in overcurrent condition 155 165
Overcurrent condition 120 130

V

O(3.3VOUT)

V

O(1.5VOUT)

V

O(1.5VOUT)

V

O(AUXOUT)

= 3.3 V, V

I(/STBYx)

= 1 mA 100 500 Ω

(discharge)

with 100-mΩ short 43 100
with 100-mΩ short, TPS2231 100 140
with 100-mΩ short, TPS2236 110 150
with 100-mΩ short 38 100

I(/CPPEx)

= V

I(/CPUSBx)

= 0 V,

mΩ

mΩ

mΩ

°C

μs

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

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TPS2231
TPS2236

SLVS536J –JULY 2004–REVISED SEPTEMBER 2009..................................................................................................................................................

ELECTRICAL CHARACTERISTICS (continued)

TJ= 25°C, V
V

I(/SYSRST)

I

I

I

I

I

lkg(FWD)

I

lkg(RVS)

LOGIC SECTION (SYSRST, SHDNx, STBYx, PERSTx, RCLKENx, OCx, CPUSBx, CPPEx)

= 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)

Operation input
quiescent current

Total input
quiescent current

Forward leakage present, discharge FETs are on); current measured
current at input pins, TJ= 120°C, includes RCLKEN pullup

Reverse leakage
current
(TPS2236 and
TPS2231)

Logic input
supply current

Logic input
voltage

RCLEN output low voltage Output I

PERST assertion threshold of output voltage (PERST
asserted when any output voltage falls below the threshold)

PERST assertion delay from output voltage 3.3VOUT, AUXOUT, or 1.5VOUT falling 500 ns

I(3.3VIN)

= V

I(AUXIN)

= 3.3 V, V

I(1.5VIN)

= 1.5 V, V

I(/SHDNx)

, V

I(/STBYx)

= 3.3 V, V

I(/CPPEx)

= V

I(/CPUSBx)

= 0 V,

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Normal operation of
TPS2236

Normal operation of
TPS2231

Normal operation of
TPS2236

Normal operation of
TPS2231

Shutdown mode of
TPS2236

Shutdown mode of
TPS2231

TPS2236 I

TPS2231 I

I

I(AUXOUT)

I

I(3.3VOUT)

I

I(1.5VOUT)

I

I(AUXIN)

I

I(3.3VIN)

I

I(1.5VIN)

I

I(AUXIN)

I

I(3.3VIN)

I

I(1.5VIN)

I

I(AUXIN)

I

I(3.3VIN)

I

I(1.5VIN)

I

I(AUXIN)

I

I(3.3VIN)

I

I(1.5VIN)

I

I(AUXIN)

I

I(3.3VIN)

I

I(1.5VIN)

I

I(AUXIN)

I

I(3.3VIN)

I

I(1.5VIN)

I

I(AUXIN)
I(3.3VIN)

I

I(1.5VIN)

I

I(AUXIN)
I(3.3VIN)

I

I(1.5VIN)

Outputs are unloaded,
TJ[–40, 120°C] (does not include CPPEx and
CPUSBx logic pullup currents)

Outputs are unloaded, TJ[–40, 120°C] (include
CPPEx and CPUSBx logic pullup currents)

CPUSB = CPPE = 0 V SHDN = 0 V (discharge
FETs are on) (include CPPEx and CPUSBx logic
pullup currents and SHDN pullup current) TJ[–40,
120°C]

SHDN = 3.3 V, CPUSB = CPPE = 3.3 V (no card

current

TJ= 25°C 0.1 10
TJ= 120°C 50

V

TJ= 25°C 0.1 10
TJ= 120°C 50

O(AUXOUT)

V

O(1.5VOUT)

(current measured from output pins going in)

= V
= 1.5 V; All voltage inputs are grounded

O(3.3VOUT)

= 3.3 V;

TJ= 25°C 0.1 10
TJ= 120°C 50

125 200

17.5 25 μA

5.5 15
85 150
10 15 μA

2.5 10

200 320

17.5 25 μA

5.5 15

120 210

10 15 μA

2.5 10

250 440

3.5 20 μA

0.1 20

144 270

3.5 10 μA

0.5 10
40 100

0.1 100 μA

0.1 100
20 50

0.1 50 μA

0.1 50

SYSRST = 3.6 V, sinking 0 1

I

(SYSRST)

I

(SHDNx)

I

(STBYx)

I

(RCLKENx)

I

(CPUSBx)

I

(CPPEx)

or

Input TPS2231-2 0 1 μA

Input μA

Input μA

SYSRST = 0 V, sourcing

TPS2231, TPS2231-1 10 30
SHDNx = 3.6 V, sinking 0 1
SHDNx = 0 V, sourcing 10 30
STBYx = 3.6 V, sinking 0 1
STBYx = 0 V, sourcing 10 30

Input RCLKENx = 0 V, sourcing 10 30 μA

Inputs μA

CPUSB or CPPE = 0 V, sinking 0 1
CPUSB or CPPE = 3.6 V, sourcing 10 30

High level 2
Low level 0.8

O(RCLKEN)

= 60 μA 0.4 V

3.3VOUT falling 2.7 3
AUXOUT falling 2.7 3 V

1.5VOUT falling 1.2 1.35

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μA

μA

μA

V

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.................................................................................................................................................. SLVS536J –JULY 2004–REVISED SEPTEMBER 2009

ELECTRICAL CHARACTERISTICS (continued)

TJ= 25°C, V
V

I(/SYSRST)

t

W(PERST)

UNDERVOLTAGE LOCKOUT (UVLO)

= 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)

PERST de-assertion delay from output voltage 4 10 20 ms
PERST assertion delay from SYSRST Max time from SYSRST asserted or de-asserted 500 ns
PERST minimum pulse width 100 250 μs
PERST output low voltage 0.4 V

PERST output high voltage 2.4 V
OC output low voltage I
OC leakage current V
OC deglitch Falling into or out of an overcurrent condition 6 20 mS

3.3VIN UVLO 2.6 2.9

1.5VIN UVLO 1 1.25

AUXIN UVLO AUXIN level, below which all switches are off 2.6 2.9
UVLO hysteresis 100 mV

I(3.3VIN)

= V

= 3.3 V, V

I(AUXIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I(1.5VIN)

= 1.5 V, V

I(/SHDNx)

3.3VOUT, AUXOUT, and 1.5VOUT rising within
tolerance

3.3VOUT, AUXOUT, or 1.5VOUT falling out of
tolerance or triggered by SYSRST

I

3.3VIN level, below which 3.3VIN and 1.5VIN
switches are off

3.3VIN level, below which 3.3VIN switch is off
(TPS2231-3 only)

1.5VIN level, below which 3.3VIN and 1.5VIN V
switches are off

1.5VIN level, below which 1.5VIN switch is off
(TPS2231-3 only)

, V

= 500 μA

O(PERST)

= 2 mA 0.4 V

O(/OC)

= 3.6 V 1 μA

O(/OC)

I(/STBYx)

= 3.3 V, V

I(/CPPEx)

= V

I(/CPUSBx)

= 0 V,

TPS2231
TPS2236

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TPS2231
TPS2236

SLVS536J –JULY 2004–REVISED SEPTEMBER 2009..................................................................................................................................................

SWITCHING CHARACTERISTICS

TJ= 25°C, V
V

I(/SYSRST)

t

r

t

f

t

f

t

pd(on)

t

pd(off)

= 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)

Output rise times ms

Output fall times
when card removed
(both CPUSB and
CPPE de-asserted)

Output fall times
when SHDN
asserted (card is
present)

Turn-on propagation
delay

Turn-off propagation
delay

I(3.3VIN)

= V

I(AUXIN)

= 3.3 V, V

I(1.5VIN)

= 1.5 V, V

I(/SHDNx)

, V

I(/STBYx)

= 3.3 V, V

I(/CPPEx)

= V

I(/CPUSBx)

= 0 V,

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

3.3VIN to 3.3VOUT C
AUXIN to AUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to AUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

3.3VIN to 3.3VOUT C
AUXIN to VAUXOUT C

1.5VIN to 1.5VOUT C

L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)
L(3.3VOUT)
L(AUXOUT)
L(1.5VOUT)

= 0.1 μF, I
= 0.1 μF, I
= 0.1 μF, I

O(3.3VOUT)
O(AUXOUT)
O(1.5VOUT)

= 100 μF, RL= V
= 100 μF, RL= V
= 100 μF, RL= V
= 0.1 μF, I
= 0.1 μF, I
= 0.1 μF, I
= 20 μF, I
= 20 μF, I
= 20 μF, I
= 0.1 μF, I
= 0.1 μF, I
= 0.1 μF, I

O(3.3VOUT)
O(AUXOUT)

O(1.5VOUT)
O(3.3VOUT)
O(AUXOUT)
O(1.5VOUT)

O(3.3VOUT)

O(AUXOUT)

O(1.5VOUT)

= 100 μF, RL= V
= 100 μF RL= V
= 100 μF, RL= V
= 0.1 μF, I
= 0.1 μF, I
= 0.1 μF, I

O(3.3VOUT)

O(AUXOUT)

O(1.5VOUT)

= 100 μF, RL= V
= 100 μF, RL= V
= 100 μF, RL= V
= 0.1 μF, I
= 0.1 μF, I
= 0.1 μF, I

O(3.3VOUT)

O(AUXOUT)

O(1.5VOUT)

= 100 μF, RL= V
= 100 μF, RL= V
= 100 μF, RL= V

= 0 A 0.1 3
= 0 A 0.1 3
= 0 A 0.1 3

/1 A 0.1 6

I(3.3VIN)

/0.250 A 0.1 6

I(AUXIN)

/0.500 A 0.1 6

I(1.5VIN)

= 0 A 10 150
= 0 A 10 150 μs

= 0 A 10 150
= 0 A 2 30
= 0 A 2 30 ms
= 0 A 2 30

= 0 A 10 150

= 0 A 10 150 μs

= 0 A 10 150

/1 A 0.1 5

I(3.3VIN)

/0.250 A 0.1 5 ms

I(AUXIN)

/0.500 A 0.1 5

I(1.5VIN)

= 0 A 0.1 1

= 0A 0.05 0.5

= 0 A 0.1 1

/1 A 0.1 1.5

I(3.3VIN)

/0.250 A 0.05 1

I(AUXIN)

/0.500 A 0.1 1.5

I(1.5VIN)

= 0 A 0.1 1.5

= 0 A 0.05 0.5

= 0 A 0.1 1.5

/1 A 0.1 1.5

I(3.3VIN)

/0.250 A 0.05 0.5

I(AUXIN)

/0.500 A 0.1 1

I(1.5VIN)

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ms

ms

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1
2
3

4
5
6
7
8
9

10
11
12

24
23
22

21
20
19
18
17
16

15
14
13

NC

SYSRST

SHDN

STBY

3.3VIN

3.3VIN

3.3VOUT

3.3VOUT
PERST

NC

GND

NC

NC
OC
RCLKEN
AUXIN
AUXOUT

1.5VIN

1.5VIN

1.5VOUT

1.5VOUT
CPPE
CPUSB
NC

TPS2231

PWP PACKAGE

(TOP VIEW)

NC-Nointernalconnection

1
2
3

4
5
6
7
8
9

10

20
19
18

17
16
15
14
13
12

11

SYSRST

SHDN

STBY

3.3VIN

3.3VIN

3.3VOUT

3.3VOUT
PERST

NC

GND

OC
RCLKEN
AUXIN
AUXOUT

1.5VIN

1.5VIN

1.5VOUT

1.5VOUT
CPPE
CPUSB

TPS2231

PWPACKAGE

(TOP VIEW)

1
2
3

4
5
6
7
8
9

10
11
12
13
14
15
16

32
31
30

29
28
27
26
25
24

23
22
21
20
19
18
17

CPPE1
CPPE2

CPUSB1

NC
NC

CPUSB2

3.3VOUT1

3.3VIN

3.3VIN

3.3VOUT2
PERST2

NC

PERST1

AUXOUT1

AUXIN

AUXOUT2

RCLKEN1
RCLKEN2
SYSRST
NC
STBY1
STBY2

1.5VOUT1

1.5VIN

1.5VIN

1.5VOUT2
NC
GND
OC2
OC1
SHDN2
SHDN1

TPS2236

DAP PACKAGE

(TOP VIEW)

TPS2231

RGP PACKAGE

(TOP VIEW)

NC

NC

3.3VIN

3.3VOUT

1.5VIN

AUXOUT

NC

NC

1.5VOUT

SHDN

OC

RCLKEN

AUXIN

NC

SYSRST

GND

PERST

CPUSB

CPPE

STBY

1

2

3

4

5

15

14

13

12

11

6 7 8 9 10

1617181920

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TPS2231
TPS2236

.................................................................................................................................................. SLVS536J –JULY 2004–REVISED SEPTEMBER 2009

PIN ASSIGNMENTS

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TPS2231
TPS2236

SLVS536J –JULY 2004–REVISED SEPTEMBER 2009..................................................................................................................................................

TERMINAL FUNCTIONS

TERMINAL

TPS2231 TPS2236

NAME NO. NAME NO.

PW PWP RGP DAP

3.3VIN 4, 5 5, 6 2 3.3VIN 8, 9 I 3.3-V input for 3.3VOUT

1.5VIN 15, 16 18, 19 12 1.5VIN 24, 25 I 1.5-V input for 1.5VOUT
AUXIN 18 21 17 AUXIN 15 I AUX input for AUXOUT and chip power

GND 10 11 7 GND 21 Ground

3.3VOUT 6, 7 7, 8 3 3.3VOUT1 7 O

1.5VOUT 13, 14 16, 17 11 1.5VOUT1 26 O

AUXOUT 17 20 15 AUXOUT1 14 O

3.3VOUT2 10 O

1.5VOUT2 23 O

AUXOUT2 16 O

SYSRST 1 2 6 SYSRST 30 I

CPPE 12 15 10 CPPE1 1 I

CPUSB 11 14 9 CPUSB1 3 I Card Present input for USB cards. Internally pulled up to AUXIN.

CPPE2 2 I

CPUSB2 6 I Card Present input for USB cards. Internally pulled up to AUXIN.

PERST 8 9 8 PERST1 13 O A logic level power good to slot 0 (with delay)

PERST2 11 O A logic level power good to slot 1 (with delay)

SHDN 2 3 20 SHDN1 17 I

SHDN2 18 I

STBY 3 4 1 STBY1 28 I

STBY2 27 I

RCLKEN 19 22 18 RCLKEN1 32 I/O

RCLKEN2 31 I/O

OC 20 23 19 OC1 19 O Overcurrent status output for slot 0 (open drain)

OC2 20 O Overcurrent status output for slot 1 (open drain)

1, 10, 4, 5, 4, 5,

NC 9 12, 13, 13, 14, NC 12, 22, No connection

24 16 29

I/O DESCRIPTION

Switched output that delivers 0 V, 3.3 V or high impedance to
card

Switched output that delivers 0 V, 1.5 V or high impedance to
card

Switched output that delivers 0 V, AUX or high impedance to
card

Switched output that delivers 0 V, 3.3 V or high impedance to
card

Switched output that delivers 0 V, 1.5 V or high impedance to
card

Switched output that delivers 0 V, AUX or high impedance to
card

System Reset input – active low, logic level signal. Internally
pulled up to AUXIN.

Card Present input for PCI Express cards. Internally pulled up to
AUXIN

Card Present input for PCI Express cards. Internally pulled up to
AUXIN.

Shutdown input – active low, logic level signal. Internally pulled
up to AUXIN.

Shutdown input – active low, logic level signal. Internally pulled
up to AUXIN.

Standby input – active low, logic level signal. Internally pulled up
to AUXIN.

Standby input – active low, logic level signal. Internally pulled up
to AUXIN.

Reference Clock Enable signal. As an output, a logic level power
good to host for slot 0 (no delay – open drain). As an input, if
kept inactive (low) by the host, prevents PERST from being
de-asserted. Internally pulled up to AUXIN.

Reference Clock Enable signal. As an output, a logic level power
good to host for slot 1 (no delay – open drain). As an input, if
kept inactive (low) by the host, prevents PERST from being
de-asserted. Internally pulled up to AUXIN.

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PG CS

S1

S4

PG CS

S2

S5

PG CS

S3

S6

CurrentLimit

ThermalLimit

Control

Logic

UVLO

POR

FAULT

AUXIN

Delay

PWR_GOOD_ALL

3.3VOUT

AUXOUT

1.5VOUT

OC

RCLKEN

PERST

SYSRST

3.3VIN

AUXIN

1.5VIN

CPUSB

CPPE

STBY

SHDN

GND

AUXIN

Note A:PG=powergood
NoteB:CS=currentsense
NoteC:TPS2231MRGP-2doesnothaveapull-upresistor.

(Note A)

(NoteC)

(NoteB)

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.................................................................................................................................................. SLVS536J –JULY 2004–REVISED SEPTEMBER 2009

FUNCTIONAL BLOCK DIAGRAM

Single ExpressCard Power Switch

TPS2231
TPS2236

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PG1 CS

S1

S4

S2

S5

S3

S6

Current Limit

Thermal Limit

Control

Logic

UVLO

POR

CHANNEL-1

FAULT

AUXIN

Delay

PWR_GOOD_ALL_2

3.3VOUT1

AUXOUT1

1.5 VOUT1

OC1

RCLKEN1

PERST1
SYSRST

3.3VIN

AUXIN

1.5VIN

CPUSB1

CPPE1

STBY1

SHDN1

GND

S7

S10

S8

S11

S9

S12

3.3VOUT2

AUXOUT2

1.5VOUT2

Delay

PWR_GOOD_ALL_1

CHANNEL-2

FAULT

RCLKEN2

PERST2
OC2

CPUSB2

CPPE2

STBY2

SHDN2

PG1 CS

PG1 CS

PG2 CS

PG2 CS

PG2 CS

TPS2231
TPS2236

SLVS536J –JULY 2004–REVISED SEPTEMBER 2009..................................................................................................................................................

Dual ExpressCard Power Switch

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CPPE

A logic low level on this input indicates that the card present supports PCI Express functions. CPPE connects to
the AUXIN input through an internal pullup. When a card is inserted, CPPE is physically connected to ground if
the card supports PCI Express functions.

CPUSB

A logic low level on this input indicates that the card present supports USB functions. CPUSB connects to the
AUXIN input through an internal pullup. When a card is inserted, CPUSB is physically connected to ground if the
card supports USB functions.

SHDN

When asserted (logic low), this input instructs the power switch to turn off all voltage outputs and the discharge
FETs are activated. SHDN has an internal pullup connected to AUXIN.

STBY

When asserted (logic low) after the card is inserted, this input places the power switch in standby mode by
turning off the 3.3-V and 1.5-V power switches and keeping the AUX switch on. If asserted prior to the card being
present, STBY places the power switch in OFF Mode by turning off the AUX, 3.3-V, and 1.5-V power switches.
STBY has an internal pullup connected to AUXIN.

.................................................................................................................................................. SLVS536J –JULY 2004–REVISED SEPTEMBER 2009

DETAILED PIN DESCRIPTIONS

RCLKEN

This pin serves as both an input and an output. On power up, a discharge FET keeps this signal at a low state as
long as any of the output power rails are out of their tolerance range. Once all output power rails are within
tolerance, the switch releases RCLKEN allowing it to transition to a high state (internally pulled up to AUXIN).
The transition of RCLKEN from a low to a high state starts an internal timer for the purpose of deasserting
PERST. As an input, RCLKEN can be kept low to delay the start of the PERST internal timer.

Because RCLKEN is internally connected to a discharge FET, this pin can only be driven low and should never
be driven high as a logic input. When an external circuit drives this pin low, RCLKEN becomes an input;
otherwise, this pin is an output.

RCLKEN can be used by the host system to enable a clock driver.

PERST

On power up, this output remains asserted (logic level low) until all power rails are within tolerance. Once all
power rails are within tolerance and RCLKEN has been released (logic high), PERST is deasserted (logic high)
after a time delay as shown in the parametric table. On power down, this output is asserted whenever any of the
power rails drop below their voltage tolerance.

The PERST signal is an output from the host system and an input to the ExpressCard module. This signal is only
used by PCI Express-based modules and its function is to place the ExpressCard module in a reset state.

During power up, power down, or whenever power to the ExpressCard module is not stable or not within voltage
tolerance limits, the ExpressCard standard requires that PERST be asserted. As a result, this signal also serves
as a power-good indicator to the ExpressCard module, and the relationship between the power rails and PERST
are explicitly defined in the ExpressCard standard.

The host can also place the ExpressCard module in a reset state by asserting a system reset SYSRST. This
system reset generates a PERST to the ExpressCard module without disrupting the voltage rails. This is what is
normally called a warm reset. However, in a cold start situation, the system reset can also be used to extend the
length of time that PERST is asserted.

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SLVS536J –JULY 2004–REVISED SEPTEMBER 2009..................................................................................................................................................

SYSRST

This input is driven by the host system and directly affects PERST. Asserting SYSRST (logic low) forces PERST
to assert. RCLKEN is not affected by the assertion of SYSRST. SYSRST has an internal pullup connected to
AUXIN.

OC

This pin is an open-drain output. When any of the three power switches (AUX, 3.3V, and 1.5V) is in an
overcurrent condition, OC is asserted (logic low) by an internal discharge FET with a deglitch delay. Otherwise,
the discharge FET is open, and the pin can be pulled up to a power supply through an external resistor.

FUNCTIONAL TRUTH TABLES

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VOLTAGE INPUTS

AUXIN 3.3VIN 1.5VIN SHDN STBY CP

Off x x x x x Off Off Off OFF
On x x 0 x x GND GND GND Shutdown
On x x 1 x 1 GND GND GND No Card
On On On 1 0 0 On Off Off Standby
On On On 1 1 0 On On On Card Inserted

(1) For input voltages, On means the respective input voltage is higher than its turnon threshold voltage; otherwise, the voltage is Off (for

AUX input,Off means the voltage is close to zero volt).

(2) For output voltages, On means the respective power switch is turned on so the input voltage is connected to the output; Off means the

power switch and its output discharge FET are both off; GND means the power switch is off but the output discharge FET is on so the
voltage on the output is pulled down to 0 V.

(3) Mode assigns each set of input conditions and respective output voltage results to a different name. These modes are referred to as

input conditions in the following Truth Table for Logic Outputs.

(4) CP = CPUSB and CPPE – equal to 1 when both CPUSB and CPPE signals are logic high, or equal to 0 when either CPUSB or CPPE is

low.

(1)

LOGIC INPUTS VOLTAGE OUTPUTS

(4)

AUXOUT 3.3VOUT 1.5VOUT

(2)

MODE

(3)

Truth Table for Logic Outputs

INPUT CONDITIONS LOGIC OUTPUTS

Truth Table for Voltage Outputs

MODE SYSRST RCLKEN

OFF

Shutdown

No Card
Standby

Card Inserted

(1) RCLKEN as a logic input in this column. RCLKEN is an I/O pin and it can be driven low externally, left open, or connected to

high-impedance terminals, such as the gate of a MOSFET. It must not be driven high externally.

(2) RCLKEN as a logic output in this column.

X X 0 0

0 Hi-Z 0 1
0 0 0 0
1 Hi-Z 1 1
1 0 0 0

(1)

PERST RCLKEN

(2)

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POWER STATES

If AUXIN is not present, then all input-to-output power switches are kept off (OFF mode).
If AUXIN is present and SHDN is asserted (logic low), then all input-to-output power switches are kept off and the

output discharge FETs are turned on (Shutdown mode). If SHDN is asserted and then de-asserted, the state on
the outputs is restored to the state prior to SHDN assertion.

If 3.3VIN, AUXIN and 1.5VIN are present at the input of the power switch and no card is inserted, then all
input-to-output power switches are kept off and the output discharge FETs are turned on (No Card mode).

If 3.3VIN, AUXIN and 1.5VIN are present at the input of the power switch prior to a card being inserted, then all
input-to-output power switches are turned on once a card-present signal (CPUSB and/or CPPE) is detected
(Card Inserted mode).

If a card is present and all output voltages are being applied, then the STBY is asserted (logic low); the AUXOUT
voltage is provided to the card, and the 3.3VOUT and 1.5VOUT switches are turned off (Standby mode).

If a card is present and all output voltages are being applied, then the 1.5VIN, or 3.3VIN is removed from the
input of the power switch; the AUXOUT voltage is provided to the card and the 3.3VOUT and 1.5VOUT switches
are turned off (Standby mode). TPS2231-3 only: If 3.3VIN is removed, the 3.3VOUT switch is turned off; and, the

1.5VOUT switch is unaffected. If 1.5VIN is removed, the 1.5VOUT switch is turned off; and, the 3.3VOUT switch
is unaffected.

If prior to the insertion of a card, the AUXIN is available at the input of the power switch and 3.3VIN and/or

1.5VIN are not, or if STBY is asserted (logic low), then no power is made available to the card (OFF mode). If

1.5VIN and 3.3VIN are made available at the input of the power switch after the card is inserted and STBY is not
asserted, all the output voltages are made available to the card (Card Inserted mode). TPS2231-3 only: If 1.5VIN
or 3.3VIN is made available at the input of the power switch after the card is inserted and STBY is not asserted,
all switches above their individual UVLO thresholds will turn on.

.................................................................................................................................................. SLVS536J –JULY 2004–REVISED SEPTEMBER 2009

DISCHARGE FETs

The discharge FETs on the outputs are activated whenever the device detects that a card is not present (No
Card mode). Activation occurs after the input-to-output power switches are turned off (break before make). The

discharge FETs de-activate if either of the card-present lines go active low, unless the SHDN pin is asserted.
The discharge FETs are also activated whenever the SHDN input is asserted and stay asserted until SHDN is

de-asserted.

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