TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
D
80-mΩ High-Side MOSFET Switch
D
500 mA Continuous Current Per Channel
D
Independent Thermal and Short-Circuit
Protection With Overcurrent Logic Output
D
Operating Range . . . 2.7 V to 5.5 V
D
CMOS- and TTL-Compatible Enable Inputs
D
2.5-ms Typical Rise Time
D
Undervoltage Lockout
D
10 µA Maximum Standby Supply Current
for Single and Dual (20 µA for Triple and
Quad)
D
Bidirectional Switch
D
Ambient Temperature Range, 0°C to 85°C
D
ESD Protection
D
UL Listed – File No. E169910
description
The TPS2041A through TPS2044A and
TPS2051A through TPS2054A power-distribution
switches are intended for applications where
TPS2041A, TPS2051A
D PACKAGE
(TOP VIEW)
GND
GNDA
GNDB
†
NC – No connect
1
IN
2
3
IN
†
4
EN
TPS2043A, TPS2053A
D PACKAGE
(TOP VIEW)
1
IN1
2
†
EN1
EN2
EN3
All enable inputs are active high for the TPS205xA series.
IN2
NC
3
†
4
5
6
†
7
8
OUT
8
OUT
7
6
OUT
5
OC
OC1
16
OUT1
15
OUT2
14
OC2
13
OC3
12
OUT3
11
10
NC
9
NC
TPS2042A, TPS2052A
D PACKAGE
(TOP VIEW)
GND
EN1
EN2
GNDA
EN1
EN2
GNDB
EN3
EN4
1
IN
2
†
3
†
4
TPS2044A, TPS2054A
D PACKAGE
(TOP VIEW)
1
IN1
2
†
3
†
4
5
IN2
6
†
7
†
8
heavy capacitive loads and short circuits are likely to be encountered. These devices incorporate 80-mΩ
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches in a single package. Each switch is controlled by an independent logic enable input. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
16
15
14
13
12
10
OC1
8
OUT1
7
OUT2
6
5
OC2
OC1
OUT1
OUT2
OC2
OC3
OUT3
11
OUT4
9
OC4
When the output load exceeds the current-limit threshold or a short is present, these devices limit the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx
) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present. These power-distribution switches are designed to current limit
at 0.9 A.
GENERAL SWITCH CATALOG
33 mΩ, single
80 mΩ, single
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPS201xA
TPS202x
TPS203x
TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
0.2 A – 2 A
0.2 A – 2 A
0.2 A – 2 A
600 mA
1 A
500 mA
500 mA
250 mA
250 mA
80 mΩ, dual
260 mΩ
IN1
IN2
1.3 Ω
OUT
TPS2042
TPS2052
TPS2046
TPS2056
TPS2100/1
IN1 500 mA
IN2 10 mA
TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
500 mA
500 mA
250 mA
250 mA
80 mΩ, dual
TPS2080
TPS2081
TPS2082
TPS2090
TPS2091
TPS2092
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
80 mΩ, triple
TPS2043
TPS2053
TPS2047
TPS2057
500 mA
500 mA
250 mA
250 mA
Copyright 2000, Texas Instruments Incorporated
80 mΩ, quad
TPS2044
TPS2054
TPS2048
TPS2058
500 mA
500 mA
250 mA
250 mA
TPS2085
TPS2086
TPS2087
TPS2095
TPS2096
TPS2097
80 mΩ, quad
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TPS2041A, TPS2042A, TPS2043A, TPS2044A
MAXIMUM CONTINUOUS
NUMBER OF
Single
Dual
0°C to 85°C
0.5
0.9
Triple
Quad
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
AVAILABLE OPTIONS
RECOMMENDED
T
A
°
†
The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2041ADR)
°
ENABLE
Active low
Active high
Active low
Active high
Active low
Active high
Active low
Active high
LOAD CURRENT
(A)
TYPICAL SHORT-CIRCUIT
CURRENT LIMIT AT 25°C
(A)
SWITCHES
p
PACKAGED DEVICES
SOIC
†
(D)
TPS2041AD
TPS2051AD
TPS2042AD
TPS2052AD
TPS2043AD
TPS2053AD
TPS2044AD
TPS2054AD
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
TPS2041A
IN
Charge
Pump
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
Power Switch
†
CS
OUT
TPS2042A
‡
EN
UVLO
GND
†
Current sense
‡
Active high for TPS205xA series
GND
‡
EN1
Charge
Pump
UVLO
Thermal
Sense
Driver
Driver
Thermal
Sense
Current
Limit
Power Switch
CS
Current
Limit
OC
OC1
†
OUT1
IN
Charge
Pump
‡
EN2
†
Current sense
‡
Active high for TPS205xA series
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Driver
Thermal
Sense
CS
Current
Limit
†
OUT2
OC2
3
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
functional block diagrams
TPS2043A
OC1
GNDA
EN1
IN1
EN2
Thermal
Sense
‡
Driver
Charge
Pump
UVLO
Power Switch
Charge
Pump
Driver
‡
Thermal
Sense
Current
Limit
CS
CS
Current
Limit
†
OUT1
†
OUT2
OC2
IN2
Charge
Pump
‡
EN3
UVLO
GNDB
†
Current sense
‡
Active high for TPS205xA series
Power Switch
Driver
Thermal
Sense
CS
Current
Limit
†
OUT3
OC3
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
TPS2044A
GNDA
EN1
IN1
EN2
OC1
Thermal
Sense
‡
Driver
Charge
Pump
UVLO
Charge
Pump
Driver
‡
Thermal
Sense
Current
Limit
CS
Power Switch
CS
Current
Limit
†
OUT
1
†
OUT
2
OC2
GNDB
‡
EN3
Charge
Pump
IN2
Charge
Pump
‡
EN4
†
Current sense
‡
Active high for TPS205xA series
UVLO
Thermal
Sense
Driver
Driver
Thermal
Sense
Current
Limit
CS
Power Switch
CS
Current
Limit
OC3
†
OUT3
†
OUT4
OC4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPS2041A, TPS2042A, TPS2043A, TPS2044A
NAME
NAME
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
Terminal Functions
TPS2041A and TPS2051A
TERMINAL
NO.
TPS2041A TPS2051A
EN 4 – I Enable input. Logic low turns on power switch.
EN – 4 I Enable input. Logic high turns on power switch.
GND 1 1 I Ground
IN 2, 3 2, 3 I Input voltage
OC 5 5 O Overcurrent. Logic output active low
OUT 6, 7, 8 6, 7, 8 O Power-switch output
TPS2042A and TPS2052A
TERMINAL
NO.
TPS2042A TPS2052A
EN1 3 – I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 – 3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND 1 1 I Ground
IN 2 2 I Input voltage
OC1 8 8 O Overcurrent. Logic output active low, for power switch, IN-OUT1
OC2 5 5 O Overcurrent. Logic output active low, for power switch, IN-OUT2
OUT1 7 7 O Power-switch output
OUT2 6 6 O Power-switch output
I/O DESCRIPTION
I/O DESCRIPTION
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NAME
NAME
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
Terminal Functions (Continued)
TPS2043A and TPS2053A
TERMINAL
NO.
TPS2043A TPS2053A
EN1 3 – I Enable input, logic low turns on power switch, IN1-OUT1.
EN2 4 – I Enable input, logic low turns on power switch, IN1-OUT2.
EN3 7 – I Enable input, logic low turns on power switch, IN2-OUT3.
EN1 – 3 I Enable input, logic high turns on power switch, IN1-OUT1.
EN2 – 4 I Enable input, logic high turns on power switch, IN1-OUT2.
EN3 – 7 I Enable input, logic high turns on power switch, IN2-OUT3.
GNDA 1 1 Ground for IN1 switch and circuitry.
GNDB 5 5 Ground for IN2 switch and circuitry.
IN1 2 2 I Input voltage
IN2 6 6 I Input voltage
NC 8, 9, 10 8, 9, 10 No connection
OC1 16 16 O Overcurrent, logic output active low, IN1-OUT1
OC2 13 13 O Overcurrent, logic output active low, IN1-OUT2
OC3 12 12 O Overcurrent, logic output active low, IN2-OUT3
OUT1 15 15 O Power-switch output, IN1-OUT1
OUT2 14 14 O Power-switch output, IN1-OUT2
OUT3 11 11 O Power-switch output, IN2-OUT3
I/O DESCRIPTION
SLVS247 – SEPTEMBER 2000
TPS2044A and TPS2054A
TERMINAL
NO.
TPS2044A TPS2054A
EN1 3 – I Enable input. logic low turns on power switch, IN1-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN1-OUT2.
EN3 7 – I Enable input. Logic low turns on power switch, IN2-OUT3.
EN4 8 – I Enable input. Logic low turns on power switch, IN2-OUT4.
EN1 – 3 I Enable input. Logic high turns on power switch, IN1-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN1-OUT2.
EN3 – 7 I Enable input. Logic high turns on power switch, IN2-OUT3.
EN4 – 8 I Enable input. Logic high turns on power switch, IN2-OUT4.
GNDA 1 1 Ground for IN1 switch and circuitry.
GNDB 5 5 Ground for IN2 switch and circuitry.
IN1 2 2 I Input voltage
IN2 6 6 I Input voltage
OC1 16 16 O Overcurrent. Logic output active low, IN1-OUT1
OC2 13 13 O Overcurrent. Logic output active low, IN1-OUT2
OC3 12 12 O Overcurrent. Logic output active low, IN2-OUT3
OC4 9 9 O Overcurrent. Logic output active low, IN2-OUT4
OUT1 15 15 O Power-switch output, IN1-OUT1
OUT2 14 14 O Power-switch output, IN1-OUT2
OUT3 11 11 O Power-switch output, IN2-OUT3
OUT4 10 10 O Power-switch output, IN2-OUT4
I/O DESCRIPTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TPS2041A, TPS2042A, TPS2043A, TPS2044A
†
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (V
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled. The power switch supplies a minimum of 500 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 10 µA on the single and dual devices (20 µA on
the triple and quad devices) when a logic high is present on ENx
(TPS205xA†). A logic zero input on ENx or a logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
, ENx)
(TPS204xA†) or a logic low is present on ENx
open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
I(IN)
= 5 V).
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant-current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS204xA and TPS205xA implement a dual-threshold thermal trip to allow fully independent operation of
the power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.
Product series designations TPS204x and TPS205x refer to devices presented in this data sheet and not necessarily to other TI devices
numbered in this sequence.
) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, V
Output voltage range, V
Input voltage range, V
Continuous output current, I
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
Storage temperature range, T
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
PACKAGE
D–8 725 mW 5.9 mW/°C 464 mW 377 mW
D–16 1123 mW 9 mW/°C 719 mW 584 mW
(see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I(IN)
O(OUT)
I(ENx)
(see Note 1) –0.3 V to V
or V
I(ENx)
O(OUT)
J
stg
Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I(IN)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN MAX UNIT
Input voltage, V
Input voltage, V
Continuous output current, I
Operating virtual junction temperature, T
I(IN)
I(EN)
or V
I(EN)
O(OUT)
(per switch) 0 500 mA
J
2.7 5.5 V
0 5.5 V
0 125 °C
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TPS2041A, TPS2042A, TPS2043A, TPS2044A
PARAMETER
TEST CONDITIONS
†
UNIT
r
trRise time, output
ms
tfFall time, output
ms
PARAMETER
TEST CONDITIONS
UNIT
VILLow-level input voltage
IIInput current
A
PARAMETER
TEST CONDITIONS
†
UNIT
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
electrical characteristics over recommended operating junction temperature range, V
= rated current, V
I
O
I(EN)
= 0 V, V
I(EN)
= V
(unless otherwise noted)
I(IN)
I(IN)
= 5.5 V,
power switch
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
V
= 5 V,
I(IN)
IO = 0.5 A
Static drain-source on-state
resistance, 5-V operation
DS(on)
Static drain-source on-state
resistance, 3.3-V operation
p
p
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
V
= 5 V,
I(IN)
IO = 0.5 A
V
= 5 V,
I(IN)
IO = 0.5 A
V
= 3.3 V,
I(IN)
IO = 0.5 A
V
= 3.3 V,
I(IN)
IO = 0.5 A
V
= 3.3 V,
I(IN)
IO = 0.5 A
V
= 5.5 V,
I(IN)
CL = 1 µF,
V
= 2.7 V,
I(IN)
CL = 1 µF,
V
= 5.5 V,
I(IN)
CL = 1 µF,
V
= 2.7 V,
I(IN)
CL = 1 µF,
TJ = 25°C,
TJ = 85°C,
TJ = 125°C,
TJ = 25°C,
TJ = 85°C,
TJ = 125°C,
TJ = 25°C,
RL=10 Ω
TJ = 25°C,
RL=10 Ω
TJ = 25°C,
RL=10 Ω
TJ = 25°C,
RL=10 Ω
80 100 80 100
90 120 90 120
100 135 100 135
90 125 90 125
110 145 110 145
120 160 120 160
2.5 2.5
3 3
4.4 4.4
2.5 2.5
mΩ
enable input ENx or ENx
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
V
High-level input voltage 2.7 V ≤ V
IH
p
p
t
Turnon time CL = 100 µF, RL=10 Ω 20 20 ms
on
t
Turnoff time CL = 100 µF, RL=10 Ω 40 40
off
TPS204xA V
TPS205xA V
4.5 V ≤ V
2.7 V≤ V
I(ENx)
I(ENx)
≤ 5.5 V 2 2 V
I(IN)
≤ 5.5 V 0.8 0.8 V
I(IN)
≤ 4.5 V 0.4 0.4
I(IN)
= 0 V or V
= V
or V
I(IN)
I(ENx)
I(ENx)
= V
I(IN)
= 0 V –0.5 0.5
–0.5 0.5
µ
current limit
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
V
= 5 V, OUT connected to GND,
I
Short-circuit output current
OS
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
I(IN)
Device enabled into short circuit
0.7 1 1.3 0.7 1 1.3 A
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
y,
A
V
V
V
0 V
y,
A
V
V
Leakage current
d
A
Reverse leakage current
g
T
25°C
A
PARAMETER
TEST CONDITIONS
UNIT
y,
A
V
V
V
V
y,
A
V
V
Leakage current
d
A
Reverse leakage current
g
T
25°C
A
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
electrical characteristics over recommended operating junction temperature range, V
= rated current, V
I
O
supply current (TPS2041A, TPS2051A)
Supply current, low-level No Load
output on OUT
Supply current, No Load
high-level output on OUT
supply current (TPS2042A, TPS2052A)
Supply current, low-level No Load
output on OUT
Supply current, No Load
high-level output on OUT
= 0 V, V
I(EN)
OUT
connecte
to ground
IN = High
impedance
OUT
connecte
to ground
IN = high
impedance
= V
I(EN)
V
= V
I(EN)
I(EN)
I(EN)
I(EN)
V
I(EN
V
I(EN)
V
I(EN
V
I(EN)
V
I(ENx
I(ENx)
I(ENx)
I(ENx)
V
I(ENx)
V
I(ENx)
V
I(EN)
V
I(EN)
I(IN)
= 0
=
=
I(IN)
= V
)
I(IN)
= 0 V –40°C ≤ TJ ≤ 125°C 100
= 0 V
)
= V
I(IN)
= V
)
I(IN)
= 0
= 0
=
I(IN)
= V
I(IN)
= 0 V –40°C ≤ TJ ≤ 125°C 100
= 0 V
= V
I(IN)
(unless otherwise noted) (continued)
I(IN)
TPS2041A TPS2051A
MIN TYP MAX MIN TYP MAX
TJ = 25°C 0.025 1
–40°C ≤ TJ ≤ 125°C 10
TJ = 25°C 0.025 1
–40°C ≤ TJ ≤ 125°C 10
TJ = 25°C 85 110
–40°C ≤ TJ ≤ 125°C 100
TJ = 25°C 85 110
–40°C ≤ TJ ≤ 125°C 100
–40°C ≤ TJ ≤ 125°C 100
°
=
J
MIN TYP MAX MIN TYP MAX
TJ = 25°C 0.025 1
–40°C ≤ TJ ≤ 125°C 10
TJ = 25°C 0.025 1
–40°C ≤ TJ ≤ 125°C 10
TJ = 25°C 85 110
–40°C ≤ TJ ≤ 125°C 100
TJ = 25°C 85 110
–40°C ≤ TJ ≤ 125°C 100
–40°C ≤ TJ ≤ 125°C 100
°
=
J
0.3
TPS2042A TPS2052A
0.3
0.3
0.3
I(IN)
= 5.5 V,
µ
µ
µ
µ
µ
µ
µ
µ
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TPS2041A, TPS2042A, TPS2043A, TPS2044A
PARAMETER
TEST CONDITIONS
UNIT
y,
A
V
V
V
0 V
y,
A
V
V
Leakage current
A
g
g
T
25°C
A
TEST CONDITIONS
UNIT
y,
A
V
V
V
V
y,
A
V
V
Leakage current
A
g
g
T
25°C
A
PARAMETER
TEST CONDITIONS
UNIT
PARAMETER
TEST CONDITIONS
UNIT
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
electrical characteristics over recommended operating junction temperature range, V
= rated current, V
I
O
I(EN)
= 0 V, V
I(EN)
= V
(unless otherwise noted) (continued)
I(IN)
I(IN)
= 5.5 V,
supply current (TPS2043A, TPS2053A)
TPS2043A TPS2053A
MIN TYP MAX MIN TYP MAX
TJ = 25°C 0.05 2
I(INx)
–40°C ≤ TJ ≤ 125°C 20
TJ = 25°C 0.05 2
–40°C ≤ TJ ≤ 125°C 20
TJ = 25°C 160 200
–40°C ≤ TJ ≤ 125°C 200
TJ = 25°C 160 200
I(INx)
–40°C ≤ TJ ≤ 125°C 200
–40°C ≤ TJ ≤ 125°C 200
I(INx)
0.3
I(IN)
°
=
J
0.3
Supply current, No Load
low-level output on OUTx
Supply current, No Load
high-level output on OUTx
OUTx connected
to ground
Reverse leakage IN = high
current
impedance
V
= V
I(ENx)
= 0
I(ENx)
=
I(ENx)
=
I(ENx)
V
= V
I(ENx)
V
= 0 V –40°C ≤ TJ ≤ 125°C 200
I(ENx)
V
= 0 V
I(ENx
)
V
= V
I(ENx)
supply current (TPS2044A, TPS2054A)
PARA-
METER
Supply current, No Load
low-level output on OUTx
Supply current, No Load
high-level output on OUTx
OUTx connected
to ground
Reverse leakage IN = high
current
impedance
V
= V
I(ENx)
= 0
I(ENx)
= 0
I(ENx)
=
I(ENx)
V
= V
I(ENx
)
V
= 0 V –40°C ≤ TJ ≤ 125°C 200
I(ENx)
V
= 0 V
I(EN)
V
= V
I(EN)
I(IN)
TJ = 25°C 0.05 2
I(INx)
–40°C ≤ TJ ≤ 125°C 20
TJ = 25°C 0.05 2
–40°C ≤ TJ ≤ 125°C 20
TJ = 25°C 170 220
–40°C ≤ TJ ≤ 125°C 200
TJ = 25°C 170 220
I(INx)
–40°C ≤ TJ ≤ 125°C 200
–40°C ≤ TJ ≤ 125°C 200
I(INx)
°
=
J
TPS2044A TPS2054A
MIN TYP MAX MIN TYP MAX
0.3
0.3
undervoltage lockout
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV
µ
µ
µ
µ
µ
µ
µ
µ
overcurrent OC
Sink current
Output low voltage IO = 5 V, V
Off-state current
†
Specified by design, not production tested.
12
†
†
VO = 5 V 10 10 mA
OL(OC)
VO = 5 V, VO = 3.3 V 1 1 µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
0.5 0.5 V
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
OUT
V
I(EN)
(5 V/div)
V
V
O(OUT)
I(EN)
t
RL CL
V
O(OUT)
TEST CIRCUIT
50%
t
on
50%
90%
10%
V
I(EN)
t
off
V
O(OUT)
VOLTAGE WA VEFORMS
r
90%
90%
10%
50%
t
on
10%
50%
90%
10%
t
f
t
off
Figure 1. Test Circuit and Voltage Waveforms
V
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
V
= 5 V
I(IN)
TA = 25°C
CL = 0.1 µF
RL = 10 Ω
0123456
t – Time – ms
78910
Figure 2. Turnon Delay and Rise Time
with 0.1-µF Load
V
O(OUT)
(2 V/div)
V
= 5 V
I(IN)
TA = 25°C
CL = 0.1 µF
RL = 10 Ω
04812
2 6 10 14 18
t – Time – ms
16 20
Figure 3. Turnoff Delay and Fall Time
with 0.1-µF Load
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
V
V
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
0123456
t – Time – ms
V
= 5 V
I(IN)
TA = 25°C
CL = 1 µF
RL = 10 Ω
78910
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
V
= 5 V
I(IN)
TA = 25°C
CL = 1 µF
RL = 10 Ω
0 2 4 6 8 10 12
t – Time – ms
14 16 18 20
V
I(EN)
(5 V/div)
I
O(OUT)
(0.5 A/div)
Figure 4. Turnon Delay and Rise Time
with 1-µF Load
V
= 5 V
I(IN)
TA = 25°C
0123456
t – Time – ms
78910
Figure 6. TPS2051A, Short-Circuit Current,
Device Enabled into Short
V
O(OUT)
(2 V/div)
I
O(OUT)
(0.5 A/div)
Figure 5. Turnoff Delay and Fall Time
with 1-µF Load
V
= 5 V
I(IN)
TA = 25°C
01020 30405060
t – Time – ms
70 80 90 100
Figure 7. TPS2051A, Threshold Trip Current
with Ramped Load on Enabled Device
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
V
O(OC)
(5 V/div)
I
O(OUT)
(0.5 A/div)
Figure 8. OC Response With Ramped Load
V
O(OC)
(5 V/div)
V
I(IN)
TA = 25°C
Ramp = 1 A/100 ms
0 20 40 60 80 100 120
t – Time – ms
on Enabled Device
= 5 V
140 160 180 200
V
= 5 V
I(IN)
TA = 25°C
V
I(EN)
(5 V/div)
I
O(OUT)
(0.2 A/div)
V
O(OC)
(5 V/div)
470 µF
220 µF
100 µF
V
= 5 V
I(IN)
TA = 25°C
RL = 10 Ω
0 2 4 6 8 10 12
t – Time – ms
14 16 18 20
Figure 9. Inrush Current with 100-µF, 220-µF
and 470-µF Load Capacitance
V
= 5 V
I(IN)
TA = 25°C
I
O(OUT)
(0.5 A/div)
0 1000 2000 3000 4000 5000
t – Time – µs
Figure 10. 4-Ω Load Connected to Enabled Device
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
O(OUT)
(1 A/div)
0 200 400 600 800 1000
t – Time – µs
Figure 11. 1-Ω Load Connected
to Enabled Device
15
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
TYPICAL CHARACTERISTICS
TURNON DELAY TIME
3.5
3.2
2.9
2.6
Turnon Delay Time – ms
2.3
2
2.5 3 3.5 4 4.5
3
CL = 1 µF
RL = 10 Ω
TA = 25°C
2.7
vs
INPUT VOLTAGE
VI – Input Voltage – V
Figure 12
RISE TIME
vs
INPUT VOLTAGE
CL = 1 µF
RL = 10 Ω
TA = 25°C
5 5.5 6
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
12
CL = 1 µF
RL = 10 Ω
TA = 25°C
10
8
Turnon Delay Time – ms
6
4
2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V
Figure 13
FALL TIME
vs
INPUT VOLTAGE
2.2
CL = 1 µF
RL = 10 Ω
2.1
TA = 25°C
2
– Rise Time – ms
t
r
16
2.4
2.1
1.8
2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V
Figure 14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1.9
1.8
– Fall Time – ms
t
f
1.7
1.6
1.5
2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V
Figure 15
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
100
Aµ
90
V
80
V
I(IN)
70
60
V
= 3.3 V
– Supply Current, Output Enabled –
50
I(IN)
I
40
–40 0 25 85 125
I(IN)
TJ – Junction Temperature – °C
I(IN)
= 4.5 V
= 5 V
V
V
I(IN)
I(IN)
= 2.7 V
= 5.5 V
Figure 16
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
Ω
160
140
120
100
80
60
40
20
– Static Drain-Source On-State Resistance – m
0
0 25 85 125
DS(on)
r
JUNCTION TEMPERATURE
IO = 0.5 A
V
= 2.7 V
I(IN)
V
= 3 V
I(IN)
V
= 5 V
I(IN)
TJ – Junction Temperature –°C
V
I(IN)
V
I(IN)
= 4.5 V
= 3.3 V
Figure 18
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
160
140
120
100
80
V
V
I(IN)
60
40
– Supply Current, Output Disabled – nA
20
I(IN)
I
0
–40 0 25 85 125
TJ – Junction Temperature – °C
V
I(IN)
= 3.3 V
I(IN)
= 2.7 V
V
V
I(IN)
= 4.5 V
Figure 17
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
70
TA = 25°C
= 4.5 V
V
I(IN)
60
V
50
V
40
30
– Input-to-Output Voltage – mV
20
O(OUT)
V
–
10
I(IN)
V
0
100 200 300 400 500
I(IN)
= 3.3 V
I(IN)
IL – Load Current – A
Figure 19
I(IN)
= 5 V
= 2.7 V
V
I(IN)
= 5.5 V
= 5 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
1.2
V
= 5.5 V
1.1
V
= 4.5 V
I(IN)
1
0.9
V
= 2.7 V
I(IN)
0.8
– Short-circuit Output Current – A
0.7
OS
I
0.6
–40
TJ – Junction Temperature – °C
V
= 5 V
I(IN)
0
25 85 125
I(IN)
V
I(IN)
= 3.3 V
1.2
1.16
1.12
1.08
Threshold Trip Current – A
1.04
1
2.5 3 3.5 4 4.5 5 5.5 6
Figure 20
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
2.35
2.3
Start Threshold
250
sµ
200
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
TA = 25°C
Load Ramp = 1 A/10 ms
VI – Input Voltage – V
Figure 21
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
V
= 5 V
I(IN)
TA = 25°C
2.25
2.2
2.15
UVLO – Undervoltage Lockout – V
2.1
–40 0 25 85 125
TJ – Junction Temperature – °C
Figure 22
18
150
Stop Threshold
100
Current Limit Response –
50
0
0 2.5 5 7.5 10 12.5
Peak Current – A
Figure 23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TPS2041A
0.1 µF
2,3
IN
5
OC
4
EN
GND
1
OUT
6,7,8
0.1 µF 22 µF
Load
Power Supply
2.7 V to 5.5 V
Figure 24. T ypical Application (Example, TPS2041A)
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy .
This precaution reduces power-supply transients that may cause ringing on the input. Additionally , bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V
has been applied (see Figure 6). The TPS204xA and TPS205xA sense the
I(IN)
short and immediately switch into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, very high currents may flow for a short time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS204xA and TPS205xA are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. The TPS204xA and
TPS205xA family of devices are designed to reduce false overcurrent reporting. An internal overcurrent
transient filter eliminates the need for external components to remove unwanted pulses. Using low-ESR
electrolytic capacitors on the output lowers the inrush current flow through the device during hot-plug events
by providing a low-impedance energy source, also reducing erroneous overcurrent reporting.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TPS2041A
GND
IN
IN
EN
OUT
OUT
OUT
OC
Figure 25. Typical Circuit for OC Pin (Example, TPS2041A)
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. Begin by determining the r
of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use
the highest operating ambient temperature of interest and read r
power dissipation per switch can be calcultaed by:
PD+
r
DS(on)
2
I
V+
R
DS(on)
pullup
from Figure 18. Using this value, the
DS(on)
Depending on which device is being used, multiply this number by the number of switches being used. This step
will render the total power dissipation from the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ+
PD
R
)
JA
T
A
q
Where:
T
= Ambient Temperature °C
A
R
= Thermal resistance SOIC = 172°C/W (for 8 pin), 111°C/W (for 16 pin)
θJA
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS204xA and TPS205xA into constant-current mode, which
causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across
the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high
levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built
into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back
on. The switch continues to cycle in this manner until the load fault or input power is removed.
The TPS204xA and TPS205xA implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or
overcurrent occurs.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce
EMI and voltage overshoots.
universal serial bus (USB) applications
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D
Hosts/self-powered hubs (SPH)
D
Bus-powered hubs (BPH)
D
Low-power, bus-powered functions
D
High-power, bus-powered functions
D
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS204xA and
TPS205xA can provide power-distribution solutions for many of these classes of devices.
host/self-powered and bus-powered hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figures 26 and 27). This power supply must provide from 5.25 V to 4.75 V to the board
side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have
current-limit protection and must report overcurrent conditions to the USB controller. T ypical SPHs are desktop
PCs, monitors, printers, and stand-alone hubs.
USB
Control
Power Supply
3.3 V 5 V
0.1 µF
2, 3
5
4
TPS2041A
IN
OC
EN
GND
OUT
7
0.1 µF 120 µF
Downstream
USB Ports
D+
D–
V
BUS
GND
Figure 26. Typical One-Port Solution
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
Power Supply
USB
Controller
3.3 V 5 V
0.1 µF
11
13
12
2
6
3
4
7
9
8
TPS2044A
IN1
IN2
OC1
EN1
OC2
EN2
OC3
EN3
OC4
EN4
GNDA
OUT1
OUT2
OUT3
OUT4
GNDB
1
15
14
11
10
5
+
+
+
+
33 µF
33 µF
33 µF
33 µF
Downstream
USB Ports
D+
D–
V
BUS
GND
D+
D–
V
BUS
GND
D+
D–
V
BUS
GND
D+
D–
V
BUS
GND
Figure 27. T ypical Four-Port USB Host/Self-Powered Hub
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on powerup, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
low-power bus-powered functions and high-power bus-powered functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and
can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of
44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 28).
Power Supply
D+
D–
V
BUS
GND
USB
Control
10 µF
3.3 V
0.1 µF
2,3
5
4
TPS2041A
IN
OC
EN
GND
1
OUT
6, 7, 8
0.1 µF 10 µF
Internal
Function
Figure 28. High-Power Bus-Powered Function (Example, TPS2041A)
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
D
Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB V
D
Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)
D
Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS204xA and TPS205xA allows them to meet each of these requirements. The
integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level
enable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as
the input ports for bus-power functions (see Figures 29 through 32).
BUS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D +
D –
GND
5 V
SN75240
TPS2041A
OC EN
IN
1 µF
0.1 µF
4.7 µF
A
B
OUT
C
D
GND
5 V Power
Supply
TPS76333
IN
3.3 V
GND
48-MHz
Crystal
Tuning
Circuit
4.7 µF
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
GND
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
Tie to TPS2041A EN
TPS2041A
EN
OC
TPS2041A
EN
OC
TPS2041A
EN
OC
TPS2041A
EN
OC
IN
OUT
IN
OUT
IN
OUT
IN
OUT
ABC
D
SN75240
ABC
D
SN75240
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Input
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
Downstream
Ports
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
USB rev 1.1 requires 120 µF per hub.
Figure 29. Hybrid Self/Bus-Powered Hub Implementation, TPS2041A
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
33 µF
†
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D +
D –
GND
5 V
TPS2041A
OC EN
IN
1 µF
0.1 µF
4.7 µF
SN75240
A
C
B
D
OUT
GND
5 V Power
Supply
TPS76333
IN
3.3 V
GND
48-MHz
Crystal
Tuning
Circuit
4.7 µF
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
GND
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
Tie to TPS2042A EN
ABC
SN75240
ABC
SN75240
TPS2042A
EN1
OUT1
OUT2
OC1
EN2
OC2
IN
TPS2042A
EN1
OUT1
OUT2
OC1
EN2
OC2
IN
Input
D
D
0.1 µF
0.1 µF
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
Downstream
Ports
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
†
USB rev 1.1 requires 120 µF per hub.
Figure 30. Hybrid Self/Bus-Powered Hub Implementation, TPS2042A
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
33 µF
5 V
†
25
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D +
D –
GND
5 V
1/2 SN75240
TPS2041A
OC EN
IN
1 µF
0.1 µF
4.7 µF
A
B
OUT
C
D
GND
5 V Power
Supply
TPS76333
IN
3.3 V
GND
48-MHz
Crystal
Tuning
Circuit
4.7 µF
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
GND
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
Tie to TPS2043A EN
ABC
SN75240
ABC
1/2 SN75240
TPS2043A
EN1
OUT1
OUT2
OC1
EN2
OC2
IN1
EN3
OUT3
OC3
IN2
Input
D
D
0.1 µF
0.1 µF
Ferrite Beads
Ferrite Beads
Ferrite Beads
Downstream
Ports
D +
D –
GND
5 V
†
47 µF
D +
D –
GND
5 V
†
47 µF
D +
D –
GND
5 V
†
47 µF
†
USB rev 1.1 requires 120 µF per hub.
Figure 31. Hybrid Self/Bus-Powered Hub Implementation, TPS2043A
26
GNDA
GNDB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D +
D –
GND
5 V
SN75240
TPS2041A
OC EN
IN
1 µF
0.1 µF
4.7 µF
A
B
OUT
C
D
GND
5 V Power
Supply
TPS76333
IN
3.3 V
GND
48-MHz
Crystal
Tuning
Circuit
4.7 µF
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
GND
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
Tie to TPS2041 EN
ABC
SN75240
ABC
SN75240
TPS2044A
EN1
OUT1
OUT2
OC1
EN2
OC2
IN1
EN3
OUT3
OUT4
OC3
EN4
OC4
IN2
GNDA
GNDB
Input
D
D
0.1 µF
0.1 µF
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
Downstream
Ports
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
33 µF
D +
D –
GND
5 V
†
USB rev 1.1 requires 120 µF per hub.
Figure 32. Hybrid Self/Bus-Powered Hub Implementation, TPS2044A
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
33 µF
†
27
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
generic hot-plug applications (see Figure 33)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xA and TPS205xA, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS204xA and TPS205xA also ensures the switch will be off after the card has been removed, and the
switch will be off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for
every insertion of the card or module.
PC Board
Power
Supply
2.7 V to 5.5 V
1000 µF
Optimum
0.1 µF
TPS2041A
GND
IN
IN
EN
OUT
OUT
OUT
OC
Block of
Circuitry
Overcurrent Response
Figure 33. T ypical Hot-Plug Implementation (Example, TPS2041A)
By placing the TPS204xA and TPS205xA between the VCC input and the rest of the circuitry , the input power
will reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing
a slow voltage ramp at the output of the device. This implementation controls system surge currents and
provides a hot-plugging mechanism for any device.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
DIM
8
7
PINS **
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
8
14
0.008 (0,20) NOM
0°–8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
4040047/D 10/96
29
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
TPS2041AD NRND SOIC D 8 75 Green (RoHS &
TPS2041ADG4 NRND SOIC D 8 75 Green (RoHS &
TPS2041ADR NRND SOIC D 8 2500 Green(RoHS &
TPS2041ADRG4 NRND SOIC D 8 2500 Green(RoHS &
TPS2042AD NRND SOIC D 8 75 Green (RoHS &
TPS2042ADG4 NRND SOIC D 8 75 Green (RoHS &
TPS2042ADR NRND SOIC D 8 2500 Green(RoHS &
TPS2042ADRG4 NRND SOIC D 8 2500 Green(RoHS &
TPS2043AD NRND SOIC D 16 40 Green (RoHS &
TPS2043ADG4 NRND SOIC D 16 40 Green (RoHS &
TPS2043ADR NRND SOIC D 16 2500 Green (RoHS &
TPS2043ADRG4 NRND SOIC D 16 2500 Green (RoHS &
TPS2044AD NRND SOIC D 16 40 Green (RoHS &
TPS2044ADG4 NRND SOIC D 16 40 Green (RoHS &
TPS2044ADR NRND SOIC D 16 2500 Green (RoHS &
TPS2044ADRG4 NRND SOIC D 16 2500 Green (RoHS &
TPS2051AD NRND SOIC D 8 75 Green (RoHS &
TPS2051ADG4 NRND SOIC D 8 75 Green (RoHS &
TPS2051ADR NRND SOIC D 8 2500 Green(RoHS &
TPS2051ADRG4 NRND SOIC D 8 2500 Green(RoHS &
TPS2052AD NRND SOIC D 8 75 Green (RoHS &
TPS2052ADG4 NRND SOIC D 8 75 Green (RoHS &
TPS2052ADR NRND SOIC D 8 2500 Green(RoHS &
TPS2052ADRG4 NRND SOIC D 8 2500 Green(RoHS &
TPS2053AD NRND SOIC D 16 40 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
4-Aug-2008
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TPS2053ADG4 NRND SOIC D 16 40 Green (RoHS &
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
4-Aug-2008
(3)
no Sb/Br)
TPS2053ADR NRND SOIC D 16 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2053ADRG4 NRND SOIC D 16 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2054AD NRND SOIC D 16 40 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2054ADG4 NRND SOIC D 16 40 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2054ADR NRND SOIC D 16 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2054ADRG4 NRND SOIC D 16 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
19-Mar-2008
*All dimensions are nominal
Device Package
Type
TPS2041ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2042ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2043ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2044ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2051ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2052ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2053ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2054ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2041ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2042ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2043ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2044ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2051ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2052ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2053ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2054ADR SOIC D 16 2500 333.2 345.9 28.6
Pack Materials-Page 2
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