Texas Instruments TNETE2201BPJD, TNETE2201BPHD Datasheet

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TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

1.25 Gigabits Per Second (Gbps) Gigabit Ethernet Transceiver

Based on the P802.3Z Specification

Transmits Serial Data up to 1.25 Gbps

Operates With 3.3-V Supply Voltage

5-V Tolerant on TTL Inputs

description

The TNETE2201B gigabit Ethernet transceiver provides for ultra high-speed bidirectional point-to-point data transmission. This device is based on the timing requirements of the proposed 10-bit interface specification by the P802.3z Gigabit Task Force.

PHD OR PJD PACKAGE

(TOP VIEW)

Interfaces to Electrical Cables/Backplane or Optical Modules

PECL Voltage Differential Signaling Load, 1 V Typ With 50 Ω – 75 Ω

Receiver Differential Input Voltage 200 mV Minimum

Low Power Consumption

64-Pin Quad Flat Pack With Thermally Enhanced Package

GND_CMOS

TD0 TD1 TD2

_CMOS

TD3 TD4 TD5 TD6

_CMOS

TD7 TD8 TD9

GND_CMOS

GND_TX

TC1

GND_A

DOUT_TXP

63 62 61 60 5964 58

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1718 19

TC0

_TX

LOOPEN

DOUT_TXN

21 22 23 24

GND_CMOS

GND_A

_CMOS

REFCLK

56 55 5457

25 26 27 28 29

SYNCEN

DIN_RXP

GND_A

53 52

LCKREFN

RESERVED

GND_CMOS

DIN_RXN

51 50 49

30 31 32

_RX

GND_RX

RC1

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

RBC1

RBC0

GND_A

RC0 SYNC GND_TTL RD0 RD1 RD2 V

_TTL

RD3 RD4 RD5 RD6 V

_TTL

RD7 RD8 RD9 GND_TTL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

description (continued)

The intended application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled-impedance media of approximately 50 Ω to 75 Ω. The transmission media can be printed-circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TNETE2201B performs the data serialization and deserialization (SERDES) functions for the gigabit ethernet physical layer interface. The transceiver operates at 1.25 Gbps (typical), providing up to 1000 Mbps of bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero (NRZ) at pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output with respect to two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel bytes in RBC clock rising edges.

The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.

The TNETE2201B provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.

The TNETE2201B is characterized for operation from 0°C to 70°C.

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functional block diagram

LOOPEN

TD0 – TD9

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

TX+ TX–

10-Bit

Shift

REFCLK

SYNCEN

SYNC

RD0 – RD9

RBC0

RBC1

62.5 MHz

125 MHz

÷ 2

10-Bit

125 MHz

Clock

Multiplier

Synchronous

Detect

Shift

PLL Clock

Recovery and

Data Retiming

2:1

MUX

RX+ RX–

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TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

I/O structures

PECL inputs (DIN_RXP, DIN_RXN) PECL outputs (DIN_TXP, DIN_TXN)

DIN_RXP

100 Ω

4 kΩ

+ _

DIN_RXN

4 kΩ

CMOS inputs (TD0 – TD9, LOOPEN, REFCLK, SYNCEN, LCKREFN)

TERMINALS REFCLK, TD0 – TD9 LOOPEN SYNCEN, LCKREFN

Input

120 Ω

CMOS outputs (RD0 – RD9, RBC0, RBC1, SYNC)

Open Circuit Open Circuit

R1 R2

Open Circuit

400 kΩ

Open Circuit

DOUT_TXP

DOUT_TXN

400 kΩ

Output

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TNETE2201B

DESCRIPTION

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

Terminal Functions

TERMINAL

NAME NO. TYPE

I/O and DATA

DOUT_TXP DOUT_TXN

DIN_RXP DIN_RXN

LCKREFN 27 Input Lock to reference. When LCKREFN is asserted low, the receive PLL phase locks to the supplied

LOOPEN 19 Input Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The

RBC0 RBC1

RC1, RC0

RD0 – RD9 45,44,43,41

REFCLK 22 Input Reference clock. REFCLK is an external 125 MHz input clock that synchronizes the receiver and

SYNC 47 Output Synchronous detect. SYNC is asserted high upon detection of the K28.5 character in the serial data

SYNCEN 24 Input Synchronous function enable. When SYNCEN is asserted high, the internal synchronization function

TC1 TC0

TD0 – TD9 2,3,4,6

NOTE 1: A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due

to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the voltage supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to reject power supply noise.

62 61

54 52

31 30

49 48

40,39,38,36

35,34

16 17

7,8,9,1 1

12,13

Output Differential output transmit. DOUT_TXP and DOUT_TXN are differential serial outputs that interface

to a copper or an optical I/F module. These terminals transmit NRZ data at a rate of 1.25 Gbps. DOUT_TXP and DOUT_TXN are held static when LOOPEN is high and are active when LOOPEN is low.

Input Differential input receive. DIN_RXP and DIN_RXN together are the differential serial input interface

from a copper or an optical I/F module. These terminals receive NRZ data at a rate of 1.25 Gbps and are active when LOOPEN is held low.

REFCLK signal. LCKREFN prelocks or resets the receive PLL.

transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held static during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active.

Output Receive byte clock. RBC0 and RBC1 are 62.5-MHz recovered clocks used for synchronizing the

10-bit output data on RD0 – RD9. The 10-bit output data words are valid on the rising edges of RBC0 and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.

Analog Receive capacitor. RC0 and RC1 are external capacitor connections used for the receiver internal

PLL filter. The recommend value for this external capacitor is 2 nF (a value of 0.1 µF can also be used, see Note 1).

Output Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol

layer. The data is referenced to terminals RBC0 and RBC1. Received data byte 0, which contains the K28.5 character, is byte aligned to the rising edge of RBC1. RD0 is the first bit received.

transmitter interfaces. The transmitter uses this clock to register the 10-bit input data (TD0..TD9) for serialization. REFCLK is also used as a RX PLL preset or reference when LCKREFN is enabled.

path. SYNC is a high level for 1/2 REFCLK period. SYNC pulses are output only when SYNCEN is activated (asserted high). Note: SYNC is active on byte0 and, therefore, active on rising edge of RCB1.

is activated. When this function is enabled, the transceiver detects the K28.5 character (0011 1 1 1010 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0 – RD9.

Analog T ransmit capacitor. TC0 and TC1 are external capacitor connections used for the transmitter internal

PLL filter. The recommended value of this external capacitor is 2 nF (a value of 0.1 µF can also be used, see Note 1).

Input Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the transceiver

for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.

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TNETE2201B

DESCRIPTION

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME NO. TYPE

POWER

VCC_A 20,28,29,53

55,57,59,60

VCC_CMOS 5,10,23, Supply Digital PECL logic power. VCC_CMOS provides an isolated low-noise power supply for the logic

VCC_RX 50 Supply Receiver power . VCC_RX provides a low-noise supply reference voltage for the receiver high-speed

VCC_TTL 42,37 Supply TTL power. VCC_TTL provides a supply reference voltage for the receiver TTL circuits. VCC_TX 18 Supply Transmitter power. VCC_TX provides a low-noise supply reference voltage for the transmitter

GND_A 21,32,56,64 Ground Analog ground. GND_A provides a ground reference for the high-speed analog circuits. GND_CMOS 1,14,

25,58 GND_RX 51 Ground Receiver ground. GND_RX provides a ground reference for the receiver circuits. GND_TTL 33,46 Ground TTL circuit ground. GND_TTL provides a ground for TTL interface circuits. GND_TX 15 Ground Transmitter ground. GND_TX provides a ground reference for the transmitter circuits.

RESERVED 26 Reserved. Internally pulled to GND, leave open or assert low.

Supply Analog power. VCC_A provides a supply reference voltage for the high-speed analog circuits.

circuits.

analog circuits.

high-speed analog circuits.

GROUND

Ground Digital PECL logic ground. GND_CMOS provides an isolated low-noise ground for the logic circuits.

MISCELLANEOUS

detailed description

data transmission

The transmitter registers incoming 10-bit-wide data words (8b/10b encoded data, TD0...TD9) on the rising edge of REFCLK (125 MHz). The reference clock is also used by the serializer, which multiplies the clock by a factor of 10 providing a 1.25 Gbaud signal that is fed to the shift register. The data is then transmitted dif ferentially at PECL voltage levels. The 8b/10b encoded data is transmitted sequentially bit 0 through 9.

transmission latency

The data transmission latency of the TNETE2201B is defined as the delay from the initial 10-bit word load to the serial transmission of bit 9. The typical transmission latency is 9 ns.

data reception

The receiver of the TNETE2201B deserializes 1.25 Gbps differential serial data. The 8b/10b data (or equivalent) is retimed based on an extracted clock from the serial data. The serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with two receive byte clocks (RBC0, RBC1). RBC0 and RBC1 are 180 degrees out of phase and are generated by dividing down the recovered 1.25 Gbps (625 MHz) clock by 10 providing for two 62.5-MHz signals. The receiver presents the protocol device byte 0 of the received data valid on the rising edge of RBC1.

NOTE:

This allows the option of byte alignment without the use of the synchronous detection

(SYNC) function by the protocol device.

The receiver PLL can lock to the incoming 1.25 GHz data without the need for a lock-to-reference preset. The received serial data rate (RX+ and RX–) should be 1.25 Gbps ±0.01% (100 ppm) for proper operation.

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TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

data reception (continued)

During a bus error condition or word alignment, the receive byte clocks RBC0 and RBC1 are stretched (never truncated). When the incoming serial data does not meet its frequency requirements, then the receive byte clock frequency is maintained at 62.5 MHz.

receive PLL operation

The receive PLL provides automatic locking to the incoming data. At power up, the maximum initial lock time is 500 µs. The PLL can also be initiated or set to phase lock to the externally supplied reference clock by enabling lock-to-reference (LCKREFN). The lock-to-reference causes the receive PLL to lock to 10× the reference clock (REFCLK) input providing a PLL preset and reset capability.

If during normal operation a transient occurs, which is defined as any arbitrary phase shift in the incoming data and/or a frequency wander of up to 200 ppm, then the PLL recovers lock within 2.4 µs. Any condition exceeding these values is considered a power-up scenario and the PLL recovers lock within 500 µs with a 0.1 µF capacitor the PLL recovers lock within 10 ms on power up (see the following note).

NOTE:

A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due to the larger filter capacitor. This reduces the transmit and receive PLL’ s ability to reject low-frequency noise or wonder in the voltage supply or datastream. Care must be taken in the filtering of the supply V to reject power supply noise.

_TX (terminal 18) and VCC_RX (terminal 50)

receiver word alignment

The TNETE2201B uses a 10-bit K28.5 character (comma character) word alignment scheme. The following sections explain how this scheme works and how it realigns itself.

comma character on expected boundary

The TNETE2201B provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is enabled by forcing SYCNEN high. This enables the function that examines and compares ten bits of serial input data to the K28.5 synchronization character. The K28.5 character is defined in the fibre channel standard as a pattern consisting of 0011111010 (a negative number beginning disparity) with the 7 MSBs (0011111) referred to as the comma character. The K28.5 character was implemented specifically for aligning data words. As long as the K28.5 character falls within the expected 10-bit word boundary, the received 10-bit data is properly aligned and data realignment is not required. Figure 1 shows the timing characteristics of RBC0, RBC1, SYNC and RD0 – RD9 while synchronized.

NOTE:

The

K28.5 character is valid on the rising edge of RBC1.

RBC0

RBC1

SYNC

RD0 – RD9

K28.5 Dxx.x Dxx.x Dxx.x K28.5 Dxx.x

Figure 1. Synchronous Timing Characteristics Waveforms

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TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

comma character not on expected boundary

When synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure 2. The 10b specification requires that RCLK cycles can not be truncated and can only be stretched or stalled in their current state during realignment. With this design the maximum stretch that occurs is an extra 10 bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1 instead of the rising edge. This system transmits a minimum of three consecutively ordered K28.5 data sets between frames and ensures that the receiver sees at least two of K28.5 sets (the fabric is allowed to drop one). Figure 2 shows the timing characteristics of the data realignment.

Systems that do not require framed data can disable byte alignment by tying SYNCEN low. When a synchronization character is detected the SYNC signal is asserted high and is aligned with the K28.5

character. The duration of the SYNC-signal pulse is equal to the duration of the data which is half an RCLK period.

Typical Receive Path Latency = 18 ns

Serial Rx Data Stream

DIN_RxP – DIN_RxN

10 Bit Times 10 Bit Times

RBC1

RBC0

RD0 – RD9

SYNC

K28.5 Dxx.x Dxx.x Dxx.xK28.5 Dxx.x

20 Bit Times (MAX)

Corrupted Data

Worst Case

Misaligned K28.5

Dxx.x Dxx.x

K28.5

Dxx.x Dxx.x Dxx.x

Dxx.x K28.5

Misalignment Corrected

K28.5

Dxx.x

Figure 2. Word Realignment Timing Characteristics Waveforms

Dxx.x K28.5

K28.5Dxx.x

data reception latency

The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RD0 received as first bit. The receive latency is typically 18 ns.

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TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

loop-back testing

The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loop-back path. Enabling LOOPEN causes serially transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. The external differential output is held in a static state during loop-back testing.

absolute maximum ratings

†

Supply voltage, VCC (see Note 2) –0.5 to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, VI (TTL, PECL) –0.5 to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current I

, (TTL) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current IO, (PECL) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any terminal –0.5 to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge, 5-V tolerant input terminals (see Note 3) Class 1, A:1 kV, B:150 V. . . . . . . . . . . . . .

Electrostatic discharge, all other terminals (see Note 3) Class 1, A:2 kV, B:200 V. . . . . . . . . . . . . . . . . . . . . .

Characterized free-air operating temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 2. All voltage values, except differential I/O bus voltages, are with respect to network ground.

3. This parameter is tested in accordance with MIL-PRF-38535.

recommended operating conditions

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Supply voltage, V Supply current, ICC (static) Static pattern Power dissipation, PD (static) Outputs open, Static pattern Supply current, ICC (dynamic) K28.5 240 330 mA Power dissipation, PD (dynamic) Outputs open, K28.5 790 1150 mW Operating free-air temperature, T

†

Power (static pattern) = 125 MHz to the receiver and 5 ones and 5 zeros to the transmitter.

†

3.14 3.3 3.47 V 180 260 mA

†

590 900 mW

0 70 °C

reference clock (REFCLK) timing requirements over recommended operating conditions (unless otherwise noted)

Frequency Accuracy –100 100 ppm

Duty cycle 40% 50% 60% Jitter Random and deterministic 40 ps

†

This clock should be crystal referenced to meet the requirements of the this table. The maximum rate of frequency change specified is valid after 10 seconds from power on.

†

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

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TYP –

0.01%

125

TYP +

0.01%

MHz

TNETE2201B

IIHHigh-level input current

IILLow-level input current

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

electrical characteristics over recommended operating conditions (unless otherwise noted)

TTL Signals: TD0 .. TD9, REFCLK, LOOPEN, SYNCEN, SYNC, RD0 .. RD9, RBC0, RBC1, LCKREFN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage VCC = MIN, IOH = –400 µA 2.4 3 V

Low-level output voltage VCC = MIN, IOL = 1 mA 0.25 0.4 V

High-level input voltage 2 5.5 V

Low-level input voltage 0.8 V

Input capacitance 4 pF

REFCLK VCC = MAX, VI = 2.4 V 900 µA

REFCLK VCC = MAX, VI = 0.4 V –900 µA

VCC = MAX, VI = 2.4 V 40 µA

VCC = MAX, VI = 0.4 V –40 µA

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TNETE2201B

VOD

Driver differential output voltage (peak-to-peak)

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

TRANSMITTER SECTION

differential electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Driver common-mode output voltage RL = 75 Ω 2100 mV

differential switching characteristics over recommended operating conditions (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Serial data deterministic jitter (peak-to-peak) Differential output jitter 96 ps

Serial data total jitter (peak-to-peak) Differential output jitter 192 ps t t

Differential signal rise time (20% to 80%)

Differential signal fall time (20% to 80%)

RL = 75 Ω, See Figure 3 1100 2200 RL = 50 Ω, See Figure 3 1100 2200

RL = 75 Ω, See Figure 3

CL = 5 pF,

300 300

ps ps

TX+

TX–

80% ≈VCC – 0.7 V 50% 20%

80% ≈1 V 50% 20%

≈VCC – 1.6 V

≈–1 V

Figure 3. Differential and Common-Mode Output Voltage Definitions

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transmitter timing requirements over recommended operating conditions (unless otherwise noted)

TEST CONDITIONS MIN NOM MAX UNIT

su1

transmit interface timing

Setup time, TD0 – TD9 valid to REFCLK ↑ See Figure 4 2 ns Hold time, REFCLK ↑ to TD0 – TD9 invalid See Figure 4 1 ns Parallel-to-serial data latency 9 ns

The transmit interface is defined in the 10 b spec as the 10-bit parallel data input to the physical layer for serial transmission. The timing values are specified from REFCLK midpoint to valid input signal levels or from valid input signal levels to REFCLK midpoint.

REFCLK

TD0 – TD9

50%

su1

Valid Valid Valid

Figure 4. Transmit 10-Bit Interface Timing Waveforms

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TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

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RECEIVER SECTION

differential electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

|VID| Differential input voltage (peak-to-peak) See Figure 5 400 2600 mV

receiver and phase-locked loop performance characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX

Jitter tolerance See P802.3Z specification 74.9% UI

From power up at 2 nF capacitor value 500 µs

Data acquisition lock time

Data relock time From synchronization loss 2500 ns

†

UI is the unit interval of a single bit (800 ps).

NOTE 4: A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due

From power up at 0.1 µF capacitor value (See Note 4)

10 ms

UNIT

†

receive clock timing requirements over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

clk

(skew)

su2

su3

su4

su5

†

(drift)

applicable under all input signal conditions with PLL locked to the REFCLK of DATA signals.

Clock frequency, RBC0 62.5 MHz Clock frequency, RBC1 (180 deg out of phase with RBC0) 62.5 MHz Data rise time See Figure 6 0.7 4 ns Data fall time See Figure 6 0.7 4 ns Rise time, single-ended output signal on RBC0 or RBC1 See Figure 6 0.7 2 ns Fall time, single-ended output signal on RBC0 or RBC1 See Figure 6 0.7 2 ns Duty cycle, RBC0 or RBC1 40% 60% Skew time, RBC1 ↑ to RBC0 ↑ See Figure 7 7.5 8 8.5 ns Setup time, RD0 – RD9, SYNC valid to RBC0 ↑ See Figure 7 2.5 ns Setup time, RD0 – RD9, SYNC valid to RBC1 ↑ See Figure 7 2.5 ns Setup time, RBC1 ↑ to RD0 – RD9, SYNC invalid See Figure 7 1.5 ns Setup time, RBC1 ↑ to RD0 – RD9, SYNC invalid See Figure 7 1.5 ns Serial-to-parallel data latency 18 ns

is the minimum time for RBC0 or RBC1 to drift from 63.5 MHz to 64.5 MHz or from 60 MHz to 59 MHz from the RCLK lock value. This is

|VID|

0 V

|VID|

Figure 5. Differential Input Voltage (Peak-to-Peak) Timing Waveform

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TNETE2201B

ÉÉ

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

80%

Data

Clock

RBC0

RBC1

50% 20%

80% 50% 20%

Figure 6. Receiver Data Measurement Levels

(skew)

50%

50% 50%

50%

RD0 – RD9, SYNC

su3

su4

Valid

Figure 7. Receiver Interface Timing Waveforms

su2

su5

Valid

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1.25-GIGABIT ETHERNET TRANSCEIVER

APPLICATION INFORMATION

TNETE2201B

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

3.3 V

Protocol

Device

Host

Ferrite Bead

0.01 µF

Ferrite Bead

50 18

VCC_TXVCC_RX

GND_RX GND_TX

TNETE2201B

DOUT_TXP

TD0 – TD9

REFCLK

LCKREFN

LOOPEN

SYNCEN

31,30

SYNC RD0 – RD9 RBC0,RBC1

DOUT_TXN

DOUT_RXP

5 Ω at 100 MHz

0.01 µF

(pd)

(see Note A)

50 Ω – 75 Ω

(see Note B)

3.3 V

Controlled Impedance Transmission Line

TC1

TC0

PLL Filter Capacitor = 2 nF or 0.1 µF (see Note C)

DOUT_RXN

RC1

Capacitor = 2 nF or 0.1 µF

NOTES: A. R(pd) – This value is set to match the falling edge to rising edge transistion times, typically 150 Ω. to 220 Ω..

B. Vt (termination voltage): Vt = VCC – 1.3 V, if ac coupled

C. A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced

PLL Filter

(see Note C)

due to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the voltage supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to reject power supply noise.

RC0

Vt = VCC – 2 V, if directly coupled.

Controlled Impedance Transmission Line

Figure 8. Typical Application Circuit

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

MECHANICAL INFORMATION

The TNETE2201B incorporates the latest development in TI’s package line. The new patent-pending design, designated the PWP, delivers thermal performance comparing to a heat-spreader design in a true low-profile package. The PWP for the TNETE2201B is designed to maximize heat transfer away from the die through the top of the chip. As seen in Figures 9 and 10 the bottom of the leadframe is deep downset towards the top of the chip, providing a thermal path away from the die and board. All this has been accomplished without exceeding the 1.15 mm height of the TQFP . This package in the 10mm × 10mm TQFP (PJD) provides a thermal resistance R

of 40°C/W and the package in the 14mm × 14mm TQFP (PHD) provides a R

θJA

of 40°C/W.

Figure 9. Heat-Spreader Design

Figure 10. Leadframe Downset

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

MECHANICAL INFORMATION

PHD (S-PQFP-G64) PowerPAD PLASTIC QUAD FLATP ACK (DIE DOWN)

1,05 0,95

0,80

12,00 TYP

14,05

13,95 16,15

15,85

0,40 0,30

3348

0,20

Thermal Pad (see Note D)

0,15 0,05

0,13 NOM

Gage Plane

0,25

0°–7°

0,75 0,45

1,20 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions include mold flash or protrusions. D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MS-026

PowerPAD is a trademark of Texas Instruments Incorporated.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Seating Plane

0,10

4087742/A 12/97

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

MECHANICAL INFORMATION

PJD (S-PQFP-G64) PowerPAD PLASTIC QUAD FLATP ACK (DIE DOWN)

1,05

0,95

0,50

0,27 0,17

7,50 TYP

10,20

9,80

12,20

11,80

0,08

Seating Plane

Thermal Pad (See Note D)

0,15 0,05

0,13 NOM

Gage Plane

0,25

0°–7°

0,75 0,45

1,20 MAX

NOTES: A. All linear dimensions are in millimeters.

PowerPAD is a trademark of Texas Instruments Incorporated.

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0,08

4147703/A 12/97

IMPORTANT NOTICE

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Texas Instruments TNETE2201BPJD, TNETE2201BPHD Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual