Texas Instruments TMX320VC5420PGE200, TMX320VC5420GGU200, TMS320VC5420PGE200, TMS320VC5420GGU200 Datasheet
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
200-MIPS Dual-Core DSP Consisting of Two
Independent Subsystems
Each Core Has an Advanced Multibus
Architecture With Three Separate 16-Bit
Data Memory Buses and One Program Bus
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel-Shifter and Two
40-Bit Accumulators Per Core
Each Core Has a 17- × 17-Bit Parallel
Multiplier Coupled to a 40-Bit Adder for
Non-Pipelined Single-Cycle Multiply/
Accumulate (MAC) Operations
Each Core Has a Compare, Select, and
Store Unit (CSSU) for the Add/Compare
Selection of the Viterbi Operator
Each Core Has an Exponent Encoder to
Compute an Exponent Value of a 40-Bit
Accumulator Value in a Single Cycle
Each Core Has Two Address Generators
With Eight Auxiliary Registers and Two
Auxiliary Register Arithmetic Units
(ARAUs)
16-Bit Data Bus With Data Bus Holder
Feature
256K × 16 Extended Program Address
Space
Total of 200K × 16 Dual- and Single-Access
On-Chip RAM
Single-Instruction Repeat and
Block-Repeat Operations
Instructions With 32-Bit Long Word
Operands
Instructions With 2 or 3 Operand Reads
Fast Return From Interrupts
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Output Control of CLKOUT
Output Control of TOUT
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions
Dual 1.8-V (Core) and 3.3-V (I/O) Power
Supplies for Low Power, Fast Operation
10-ns Single-Cycle Fixed-Point Instruction
Execution
Interprocessor Communication via Two
Internal 8-Element FIFOs
12 Channels of Direct Memory Access
(DMA) for Data Transfers With No CPU
Loading (6 Channels Per Subsystem)
Six Multichannel Buffered Serial Ports
(McBSPs) (Three McBSPs Per Subsystem)
16-Bit Host-Port Interface (HPI16)
Multiplexed With External Memory Interface
Pins
Software-Programmable Phase-Locked
Loop (PLL) Provides Several Clocking
Options (Requires External TTL Oscillator)
On-Chip Scan-Based Emulation Logic
T wo Software-Programmable Timers
(One Per Subsystem)
Software-Programmable Wait-State
Generator (14 Wait States Maximum)
Provided in 144-pin BGA Ball Grid Array
(GGU Suffix) and 144-pin Thin Quad
Flatpack (TQFP) (PGE Suffix) packages
NOTE:This data sheet is designed to be used in conjunction with the
TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table of Contents
Pin Assignments 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multicore Reset Signals 18. . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Peripherals 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-bit Host-Port Interface (HPI16) 23. . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) 25. . . . . . . . . . .
Direct Memory Access Unit (DMA) 26. . . . . . . . . . . . . . . . . .
Subsystem Communications 28. . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory-Mapped Registers 32. . . . . . . . . . . . . . . . . . . . . . . .
Interrupts 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDLE3 Power-Down Mode 38. . . . . . . . . . . . . . . . . . . . . . . . .
Emulating the ’5420 Device 38. . . . . . . . . . . . . . . . . . . . . . . .
Documentation Support 39. . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 40. . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 40. . . . . . . . . . . . . . .
Electrical Characteristics 41. . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-By-N ClockOption 42. . . . . . . . . . . . . . . . .
Bypass Option 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory Interface Timing 44. . . . . . . . . . . . . . . . . .
Ready Timing 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Interface Timing 50. . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and XIO Timing 54. . . . . . . . . . . . . . .
External Flag (XF), and Timer Output (TOUT) Timing 56. .
General Purpose Input Output (GPIO) Timing 57. . . . . . . .
SELA/B Timing 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port Timing 59. . . . . . . . . . . . .
multichannel buffered serial port timing (continued) 60. . . .
HPI16 Timing 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
description
The TMS320VC5420 fixed-point digital signal processor (DSP) is a dual CPU device capable of up to 200-MIPS
performance. The ’5420 consists of two independent ’54x subsystems capable of core-to-core
communications.
Each subsystem CPU is based on an advanced, modified Harvard architecture that has one program memory
bus and three data memory buses. The processor also provides an arithmetic logic unit (ALU) that has a high
degree of parallelism, application-specific hardware logic, on-chip memory , and additional on-chip peripherals.
Each subsystem has separate program and data spaces, allowing simultaneous accesses to program
instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions
with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can
be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit manipulation operations that can be performed in a single machine cycle. In addition, the ’5420 includes
the control mechanisms to manage interrupts, repeated operations, and function calls.
The ’5420 is offered in two temperature ranges and individual part numbers as shown below . (Please note that
the industrial temperature device part numbers do not follow the typical numbering tradition.)
Commercial temperature devices (0°C to 85°C)
TMS320VC5420PGE200 (144-pin LQFP)
TMS320VC5420GGU200 (144-pin BGA)
Industrial temperature range devices (–40°C to 100°C)
TMS320C5420PGEA200 (144-pin LQFP)
TMS320C5420GGUA200 (144-pin BGA)
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
AV
PPA14
PPA15
V
SS
PPA16
PPA17
B_INT0
B_INT1
B_NMI
IS
B_GPIO2/BIO
B_GPIO1
B_GPIO0
B_BFSR1
B_BDR1
CV
DD
V
SS
B_BCLKR1
B_BFSX1
V
SS
B_BDX1
B_BCLKX1
CV
DD
V
SS
TEST
XIO
B_RS
B_XF
B_CLKOUT
HMODE
HPIRS
PPA13
PPA12
V
SS
DV
DD
PPA11
PPA10
PPD7
PPA8
PPA0
DV
DD
PPA9
PPD1
A_INT1
A_NMI
IOSTRB
A_GPIO2/BIO
A_GPIO1
A_RS
A_GPIO0
V
SS
V
SS
CV
DD
A_BFSR1
A_BDR1
A_BCLKR1
A_BFSX1
CV
DD
V
SS
A_BDX1
A_BCLKX1
A_XF
A_CLKOUT
VCO
TCK
TMS
TDI
TRST
EMU1/OFF
DV
DD
A_INT0
EMU0
TDO
144
PPD0
PPD5
143
142
141
PPD6
140
A_BFSX2
139
A_BDX2
138
A_BFSR2
137
A_BDR2
136
A_BCLKR2
135
134
133
A_BCLKX2
132
READY
131DV130
129
128
127
126
125
B_BCLKX2
124
B_BDX2
123
B_BFSX2
122
B_BCLKR2
121
120
119
B_BDR2
118
117
PPD2
116
PPD3
115
PPA1
114
PPA5
113
112
373839404142434445464748495051525354555657585960616263646566676869
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PPD15
PPD14SSPPD13
PPD12
A_BFSR0
A_BDR0
A_BCLKR0
A_BFSX0
A_BDX0
A_BCLKX0
DD
SS
B_BFSX0
B_BCLKR0
B_BDR0
B_BFSR0
R/W
PPA2
PPA3
SELA/B
PPD8
PPD9
PPD10
B_BDX0
MSTRB
111
110
PPA7
109
707172
PPD11
B_BFSR2
PPA6
DV
CLKIN
V
DV
V
DD
DD
DD
TMS320VC5420 PGE PACKAGE
†‡§
(TOP VIEW)
PPD4
B_BCLKX0
SS
V
V
SS
SS
V
SS
V
SS
V
DD
CV
DS
PS
DD
CV
SS
V
PPA4
SS
V
CV
DD
SSA
V
NC
CV
DD
SS
V
†
NC = No internal connection
‡
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O
pins and the core CPU.
§
Pin configuration shown for nonmultiplexed mode only. See the Pin Assignments for the TMS320VC5420PGE table for multiplexed
functions of specific pins.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320VC5420 GGU PACKAGE
(BOTTOM VIEW)
A
B
D
C
E
F
H
J
L
M
K
N
G
12
3456781012 1113 9
The pin assignments table for the TMS320VC5420GGU lists each pin name and its associated pin number for
this 144-pin ball grid array (BGA) package.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
pin assignments
The ’5420 pin assignments tables list each pin name and corresponding pin number for the two package types.
Some of the ’5420 pins can be configured for one of two functions. For these pins, the primary pin name is listed
in the primary column. The secondary pin name is listed in the secondary column and is shaded grey.
Pin Assignments for the TMS320VC5420PGE
(144-Pin Thin Quad Flatpack)
PRIMARY
SIGNAL NAME
SECONDARY
SIGNAL NAME
PIN
NO.
PRIMARY
SIGNAL NAME
SECONDARY
SIGNAL NAME
PIN
NO.
PPD7 HD7 1 PPA8
2
PPA0 A_HINT 3 DV
DD
4
PPA9 5 PPD1 HD1 6
A_INT1 7 A_NMI 8
A_GPIO3
IOSTRB
A_TOUT
9 A_GPIO2/BIO 10
A_GPIO1 11 A_RS 12
A_GPIO0 13 V
SS
14
V
SS
15 CV
DD
16
A_BFSR1 17 A_BDR1 18
A_BCLKR1 19 A_BFSX1 20
CV
DD
21 V
SS
22
A_BDX1 23 A_BCLKX1 24
A_XF 25 A_CLKOUT 26
VCO 27 TCK 28
TMS 29 TDI 30
TRST 31 EMU1 32
DV
DD
33 A_INT0 34
EMU0 35 TDO 36
V
SS
37 PPD15 HD15 38
PPD14 HD14 39 V
SS
40
PPD13 HD13 41 PPD12 HD12 42
A_BFSR0 43 A_BDR0 44
A_BCLKR0 45 A_BFSX0 46
V
SS
47 CV
DD
48
A_BDX0 49 A_BCLKX0 50
MSTRB HCS 51 DS HDS2 52
PS HDS1 53 B_BCLKX0 54
B_BDX0 55 DV
DD
56
V
SS
57 B_BFSX0 58
B_BCLKR0 59 B_BDR0 60
CV
DD
61 V
SS
62
B_BFSR0 63 R/W HR/W 64
PPA2 HCNTL1 65 PPA3 HCNTL0 66
SELA/B 67 PPD8 HD8 68
PPD9 HD9 69 PPD10 HD10 70
PPD11 HD11 71 V
SS
72
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Assignments for the TMS320VC5420PGE
(144-Pin Thin Quad Flatpack) (Continued)
PRIMARY
SIGNAL NAME
PIN
NO.
SECONDARY
SIGNAL NAME
PRIMARY
SIGNAL NAME
PIN
NO.
SECONDARY
SIGNAL NAME
PPA10 73 PPA11 74
DV
DD
75 V
SS
76
PPA12 77 PPA13 78
HPIRS 79 HMODE 80
B_CLKOUT 81 B_XF 82
B_RS 83 XIO 84
TEST 85 V
SS
86
CV
DD
87 B_BCLKX1 88
B_BDX1 89 V
SS
90
B_BFSX1 91 B_BCLKR1 92
V
SS
93 CV
DD
94
B_BDR1 95 B_BFSR1 96
B_GPIO0 97 B_GPIO1 98
B_GPIO2/BIO 99
IS
B_GPIO3
100
B_NMI 101 B_INT1 102
B_INT0 103 PPA17 104
PPA16 105 V
SS
106
PPA15 107 PPA14 108
PPA7 109 PPA6 110
PPA4 HAS 111 DV
DD
112
PPA5 113 PPA1 B_HINT 114
PPD3 HD3 115 PPD2 HD2 116
B_BFSR2 117 B_BDR2 118
V
SS
119 CV
DD
120
B_BCLKR2 121 B_BFSX2 122
B_BDX2 123 B_BCLKX2 124
V
SS
125 AV
DD
126
V
SSA
127 NC 128
CLKIN 129 DV
DD
130
READY HRDY 131 A_BCLKX2 132
CV
DD
133 V
SS
134
A_BCLKR2 135 A_BDR2 136
A_BFSR2 137 A_BDX2 138
A_BFSX2 139 PPD6 HD6 140
PPD4 HD4 141 PPD5 HD5 142
PPD0 HD0 143 V
SS
144
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Assignments for the TMS320VC5420GGU
(144-Pin MicroStar Ball Grid Array)
PRIMARY SECONDARY BALL PRIMARY SECONDARY BALL
PRIMARY
SIGNAL NAME
SECONDARY
SIGNAL NAME
BALL
NO.
PRIMARY
SIGNAL NAME
SECONDARY
SIGNAL NAME
BALL
NO.
PPD7 HD7 A1 PPA8 B1
DV
DD
C1 A_NMI D1
A_RS E1 CV
DD
F1
A_BDR1 G1 CV
DD
H1
A_XF J1 TMS K1
EMU1/OFF L1 EMU0 M1
V
SS
N1 PPD0 HD0 A2
V
SS
B2 PPA0 A_HINT C2
A_INT1 D2 A_GPIO1 E2
V
SS
F2 A_BFSR1 G2
V
SS
H2 A_CLKOUT J2
TDI K2 DV
DD
L2
TDO M2 PPD15 HD15 N2
PDD6 HD6 A3 PPD4 HD4 B3
PPD5 HD5 C3 PPD1 HD1 D3
A_GPIO2/BIO E3 V
SS
F3
A_BCLKR1 G3 A_BDX1 H3
VCO J3 TRST K3
A_INT0 L3 PPD14 HD14 M3
V
SS
N3 A_BFSR2 A4
A_BDX2 B4 A_BFSX2 C4
A_GPIO3
PPA9 D4 IOSTRB
A_TOUT
E4
A_GPIO0 F4 A_BFSX1 G4
A_BCLKX1 H4 TCK J4
PPD13 HD13 K4 PPD12 HD12 L4
A_BFSR0 M4 A_BDR0 N4
CV
DD
A5 V
SS
B5
A_BCLKR2 C5 A_BDR2 D5
A_BCLKR0 K5 A_BFSX0 L5
V
SS
M5 CV
DD
N5
CLKIN A6 DV
DD
B6
READY HRDY C6 A_BCLKX2 D6
A_BDX0 K6 A_BCLKX0 L6
MSTRB HCS M6 DS HDS2 N6
AV
DD
A7 V
SS
B7
V
SSA
C7 NC D7
DV
DD
K7 B_BDX0 L7
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Assignments for the TMS320VC5420GGU
(144-Pin MicroStar Ball Grid Array) (Continued)
PRIMARY
SIGNAL NAME
BALL
NO.
SECONDARY
SIGNAL NAME
PRIMARY
SIGNAL NAME
BALL
NO.
SECONDARY
SIGNAL NAME
PRIMARY
SIGNAL NAME
BALL
NO.
SECONDARY
SIGNAL NAME
PRIMARY
SIGNAL NAME
BALL
NO.
SECONDARY
SIGNAL NAME
PS HDS1 M7 B_BCLKX0 N7
B_BCLKX2 A8 B_BDX2 B8
B_BFSX2 C8 B_BCLKR2 D8
B_BDR0 K8 B_BCLKR0 L8
B_BFSX0 M8 V
SS
N8
CV
DD
A9 V
SS
B9
B_BDR2 C9 B_BFSR2 D9
R/W HR/W K9 B_BFSR0 L9
V
SS
M9 CV
DD
N9
PPD2 HD2 A10 PPD3 HD3 B10
PPA1 B_HINT C10 PPA5 D10
B_GPIO3
IS
B_TOUT
E10 B_BFSR1 F10
B_BCLKR1 G10 TEST H10
B_CLKOUT J10 PPA12 K10
SELA/B L10 PPA3 HCNTL0 M10
PPA2 HCNTL1 N10 DV
DD
A11
PPA4 HAS B11 V
SS
C11
B_INT0 D11 B_GPIO2/BIO E11
B_BDR1 F11 B_BFSX1 G11
V
SS
H11 B_XF J11
PPA13 K11 PPD10 HD10 L11
PPD9 HD9 M11 PPD8 HD8 N11
PPA6 A12 PPA14 B12
PPA16 C12 B_INT1 D12
B_GPIO1 E12 CV
DD
F12
B_BDX1 G12 CV
DD
H12
B_RS J12 HPIRS K12
DV
DD
L12 V
SS
M12
PPD11 HD11 N12 PPA7 A13
PPA15 B13 PPA17 C13
B_NMI D13 B_GPIO0 E13
V
SS
F13 V
SS
G13
B_BCLKX1 H13 XIO J13
HMODE K13 V
SS
L13
PPA11 M13 PPA10 N13
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
signal descriptions
The ’5420 signal descriptions table lists each pin name, function, and operating mode(s) for the ’5420 device.
Some of the ’5420 pins can be configured for one of two functions; a primary function and a secondary function.
The names of these pins in secondary mode are shaded in grey in the following table.
Signal Descriptions
NAME TYPE
†
DESCRIPTION
DATA SIGNALS
PPA17 (MSB)
PPA16
PPA1
5
PPA15
PPA14
PPA13
PPA12
Parallel port address bus. The DSP can access the external memory locations by way of the external memor
y
PPA12
PPA11
PPA10
PPA9
Parallel ort address bus. The DSP can access the external memory locations by way of the external memory
interface using PPA[17:0] in external memory interface (EMIF) mode when the XIO pin is logic high.
The PPA[17:0] pins are also multiplexed with the HPI interface. In HPI mode
(
XIO pin is low), the external address
PPA9
PPA8
PPA7
PPA6
I/O/Z
The PPA[17:0] ins are also multi lexed with the HPI interface. In HPI mode (XIO in is low), the external address
pins PPA[17:0] are used by a host processor for access to the memory map by way of the on-chip HPI. Refer
to the HPI section of this table for details on the secondary functions of these pins.
PPA6
PPA5
PPA4
‡§
PPA3
These pins are placed into the high-impedance state when OFF is low.
PPA3
PPA2
PPA1
PPA0 (LSB)
PPD15 (MSB)
PPD14
PPD13
PPD12
PPD11
PPD10
PPD9
PPD8
PPD7
PPD6
PPD5
PPD4
PPD3
PPD2
PPD1
PPD0 (LSB)
I/O/Z
¶
Parallel port data bus. The DSP uses this bidirectional data bus to access external memory when the device is
in external memory interface (EMIF) mode (the XIO pin is logic high).
This data bus is also multiplexed with the 16-bit HPI data bus. When in HPI mode, the bus is used to transfer data
between the host processor and internal DSP memory via the HPI. Refer to the HPI section of this table for details
on the secondary functions of these pins.
The data bus includes bus holders to reduce power dissipation caused by floating, unused pins. The bus holders
also eliminate the need for external pullup resistors on unused pins. When the data bus is not being driven by
the ’5420, the bus holders keep data pins at the last driven logic level. The data bus keepers are disabled at reset
and can be enabled/disabled via the BH bit of the BSCR register.
These pins are placed into high-impedance state when OFF
is low.
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
A_INT0
§
B_INT0
§
A_INT1
§
B_INT1
§
I
External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register (IMR) and
the interrupt mode bit. INT0
–INT3 can be polled and reset by way of the interrupt flag register (IFR).
A_NMI
§
B_NMI
§
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI
is activated, the processor traps to the appropriate vector location.
†
I = Input, O = Output, S = Supply, Z = High Impedance
‡
This pin has an internal pullup resistor.
§
These pins have Schmitt trigger inputs.
¶
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
#
This pin is used by Texas Instruments for device testing and should be left unconnected.
||
This pin has an internal pulldown resistor.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME DESCRIPTIONTYPE
†
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
A_RS
§
B_RS
§
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS
is brought to a high level, execution begins at location 0FF80h of program
memory. RS
affects various registers and status bits.
XIO I
The XIO pin is used to configure the parallel port as a host-port interface (HPI mode when XIO pin is low), or as
an asynchronous memory interface (EMIF mode when XIO pin is high).
At device reset, the logic combination of the XIO, HMODE, and SELA/B pin levels determines the initialization
value of the MP/MC bit (a bit in the processor mode status (PMST) register ) Refer to the memory section for
details.
GENERAL-PURPOSE I/O SIGNALS
A_XF
B_XF
O
External flag output (latched software-programmable output-only signal). Bit addressable. A_XF and B_XF are
placed into the high-impedance state when OFF
is low.
A_GPIO0
B_GPIO0
A_GPIO1
B_GPIO1
I/O
General-purpose I/O pins (software-programmable I/O signal). V alues can be latched (output) by writing into the
GPIO register. The states of GPIO pins (inputs) can be read by reading the GPIO register. The GPIO direction
is also programmable by way of the DIRn field in the GPIO register.
A_GPIO2/BIO
B_GPIO2/BIO
I/O
General-purpose I/O. These pins can be configured in the same manner as GPIO0–1; however in input mode,
the pins also operate as the traditional branch control bit (BIO
). If application code does not perform
BIO
-conditional instructions, these pins operate as general inputs.
PRIMARY
p
p
A_GPIO3
(A_TOUT)
IOSTRB
Wh
en the device is in
HPI
mode and
HMODE
= 0 (mu
ltipl
exed), these pins are controlle
d
by the general-purpose I/O control register. TOUT bit must be set to “1” to drive the timer
output on the pin. IF TOUT = 0, then these pins are general-purpose I/Os. In EMIF mode
B_GPIO3
(B_TOUT)
I/O
IS
O
out ut on the in. IF TOUT 0, then these ins are general ur ose I/Os. In EMIF mode
(XIO pin high), these signals serve their primary functions and are active during external
I/O space accesses.
MEMORY CONTROL SIGNALS
PS
‡
O
Program space select signal. The PS signal is asserted during external program space accesses. This pin is
placed into the high-impedance state when OFF
is low.
This pin is also multiplexed with the HPI, and functions as the HDS1
data strobe input signal in HPI mode. Refer
to the HPI section of this table for details on the secondary function of this pin.
DS
‡
O
Data space select signal. The DS signal is asserted during external data space accesses. This pin is placed into
the high-impedance state when OFF
is low.
This pin is also multiplexed with the HPI, and functions as the HDS2
data strobe input signal in HPI mode. Refer
to the HPI section of this table for details on the secondary function of this pin.
IS O
I/O space select signal. The IS signal is asserted during external I/O space accesses. This pin is placed into the
high-impedance state when OFF
is low.
This pin is also multiplexed with the general purpose I/O feature, and functions as the B_GPIO3 (B_TOUT)
input/output signal in HPI mode. Refer to the General Purpose I/O section of this table for details on the secondary
function of this pin.
MSTRB
‡§
O
Program and data memory strobe (active in EMIF mode). This pin is placed into the high-impedance state when
OFF
is low.
†
I = Input, O = Output, S = Supply, Z = High Impedance
‡
This pin has an internal pullup resistor.
§
These pins have Schmitt trigger inputs.
¶
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
#
This pin is used by Texas Instruments for device testing and should be left unconnected.
||
This pin has an internal pulldown resistor.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME DESCRIPTIONTYPE
†
MEMORY CONTROL SIGNALS (CONTINUED)
READY I
Data-ready input signal. READY indicates that the external device is prepared for a bus transaction to be
completed. If the device is not ready (READY = 0), the processor waits one cycle and checks READY again. The
processor performs the READY detection if at least two software wait states are programmed.
This pin is also multiplexed with the HPI, and functions as the Host-port data ready (output) in HPI mode. Refer
to the HPI section of this table for details on the secondary function of this pin.
R/W O
Read/write output signal. R/W indicates transfer direction during communication to an external device. R/W is
normally in the read mode (high), unless it is asserted low when the DSP performs a write operation.
This pin is also multiplexed with the HPI, and functions as the Host-port Read/write input in HPI mode. Refer to
the HPI section of this table for details on the secondary function of this pin.
This pin is placed into the high-impedance state when OFF
is low.
IOSTRB O
I/O space memory strobe. External I/O space is accessible by the CPU and not the direct memory access (DMA)
controller. The DMA has its own dedicated I/O space that is not accessible by the CPU.
This pin is also multiplexed with the general pupose I/O feature, and functions as the A_GPIO3(A_TOUT) signal
in HPI mode. Refer to the general purpose I/O section of this table for details on the secondary function of this
pin.
This pin is placed into the high-impedance state when OFF
is low.
SELA/B I
The SELA/B pin designates which DSP subsystem has access to the parallel-port interface. Furthermore, this
pin determines which subsystem is accessible by the host via the HPI.
For external memory accesses (XIO pin high), when SELA/B is low subsystem A has control of the external
memory interface. Similarly, when SELA/B is high subsystem B has control.
See Table 7 for a truth table of SELA/B, HMODE and XIO pins and functionality.
At device reset, the logic combination of the XIO, HMODE, and SELA/B pin levels determines the initialization
value of the MP/MC bit (a bit in the processor mode status (PMST) register ) Refer to the memory section for
details.
CLOCKING SIGNALS
A_CLKOUT
B_CLKOUT
O
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the falling edges of this signal. The CLKOUT pin can be turned off by writing a “1” to the CLKOFF
bit of the PMST register. CLKOUT goes into the high-impedance state when EMU1/OFF
is low.
CLKIN
§
I Input clock to the device. CLKIN connects to an oscillator circuit/device.
VCO O
VCO is the output of the voltage-controlled oscillator stage of the PLL. This is a 3-state output during normal
operation. Active in silicon test/debug mode.
MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS
A_BCLKR0
‡§
B_BCLKR0
‡§
A_BCLKR1
‡§
B_BCLKR1
‡§
A_BCLKR2
‡§
B_BCLKR2
‡§
I/O/Z
Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver . Input from an external
clock source for clocking data into the McBSP. When not being used as a clock, these pins can be used as
general-purpose I/O by setting RIOEN = 1.
BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register.
†
I = Input, O = Output, S = Supply, Z = High Impedance
‡
This pin has an internal pullup resistor.
§
These pins have Schmitt trigger inputs.
¶
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
#
This pin is used by Texas Instruments for device testing and should be left unconnected.
||
This pin has an internal pulldown resistor.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME DESCRIPTIONTYPE
†
MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS (CONTINUED)
A_BCLKX0
‡§
B_BCLKX0
‡§
A_BCLKX1
‡§
B_BCLKX1
‡§
A_BCLKX2
‡§
B_BCLKX2
‡§
I/O/Z
Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be configured as
an input by setting the CLKXM = 0 in the PCR register. BCLKX can be sampled as an input by way of the IN1
bit in the SPC register. When not being used as a clock, these pins can be used as general-purpose I/O by setting
XIOEN = 1.
These pins are placed into the high-impedance state when OFF
is low.
A_BDR0
B_BDR0
A_BDR1
B_BDR1
A_BDR2
B_BDR2
I
Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can be used as
general-purpose I/O by setting RIOEN = 1.
A_BDX0
B_BDX0
A_BDX1
B_BDX1
A_BDX2
B_BDX2
O/Z
Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins can be used as
general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF
is
low.
A_BFSR0
B_BFSR0
A_BFSR1
B_BFSR1
A_BFSR2
B_BFSR2
I/O/Z
Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the receive-data process
over BDR pin.
When not being used as data-receive synchronization pins, these pins can be used as
general-purpose I/O by setting RIOEN = 1.
A_BFSX0
B_BFSX0
A_BFSX1
B_BFSX1
A_BFSX2
B_BFSX2
I/O/Z
Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the transmit-data
process over BDX pin. If RS
is asserted when BFSX is configured as output, then BFSX is turned into input mode
by the reset operation.
When not being used as data-transmit synchronization pins, these pins can be used as
general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF
is
low.
HOST-PORT INTERFACE SIGNALS
PRIMARY
HPI address inputs. HA[0:17] are used by the host device, in the HPI non-multiplexed
mode
(
HMODE pin is high), to address the on-chip RAM of the ’5420. These pins are
HA[0:17] I PPA[0:17] O
mode (HMODE in is high), to address the on-chi RAM of the 5420. These ins are
shared with the external memory interface and are only used by the HPI when the interface
is in HPI mode (XIO pin is low).
HD[0:15] I/O/Z PPD[0:15]
I/O/Z
Parallel bidirectional data bus. HD[0:15] are used by the host device to transfer data to
and from the on-chip RAM of the ’5420. These pins are shared with the external memory
interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low).
The data bus includes bus holders to reduce power dissipation caused by floating, unused
pins. The bus holders also eliminate the need for external pullup resistors on unused pins.
When the data bus is not being driven by the ’5420, the bus holders keep data pins at the
last driven logic level. The data bus keepers are disabled at reset and can be
enabled/disabled via the BH bit of the BSCR register. These pins are placed into the
high-impedance state when OFF
is low.
†
I = Input, O = Output, S = Supply, Z = High Impedance
‡
This pin has an internal pullup resistor.
§
These pins have Schmitt trigger inputs.
¶
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
#
This pin is used by Texas Instruments for device testing and should be left unconnected.
||
This pin has an internal pulldown resistor.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME DESCRIPTIONTYPE
†
HOST-PORT INTERFACE SIGNALS (CONTINUED)
PRIMARY
HCNTL0
HCNTL1
I
PPA3
PPA2
O
HPI control inputs. The HCNTL0 and HCNTL1 values between HPIA, and HPID registers
during HPI reads and writes. These signals are only used in HPI multiplexed address/data
mode (HMODE pin is low).
These pins are shared with the external memory interface and are only used by the HPI
when the interface is in HPI mode (XIO pin is low).
HAS
‡§
I PPA4
‡§
O
Address strobe input. Hosts with multiplexed address and data pins require HAS to latch
the address in the HPIA register. This signal is only used in HPI multiplexed address/data
mode (HMODE pin is low).
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
HCS
‡§
I MSTRB
‡§
O
HPI chip-select signal. Thissignal must be active during HPI transfers, and can remain
active between concurrent transfers.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
HDS1
‡§
HDS2
‡§
I
PS
‡§
DS
‡§
O
HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes to control
transfer HPI transfers.
These pins are shared with the external memory interface and are only used by the HPI
when the interface is in HPI mode (XIO pin is low).
HR/W I R/W O
HPI read/write signal. This signal is used by the host to control the direction of an HPI
transfer.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
HRDY O READY I
HPI data-ready output. The ready output informs the host when the HPI is ready for the
next transfer.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low). HRDY is placed into the high-impedance state
when OFF
is low.
A_HINT
B_HINT
O
PPA0
PPA1
O
Host interrupt pin. HPI can interrupt the host by asserting this low. The host can clear this
interrupt by writing a “1” to the HINT
bit of the HPIC register. Only supported in HPI
multiplexed address/data mode (HMODE pin is low). These pins are placed into the
high-impedance state when OFF
is low.
HPIRS
§
I Host-port interface (HPI) reset pin. This signal resets the host port interface and both subsystems.
HMODE I
Host mode select. When this pin is low it selects the HPI multiplexed address/data mode. The multiplexed
address/data mode allows hosts with multiplexed address/data lines access to the HPI registers HPIC, HPIA,
and HPID. Host-to-DSP and DSP-to-host interrupts are supported in this mode.
When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts with
separate address/data buses to access the HPI address range by way of the 18-bit address bus and the HPI data
(HPID) register via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not supported in this mode.
SUPPLY PINS
AV
DD
S Dedicated power supply that powers the PLL. AVDD = 1.8 V. AVDD can be connected to CVDD.
CV
DD
S Dedicated power supply that powers the core CPUs. CVDD = 1.8 V
DV
DD
S Dedicated power supply that powers the I/O pins. DVDD = 3.3 V
V
SS
S Digital ground. Dedicated ground plane for the device.
†
I = Input, O = Output, S = Supply, Z = High Impedance
‡
This pin has an internal pullup resistor.
§
These pins have Schmitt trigger inputs.
¶
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
#
This pin is used by Texas Instruments for device testing and should be left unconnected.
||
This pin has an internal pulldown resistor.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME DESCRIPTIONTYPE
†
SUPPLY PINS (CONTINUED)
V
SSA
S
Analog ground. Dedicated ground for the PLL. V
SSA
can be connected to VSS if digital and analog grounds are
not separated.
TEST PIN
TEST
#
No connection
EMULATION/TEST PINS
TCK
‡§
I
Standard test clock. This is normally a free-running clock signal with a 50% duty cycle. Changes on the test
access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or
selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling
edge of TCK.
TDI
‡
I
Test data input. Pin with an internal pullup device. TDI is clocked into the selected register (instruction or data)
on a rising edge of TCK.
TDO O
Test data pin. The contents of the selected register is shifted out of TDO on the falling edge of TCK. TDO is in
high-impedance state except when the scanning of data is in progress. These pins are placed into high-impedance state when OFF
is low.
TMS
‡
I
Test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on
the rising edge of TCK.
TRST
||
I
T est reset. When high, TRST gives the scan system control of the operations of the device. If TRST is driven low,
the device operates in its functional mode and the emulation signals are ignored. Pin with internal pulldown
device.
EMU0 I/O/Z
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined
as I/O.
EMU1/OFF I/O/Z
Emulator interrupt 1 pin. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator
system and is defined as I/O. When TRST
transitions from high to low, then EMU1 operates as OFF. EMU/OFF
= 0 puts all output drivers into the high-impedance state.
Note that OFF is used exclusively for testing and emulation purposes (and not for multiprocessing applications).
Therefore, for the OFF
condition, the following conditions apply:
TRST = 0, EMU0 = 1, EMU1 = 0
†
I = Input, O = Output, S = Supply, Z = High Impedance
‡
This pin has an internal pullup resistor.
§
These pins have Schmitt trigger inputs.
¶
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
#
This pin is used by Texas Instruments for device testing and should be left unconnected.
||
This pin has an internal pulldown resistor.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional overview
GPIO[3:0]
DMA Bus
48K Prog/Data
SARAM
McBSP0
McBSP1
McBSP2
Peripheral Bus
APLL
TIMER
JTAG
Clocks
CPU BUS
DMA
(6 channels)
’C54x Core A
Modified HPI16
DSP Subsystem A
GPIO[3:0]
McBSP0
McBSP1
DMA Bus
Peripheral Bus
36K
Program
SARAM
CPU Bus
48K Prog/Data
SARAM
Peripheral
Bus
Bridge
P, C, D, E Buses and Control Signals
McBSP2
TIMER
JTAG
Host Access Bus
DMA
(6 channels)
’C54x Core B
Modified HPI16
DSP Subsystem B
Interprocessor IRQ’s
16K Prog/Data
DARAM
Core-to-Core
FIFO Interface
16K Prog/Data
DARAM
Pbus
Cbus
Dbus
Ebus
Pbus
Pbus
Cbus
Dbus
Ebus
Pbus
Cbus
Dbus
Ebus
Pheripheral Bus
DMA BusDMA Bus
Pbus
Cbus
Dbus
Ebus
Pbus
Pbus
Cbus
Dbus
Ebus
Pbus
Cbus
Dbus
Ebus
Peripheral Bus
DMA Bus
36K
Program
SARAM
Ebus
Ebus
P, C, D, E Buses and Control Signals
Peripheral
Bus
Bridge
Host Access Bus
Figure 1. Functional Block Diagram
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory
The total memory address range for each ’5420 subsystem is 384K 16-bit words. The memory space is divided
into three specific memory segments: 256K-word program, 64K-word data, and 64K-word I/O. The program
memory space contains the instructions to be executed as well as tables used in execution. The data memory
space stores data used by the instructions. The I/O memory space is used to interface to external
memory-mapped peripherals and can also serve as extra data storage space. The CPU I/O space should not
be confused with the DMA I/O space, which is completely independent and not accessible by the CPU.
on-chip dual-access RAM (DARAM)
The ’5420 subsystems A and B each have 16K
× 16-bit on-chip DARAM (2 blocks of 8K words).
Each of these RAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store
data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory
space. DARAM can be mapped into program/data memory space by setting the OVL Y bit in the PMST register.
on-chip single-access RAM (SARAM)
The ’5420 subsystems A and B each have 84K-word × 16-bit on-chip SARAM (ten blocks of 8K words each and
one block of 4K words).
Each of these SARAM blocks is a single-access memory . This memory is intended primarily to store data values;
however, it can be used to store program as well. At reset, the SARAM (4000h–7FFFh) is mapped into data
memory space. This memory range can be mapped into program/data memory space by setting the OVL Y bit
in the PMST register. The SARAM at 8000h–FFFFh is program memory at reset and can be configured as
program/data memory by setting the DROM bit. SARAM spaces18000h–1FFFFh and 2F000h–2FFFFh are
mapped as program memory only.
program memory
The ’5420 device features a paged extended memory scheme in program space to allow access of up to 256K
of program memory relative to each subsystem. This extended program memory (each subsystem) is organized
into four pages (0–3), each 64K in length. A hardware pin is used to select which DSP subsystem (A or B) has
control of the external memory interface. To implement the extended program memory scheme, the ’5420
device includes the following features:
Two additional address lines (for a total of 18)
A pin (SELA/B) for external memory interface arbitration between subsystem A and B
data memory
The data memory space on each ’5420 subsystem contains up to 64K 16-bit word addresses. The device
automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated
outside the RAM bounds, the device automatically generates an external access.
parallel I/O ports
Each subsystem of the ’5420 has a total of 64K I/O ports. These ports can be addressed by PORTR and
PORTW . The IS
signal indicates the read/write access through an I/O port. The devices can interface easily with
external devices through the I/O ports while requiring minimal off-chip address-decoding logic. The SELA/B pin
selects which subsystem has access to the external I/O space.
external memory interface
The ’5420 has a single external memory interface shared between both subsystems. The external memory
interface enables the ’5420 subsystems to connect to external memory devices or other parallel interfaces. The
SELA/B pin is used to determine which subsystem has access to the external memory interface. When the
SELA/B pin is low , subsystem A has access to the external memory interface, and when it is high, subsystem
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
external memory interface (continued)
B has access to the interface. The external memory interface is also shared with the host port interface (HPI).
The XIO pin is used to select between the external memory interface and the hostport interface. When the XIO
pin is high, the external memory interface is active, and when it is low, the host port interface is active.
processor mode status register (PMST)
Each subsystem has a processor-mode status register (PMST) that controls memory configuration. The bit
layout of the PMST register is shown in Figure 1
15 76543210
IPTR
MP/MC OVLY AVIS DROM CLKOFF SMUL SST
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R = Read, W = Write
Figure 1. Processor Mode Status Register (PMST) Bit Layout
The functions of the PMST register bits are illustrated in the memory map. The MP/MC bit is used to map the
upper address range of all program space pages (x8000–xFFFF) as either external or internal memory. The
OVL Y bit is used to overlay the on-chip DARAM0 and SARAM1 blocks from dataspace onto to program space.
Similarly, the DROM bit is used to overlay the SARAM2 block from program space onto data space. See the
TMS320C54x DSP CPU and Peripherals Reference Set, Volume 1
(literature number SPRU131) for a
description of the other bits of the PMST register.
Due to the dual-processor configuration and the several EMIF/HPI options available, the MP/MC bit is initialized
at the time of device reset to a logic level that is dependent on the XIO, HMODE, and SELA/B pins. Table 1
shows the initialized logic level of the MP/MC bit and how it depends on these pins.
Table 1. MP/MC Bit Logic Levels at Reset
’5420 PINS MP/MC BIT
XIO HMODE SELA/B SUBSYSTEM A SUBSYSTEM B
0 X X 0 0
1 0 X 1 1
1 1 0 1 0
1 1 1 0 1
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map
Memory-
Mapped
Registers
Scratch-Pad
DARAM
On-Chip
DARAM 0
(16K Words)
On-Chip
SARAM 1
(16K Words)
On-Chip
SARAM 2
(32K Words)
Prog/Data
(DROM=1)
External
(DROM=0)
†
0000
005F
0060
007F
0080
3FFF
4000
7FFF
8000
FFFF
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 2
(32K Words)
Prog/Data
(MP/MC=0)
0000
3FFF
4000
7FFF
8000
FFFF
DataHex Program Page 0Hex
External
(OVLY=0)
†
External
(OVLY=0)
†
External
(MP/MC=1)
†
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 3
(32KWords)
(MP/MC=0)
10000
13FFF
14000
17FFF
18000
1FFFF
Program Page 1Hex
External
(OVLY=0)
†
External
(OVLY=0)
†
External
(MP/MC=1)
†
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 4
(4K Words)
(MP/MC=0)
20000
23FFF
24000
27FFF
28000
2FFFF
Program Page 2Hex
External
(OVLY=0)
†
External
(OVLY=0)
†
External
(MP/MC=1)
†
Reserved
(MP/MC=0)
External
(MP/MC=1)
†
2EFFF
2F000
(extended)
(extended) (extended)
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
30000
33FFF
34000
37FFF
38000
3FFFF
Program Page 3Hex
External
(OVLY=0)
†
External
(OVLY=0)
†
Reserved
(MP/MC=0)
External
(MP/MC=1)
†
(extended)
0000
FFFF
I/OHex
64K
External
I/O Ports
†
†
The external memory interface must be enabled by driving the XIO pin high, in order for external memory accesses to occur.
Figure 2. Memory Map for Each CPU Subsystem
multicore reset signals
The ’5420 device includes three reset signals: A_RS, B_RS, and HPIRS. The A_RS and B_RS pins function
as the CPU reset signal for subsystem A and subsystem B, respectively. These signals reset the state of the
CPU registers and upon release, initiates the reset function. Additionally, the A_RS signal resets the on-chip
PLL and initializes the CLKMD register to bypass mode.
The HPI reset signal (HPIRS) places the HPI peripheral into a reset state. It is necessary to wait three clock
cycles after the rising edge of HPIRS
before performing an HPI access.
reset vector initialization
The ’5420 device does not have on-chip ROM and therefore does not contain bootloader routines/software.
Consequently , the user must have a valid reset vector in place before releasing the reset signal. This is referred
to as
reset vector initialization
. After reset, the ’5420 device fetches the reset vector at address 0xFF80 in
program memory and begins to execute the instructions found in memory . The application code is raw program
and data words and does not require the traditional
boot-table
or
boot-packet
format.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
reset vectorinitialization (continued)
The selection of the reset initialization option is determined by the state of three pins; XIO, XMODE, and SELA/B.
The options include:
HPI (host-dependent)
EMIF-to-HPI (stand-alone)
Simultaneous EMIF (stand-alone)
Sequential EMIF (stand-alone)
HPI
The HPI method is only valid when the level of the XIO pin is low. The ’5420 acts as a slave to an external master
host. The host device must keep the ’5420 device in reset as it downloads code to the subsystem that is
determined by the logic level of the SELA/B pin. When SELA/B is low, the master downloads code to
subsystem A. By driving SELA/B high, the master host can subsequently download code to subsystem B. The
HMODE pin determines the configuration of the HPI (multiplexed or nonmultiplexed) and is an asynchronous
input. Therefore, HMODE can be changed to the desired configuration while A_RS
and B_RS are low prior to
the transfer. Once the subsystem(s) have been loaded and are ready to execute, the master host can release
the reset pin(s).
There are two valid options for controlling the reset function of the subsystems. The first option is to hold the
A_RS and B_RS pins low while the HPIRS pin transitions from low to high. This keeps the cores in reset while
allowing the HPI full access to download the application code. The host can now drive the A_RS
and B_RS
signals high simultaneously or separately to release the respective subsystem from reset. The subsystems then
fetch their respective reset vector. If the subsystems are released from reset seperately, subsystem A should
be released from reset first, since the A_RS pin resets the on-chip PLL that is common to both subsystems.
Another valid option is to keep the A_RS and B_RS pins high while the host transitions the HPIRS pin from low
to high. Special internal logic causes the HPI to be fully operable and the cores remain in reset. As a result, after
the host processor has downloaded the application code via the HPI, it must perform an additional HPI write
(any value) to address 0x2F. This releases the respective subsystem from reset. By changing the value of
SELA/B, the host can write to 0x2F via the HPI to release the other subsystem from reset.
EMIF-to-HPI
In this particular vector initialization method, the host processor controlling the HPI is one of the subsystems.
The master host is subsystem A if SELA/B is low and subsystem B when SELA/B is high. As described in the
signal descriptions table, the address, data, and control signals of the program space are multiplexed with the
HPI signals. In a special mode when XIO is high (EMIF mode) and HMODE is high (HPI nonmultiplexed mode),
these multiplexed signals are connected, making it possible for the master subsystem’s EMIF to initialize the
slave subsystem via the slave’s HPI. The master subsystem then releases the slave from reset either by
transitioning the hardware reset signal (x_RS
) high, or in software, by writing to memory location 0x2F via the
HPI. As a result, the slave core fetches the reset vector.
simultaneous EMIF
The simultaneous EMIF vector initialization option allows both subsystems to access external memory
simultaneously . The subsystems are designed to operate synchronized with one another while accessing the
same locations simultaneously . In this mode, when XIO is high and HMODE is low , one subsystem is given full
control of the EMIF while the other subsystem relies on the synchronization of the two subsystems. Instructions
fetched by one subsystem are ready for both subsystems to execute. After the application code is executed or
transferred to internal memory, write accesses to external memory are prohibited.
This method requires the A_RS and B_RS pins to be tied high while HPIRS transitions from low to high. When
HPIRS transitions high, both subsystems fetches the same reset vector.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
sequential EMIF
The sequential EMIF option allows one master subsystem to run from external memory while controlling the
slave subsystem’s RS signal and the SELA/B pin. At system reset, only the master subsystem is actually reset.
Upon a low-to-high transition of the master’s RS signal, the master subsystem fetches the reset vector and
proceeds to copy external application code to internal memory space. The master subsystem begins executing
the application code, then changes the state of SELA/B, relinquishing the external EMIF to the slave subsystem.
The master then releases the slave RS
signal. As a result, the slave fetches the reset vector and begins to copy
the external application code to internal memory space. Note, GPIO pins on the master subsystem can be used
to control the SELA/B and slave reset (x_RS) pins externally.
on-chip peripherals
All the ’54x devices have the same CPU structure; however, they have dif ferent on-chip peripherals connected
to their CPUs. The on-chip peripheral options provided on each subsystem of the ’5420 are:
Software-programmable wait-state generator
Programmable bank-switching
16-bit host-port interface (HPI16)
Multichannel buffered serial ports (McBSPs)
A hardware timer
A software-programmable clock generator with a phase-locked loop (PLL)
software-programmable wait-state generators
The Software-programmable wait-state generator can be used to extend external bus cycles up to fourteen
machine cycles to interface with slower off-chip memory and I/O devices. Note that all external memory
accesses on the ’5420 require at least one wait state. The software wait-state register (SWWSR) controls the
operation of the wait-state generator. The SWWSR of a particular DSP subsystem (A or B) is used for the
external memory interface, depending on the logic level of the SELA/B pin.The 14 LSBs of the SWWSR specify
the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges.
This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized
to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3
and described in Table 2.
XPA I/O Data Data Program Program
14 12 11 9 8 6 5 3 2 015
R/W-111R/W-0 R/W-111 R/W-111 R/W-111 R/W-111
LEGEND: R=Read, W=Write, 0=V alue after reset
Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
software-programmable wait-state generator (continued)
Table 2. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
NO. NAME
RESET
VALUE
FUNCTION
15 XPA 0
Extended program address control bit. XP A is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
14–12 I/O 1
I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
11–9 Data 1
Upper data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
8–6 Data 1
Lower data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
5–3 Program 1
Upper program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
XPA = 0: x8000 – xFFFFh
XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
2–0 Program 1
Program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
XPA = 0: x0000–x7FFFh
XP A = 1: 00000–3FFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described
in Table 3.
Reserved
115
R/W-0
SWSM
0
R/W-0
LEGEND: R = Read, W = Write
Figure 4. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3. Software Wait-State Control Register (SWCR) Bit Fields
PIN
RESET
NO. NAME
RESET
VALUE
FUNCTION
15–1 Reserved 0
These bits are reserved and are unaffected by writes.
0 SWSM 0
Software wait-state multiplier . Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
programmable bank-switching
Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank
boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from
program-memory space to data-memory space (’54x) or one program memory page to another program
memory page. This extra cycle allows memory devices to release the bus before other devices start driving the
bus; thereby avoiding bus contention. The size of the memory bank for the bank-switching is defined by the
bank-switching control register (BSCR). The BSCR of a particular DSP subsystem (A or B) is used for the
external memory interface depending on the logic level of the SELA/B pin.
15 12 11 10 9 8 7 3 2 1 0
BNKCMP
PS-DS Reserved IPIRQ Reserved BH Reserved EXIO
R/W R/W R/W R/W R/W R/W
LEGEND: R = Read, W = Write
Figure 5. BSCR Register Bit Layout for Each DSP Subsystem
Table 4. BSCR Register Bit Functions for Each DSP Subsystem
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
15–12 BNKCMP 1111
Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four
MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared,
resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
11 PS-DS 1
Program read – data read access. PS-DS inserts an extra cycle between consecutive accesses of
program read and data read or data read and program read.
PS-DS = 0 No extra cycles are inserted by this feature.
PS-DS = 1 One extra cycle is inserted between consecutive data and program reads.
10–9 Reserved 0 These bits are reserved and are unaffected by writes.
8 IPIRQ 0
The IPIRQ bit is used to send an interprocessor interrupt to the other subsystem. IPIRQ=1 sends the
interrupt. IPIRQ must be cleared before subsequent interrupts can be made. Refer to the interrupts section
for more details
7–3 Reserved 0 These bits are reserved and are unaffected by writes.
2 BH 0
Bus holder. BH controls the data bus holder feature: BH is cleared to 0 at reset.
BH = 0 The bus holder is disabled.
BH = 1 The bus holder is enabled. When not driven, the data bus (PPD[15:0]) is held in the
previous logic level.
1 Reserved 0 These bits are reserved and are unaffected by writes.
0 EXIO 0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0 The external bus interface functions as usual.
EXIO = 1 The address bus, data bus, and control signals become inactive after completing the
current bus cycle. Note that the DROM, MP/MC
, and OVLY bits in the PMST and the
HM bit of ST1 cannot be modified when the interface is disabled.
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
16-bit host-port interface (HPI16)
The HPI16 is an enhanced 16-bit version of the ’C54x 8-bit host-port interface (HPI). The HPI16 is designed
to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface.
Figure 6 illustrates the available memory accessible by the HPI. It should be noted that neither the CPU nor DMA
I/O spaces can be accessed using the host-port interface.
16-bit bidirectional host-port interface (HPI16)
Program Page 0
Reserved
McBSP
DXR/DRR
MMRegs Only
On-Chip
DARAM 0
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(Overlayed)
Prog/Data
On-Chip
SARAM 2
(32K Words)
Prog/Data
Hex
0000
001F
0020
005F
0060
3FFF
4000
7FFF
8000
FFFF
Program Page 1
Reserved
On-Chip
DARAM 0
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(Overlayed)
Prog/Data
On-Chip
SARAM 3
(32K Words)
Program
Hex
10000
13FFF
14000
17FFF
18000
1FFFF
Program Page 2
Reserved
On-Chip
DARAM 0
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(Overlayed)
Prog/Data
On-Chip
SARAM 4
(4K Words)
Program
Hex
20000
23FFF
24000
27FFF
28000
2FFFF
Reserved
2EFFF
2F000
Program Page 3
Reserved
On-Chip
DARAM 0
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(Overlayed)
Prog/Data
Hex
30000
33FFF
34000
37FFF
38000
3FFFF
Reserved
1005F
10060
2005F
20060
3005F
30060
Figure 6. Memory Map Relative to Host-Port interface
TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
16-bit bidirectional host-port interface (HPI16) (continued)
Some of the features of the HPI16 include:
16-bit bidirectional data bus
Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts
Multiplexed
and
nonmultiplexed address/data modes
18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal
extended address pages)
18-bit address register used in multiplexed mode. Includes address autoincrement feature for faster
accesses to sequential addresses
Interface to on-chip DMA module to allow access to entire internal memory space
HRDY signal to hold off host accesses due to DMA latency
Control register available in
multiplexed
mode only . Accessible by either host or DSP to provide host/DSP
interrupts, extended addressing, and data prefetch capability
The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP . There
are two modes of operation as determined by the HMODE signal:
multiplexed
mode and
nonmultiplexed
mode.
HPI multiplexed mode
In
multiplexed
mode, HPI16 operation is very similar to the standard 8-bit HPI, which is available with other ’C54x
products. A host with a multiplexed address/data bus can access the HPI16 data register (HPID), address
register (HPIA), or control register (HPIC) via the HD bidirectional data bus. The host initiates the access with
the strobe signals (HDS1
, HDS2, HCS) and controls the type of access with the HCNTL, HR/W, and HAS
signals. The DSP can interrupt the host via the HINT signal, and can stall host accesses via the HRDY signal.
host/DSP interrupts
In
multiplexed
mode, the HPI16 offers the capability for the host and DSP to interrupt each other through the
HPIC register.
For host-to-DSP interrupts, the host must write a “1” to the DSPINT bit of the HPIC register. This generates an
interrupt to the DSP . This interrupt can also be used to wake the DSP from any of the IDLE 1,2, or 3 states. Note
that the DSPINT bit is always read as “0” by both the host and DSP.
For DSP-to-host interrupts, the DSP must write a “1” to the HINT bit of the HPIC register to interrupt the host
via the HINT
pin. The host acknowledges and clear this interrupt by also writing a “1” to the HINT bit of the HPIC
register. Note that writing a “0” to the HINT bit by either host or DSP has no effect.
HPI nonmultiplexed mode
In
nonmultiplexed
mode, a host with separate address/data buses can access the HPI16 data register (HPID)
via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 18-bit HA address bus. The host
initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with
the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not
available in
nonmultiplexed
mode since there are no HCNTL signals available. All host accesses initiate a DMA
read or write access.
other HPI16 system considerations
operation during IDLE2
The HPI16 can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns
on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power .
The DSP CPU does not wake up from the IDLE mode during this process.
Loading...