Texas Instruments TMS320F206PZA, TMS320F206PZ Datasheet

D

High-Performance Static CMOS Technology

D

Includes the T320C2xLP Core CPU

D

TMS320F206 is a Member of the
TMS320C20x Generation, Which Also
Includes the TMS320C203, and
TMS320C209 Devices

D

Instruction-Cycle Time 50 ns @ 5 V

D

Source Code Compatible With TMS320C25

D

Upwardly Code-Compatible With
TMS320C5x Devices

D

Three External Interrupts

D

TMS320F206 Integrated Memory:
– 544 × 16 Words of On-Chip Dual-Access

Data RAM

– 32K × 16 Words of On-Chip Flash

Memory (EEPROM)

– 4K × 16 Words of On-Chip Single-Access

Program/Data RAM

D

224K × 16-Bit Maximum Addressable
External Memory Space
– 64K Program
– 64K Data
– 64K Input/Output (I/O)

description

– 32K Global

TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

D

32-Bit ALU/Accumulator

D

16 × 16-Bit Multiplier With a 32-Bit Product

D

Block Moves from Data and Program
Space

D

TMS320F206 Peripherals:
– On-Chip 16-Bit Timer
– On-Chip Software-Programmable

Wait-State (0 to 7) Generator
– On-Chip Oscillator
– On-Chip Phase-Locked Loop (PLL)
– Six General-Purpose I/O Pins
– Full-Duplex Asynchronous Serial Port

(UART)
– Enhanced Synchronous Serial Port

(ESSP) With Four-Level-Deep FIFOs

D

Input Clock Options
– Options – Multiply-by-One, -Two, or -Four

and Divide-by-Two

D

Support of Hardware Wait States

D

Power Down IDLE Mode

D

IEEE 1149.1†-Compatible Scan-Based
Emulation

D

100-Pin Thin Quad Flat Package (TQFP)
(PZ Suffix)

The TMS320F206 Texas Instruments (TI) digital signal processor (DSP) is fabricated with static CMOS
integrated-circuit technology, and the architectural design is based upon that of the TMS320C20x series,
optimized for low-power operation. The combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory , and a highly specialized instruction set is the basis of the operational flexibility and speed of
the ’F206.

The ’F206 offers these advantages:

D

32K  16 words on-chip flash EEPROM reduces system cost and facilitates prototyping

D

Enhanced TMS320 architectural design for increased performance and versatility

D

Advanced integrated-circuit processing technology for increased performance

D

’F206 devices are pin- and code-compatible with ’C203 devices.

D

Source code for the ’F206 DSP is software-compatible with the ’C1x and ’C2x DSPs and is upwardly
compatible with fifth-generation DSPs (’C5x)

D

New static-design techniques for minimizing power consumption and increasing radiation tolerance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.
†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1998, Texas Instruments Incorporated

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

1

TMS320F206
DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

PZ PACKAGE

(TOP VIEW)

EMU0

EMU1/ OFF

TCK

TRST

TDI

TMS

TDO

V

CLKR

FSR

DR

CLKX

V
FSX

DX

V

TOUT

V

RX
IO0
IO1

BIO

RS

A14

DIV1

A13

CCP

V

SS

A12VA11

DIV2

HOLDA

V

SS

A10A9A8VA7VA6A5A4VA3A2A1A0VPSIS

X1

DD

DD

IO2

IO3

V

PLL5V

CLKIN/X2

DD

V

A15

76
77
78
79
80
81
82
83

SS

84
85
86
87
88

SS

89
90
91

DD

92
93

TX

94

SS

95
96
97
98

XF

99

TEST

MP/ MC

DD

SS

V

CLKOUT1

CCP

V

SS

NMI

HOLD / INT1

INT2

INT3

SS

V

SS

D0D1D2

DS

51525354555657585960616263646566676869707172737475

V

50

DD

READY

49

V

48

SS

R/W

47

STRB

46

RD

45

WE

44

BR

43

V

42

SS

D15

41

D14

40

D13

39

D12

38

V

37

SS

D11

36

V

35

DD

D10

34

D9

33

D8

32

D7

31

V

30

SS

D6

29

D5

28

D4

27

D3

26100

25242322212019181716151413121110987654321

SS

V

T able 1 shows the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the execution
time of one machine cycle, and the type of package with total pin count of the TMS320F206 device.

Table 1. Characteristics of the TMS320F206 Processor

ON-CHIP MEMORY

FLASH

EEPROM

DEVICE

RAM ROM

DATA

DATA/
PROG

PROG PROG SERIAL PARALLEL

TMS320F206 288 4K + 256 – 32K 2 64K 5 50 100-pin TQFP

I/O PORTS

POWER
SUPPLY

CYCLE

TIME

PACKAGE

TYPE WITH

(V) (ns) PIN COUNT

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TYPE

†

DESCRIPTION

TMS320F206 Terminal Functions

TERMINAL

NAME NO.

DATA AND ADDRESS BUSES

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

PS 53 O/Z

DS 51 O/Z

IS 52 O/Z

READY 49 I

R/W 47 O/Z

RD 45 O/Z

†

I = input, O = output, Z = high impedance, PWR = power, GND = ground

41
40
39
38
36
34
33
32
31
29
28
27
26
24
23
22

74
73
72
71
69
68
67
66
64
62
61
60
58
57
56
55

I/O/Z

O/Z

Parallel data bus D15 [most significant bit (MSB)] through D0 [least significant bit (LSB)]. D15–D0 are
used to transfer data between the TMS320F206 and external data /program memory or I/O devices.
Placed in the high-impedance state when not outputting (R/W
the high-impedance state when OFF

Parallel address bus A15 (MSB) through A0 (LSB). A15–A0 are used to address external data/program
memory or I/O devices. These signals go into the high-impedance state when OFF

MEMORY CONTROL SIGNALS

Program-select signal. PS is always high unless low-level asserted for communicating to off-chip program
space. PS

Data-select signal. DS is always high unless low-level asserted for communicating to off-chip program
space. DS

I/O space-select signal. IS is always high unless low-level asserted for communicating to I/O ports. IS
goes into the high-impedance state when OFF is active low.

Data-ready input. READY indicates that an external device is prepared for the bus transaction to be
completed. If the external device is not ready (READY low), the TMS320F206 waits one cycle and checks
READY again. If READY is not used, it should be pulled high.

Read/write signal. R/W indicates transfer direction when communicating with an external device. R/W
is normally in read mode (high), unless low level is asserted for performing a write operation. R/W goes
into the high-impedance state when OFF

Read-select indicates an active, external read cycle. RD is active on all external program, data, and I/O
reads. RD
be programmed to provide an inverted R/W
register controls this selection.

goes into the high-impedance state when OFF is active low.

goes into the high-impedance state when OFF is active low.

goes into the high-impedance state when OFF is active low. The function of the RD pin can

TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

high) or RS when asserted. They go into

is active low.

is active low.

is active low.

signal instead of RD. The FRDN bit (bit 15) in the PMST

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

3

TMS320F206

TYPE

†

DESCRIPTION

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

TMS320F206 Terminal Functions (Continued)

TERMINAL

NAME NO.

MEMORY CONTROL SIGNALS (CONTINUED)

Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15–D0). Data

WE 44 O/Z

STRB 46 O/Z

BR 43 O/Z

HOLDA 6 O/Z

XF 98 O/Z

BIO 99 I Branch control input. When polled by the BIOZ instruction, if BIO is low, the TMS320F206 executes a branch.
IO0

IO1
IO2
IO3

RS 100 I

TEST 1 I Reserved input pin. TEST is connected to VSS for normal operation.

MP/MC 2 I

NMI 17 I

HOLD/INT1 18 I

INT2
INT3

TOUT 92 O/Z

CLKOUT1 15 O/Z

CLKIN/X2
X1

†

I = input, O = output, Z = high impedance, PWR = power, GND = ground

96
97

19
20

12
13

I/O/Z

8
9

can be latched by an external device on the rising edge of WE
I/O writes. WE

Strobe signal. STRB is always high unless asserted low to indicate an external bus cycle. STRB goes into the
high-impedance state when OFF

Bus-request signal. BR is asserted when a global data-memory access is initiated. BR goes into the
high-impedance state when OFF

Hold-acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and
that the address, data, and memory control lines are in the high-impedance state so that they are available to
the external circuitry for access of local memory. HOLDA
active low.

External flag output (latched software-programmable signal). XF is used for signalling other processors in
multiprocessing configurations or as a general-purpose output pin. XF goes into the high-impedance state
when OFF

Software-controlled input /output pins by way of the asynchronous serial-port control register (ASPCR). At
reset, IO0–IO3 are configured as inputs. These pins can be used as general-purpose input/output pins or as
handshake control for the UART. IO0–IO3 go into the high-impedance state when OFF
IO0 also functions as a frame-sync output when the synchronous serial port (SSP) is used in multichannel
mode.

INITIALIZATION, INTERRUPTS, AND RESET OPERATIONS

Reset input. RS causes the TMS320F206 to terminate execution and forces the program counter to zero.
When RS
registers and status bits.

Microprocessor/microcomputer-mode-select pin. If MP/MC is low, the on-chip flash memory is mapped into
program space. When MP/MC
and its value is latched into bit 0 of the PMST register.

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the interrupt-mode bit
(INTM) or the interrupt mask register (IMR). When NMI
vector location. If NMI

HOLD and INT1 share the same pin. Both are treated as interrupt signals. If the MODE bit is 0 in the
interrupt-control register (ICR), hold logic can be implemented in combination with the IDLE instruction in
software. At reset, the MODE bit in ICR is zero, enabling the HOLD mode for the pin.

External user interrupts. INT2 and INT3 are prioritized and maskable by the IMR and the INTM. INT2 and INT3

I

can be polled and reset by way of the interrupt flag register (IFR).

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one
CLKOUT1-cycle wide. TOUT goes into the high-impedance state when OFF

Master clock output signal. The CLKOUT1 signal cycles at the machine-cycle rate of the CPU. The internal
machine cycle is bounded by the rising edges of CLKOUT1. CLKOUT1 goes into the high-impedance state
when OFF

Input clock. CLKIN/X2 is the input clock to the device. As CLKIN, the pin operates as the external oscillator

I

clock input, and as X2, the pin operates as the internal oscillator input with X1 being the internal oscillator

O

output.

goes into the high-impedance state when OFF is active low.

is active low.

MULTI-PROCESSING SIGNALS

is active low.

is active low.

is brought high, execution begins at location 0 of program memory after 16 cycles. RS affects various

is high, the device accesses off-chip memory . This pin is only sampled at reset,

is not used, it should be pulled high.

OSCILLATOR, PLL, AND TIMER SIGNALS

is active low.

. WE is active on all external program, data, and

goes into the high-impedance state when OFF is

is active low.

is activated, the processor traps to the appropriate

is active low.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TYPE

†

DESCRIPTION

TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

TMS320F206 Terminal Functions (Continued)

TERMINAL

NAME NO.

OSCILLATOR, PLL, AND TIMER SIGNALS (CONTINUED)

DIV1
DIV2

PLL5V 10 I The TMS320F206 is strictly a 5-V device. For this reason, the PLL5V pin should always be pulled high.

CLKX 87 I/O/Z

CLKR 84 I/O/Z

FSR 85 I/O/Z

FSX 89 I/O/Z

DR 86 I Serial-data receive input. Serial data is received in the receive shift register (RSR) through the DR pin.
DX 90 O/Z
TX 93 O/Z Asynchronous transmit data pin. TX is in the high-impedance state when OFF is active low.

RX 95 I Asynchronous receive data pin

TRST 79 I

TCK 78 I

TMS 81 I JTAG test-mode select. TMS is clocked into the TAP controller on the rising edge of TCK.
TDI 80 I JTAG test-data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.

TDO 82 O/Z

EMU0 76 I/O/Z

EMU1/OFF 77 I/O/Z

†

I = input, O = output, Z = high impedance, PWR = power, GND = ground

3
5

DIV1 and DIV2 provide clock-mode inputs.

I

DIV1–DIV2 should not be changed unless the RS

SERIAL PORT AND UART SIGNALS

Transmit clock. CLKX is a clock signal for clocking data from the serial-port transmit shift register (XSR) to the
DX data-transmit pin. The CLKX can be an input if the MCM bit in the synchronous serial-port control register
(SSPCR) is set to 0. CLKX can also be driven by the device at one-half of the CLKOUT1 frequency when
MCM = 1. If the serial port is not being used, CLKX goes into the high-impedance state when OFF
low. Value at reset is as an input.

Receive-clock input. External clock signal for clocking data from the DR (data-receive) pin into the serial-port
receive shift register (RSR). CLKR must be present during serial-port transfers. If the serial port is not being
used, CLKR can be sampled as an input by the IN0 bit of the SSPCR. This pin also functions as a frame-sync
output when the SSP is used in multichannel mode.

Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive
process, beginning the clocking of the RSR. FSR goes into the high-impedance state when OFF
This pin also functions as a frame-sync output when the SSP is used in multichannel mode.

Frame synchronization pulse for transmit input/ ouput. The falling edge of the FSX pulse initiates the
data-transmit process, beginning the clocking of the serial-port transmit shift register (XSR). Following reset,
FSX is an input. FSX can be selected by software to be an output when the TXM bit in the SSPCR is set
to 1. FSX goes into the high-impedance state when OFF

Serial-port transmit output. Serial data is transmitted from the transmit shift register (XSR) through the DX pin.
DX is in the high-impedance state when OFF

TEST SIGNALS

IEEE Standard 1149.1 (JTAG) test reset. TRST, when driven high, gives the scan system control of the
operations of the device. If TRST
are ignored.

If the TRST

JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the
test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller , instruction register , or
selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.

JTAG test-data output. The contents of the selected register (instruction or data) are shifted out of TDO on the
falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress.

Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as an input/output
through the JTAG scan.

Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1 /OFF is used as an
interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. When TRST
is driven low, this pin is configured as OFF. EMU1/ OFF, when active low, puts all output drivers in the
high-impedance state. Note that OFF
multiprocessing applications). Therefore, for the OFF
TRST
EMU0 = 1
EMU1/OFF

pin is not driven, an external pulldown resistor must be used.

= 0

= 0

is driven low, the device operates in its functional mode, and the test signals

is used exclusively for testing and emulation purposes (not for

signal is active.

is active low.

is active low.

condition, the following apply:

is active

is active low.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

5

TMS320F206

TYPE

†

DESCRIPTION

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

TMS320F206 Terminal Functions (Continued)

TERMINAL

NAME NO.

SUPPLY PINS

V

CCP

V

DD

V

SS

†

I = input, O = output, Z = high impedance, PWR = power, GND = ground

4

16

7
11
35
50
63
75
91

14
21
25
30
37
42
48
54
59
65
70
83
88
94

PWR V

PWR Power

GND Ground

CCP

must be connected directly to V

DD.

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram of the ’F206 internal hardware

DIV1
DIV2

IS
DS
PS

Control

MUXMUX

ARP(3)

ARB(3)

3

3

MUX

Data/Prog

SARAM

(4K × 16)

MUX

16

X1
CLKOUT1
CLKIN/X2

16

RD
WE
NMI

16

16

16

3

PC

FLASH EEPROM

16

16

ARAU(16)

MUX

Data/Prog

DARAM

B0 (256 × 16)

MUX

16

(32K × 16)

16

16

AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)

TOUT

I/O[0–3]

CLKX

CLKR

FSX

FSR

TX

RX

DX

DR

A15–A0

D15–D0

Timer

TCR

PRD

TIM

ASP

ADTR

IOSR

BRD

4

SSP

SSPCR

SDTR

Reserved

I/O-Mapped Registers

STRB

READY

HOLD

HOLDA

MP/MC

INT[1–3]

16

R/W

BR
XF

†
†

RS

Data Bus

3

16

16

Memory Map

Register
IMR (16)

IFR (16)

GREG (16)

3

MUX

NPAR

PAR MSTACK

DP(9)

16

MUX

MUX

Data

DARAM

B2 (32 × 16)

B1 (256 × 16)

16

TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

Program Bus

Data Bus

MUX

Stack 8 × 16

Program Control

(PCTRL)

16

16

Data Bus

16

MUX

16

16

TREG0(16)

Multiplier

PREG(32)

PSCALE (–6, 0, 1, 4)

MUX

CALU(32)

32

ACCL(16)ACCH(16)C

32

OSCALE (0–7)

16

MUX

32

3232

32

9

7
LSB
from
IR

9

16

ISCALE (0–16)

32

16

16

Program Bus

1616

16

Program Bus

NOTES: A. Symbol descriptions appear in Table 3.

B. For clarity the data and program buses are shown as single buses although they include address and data bits.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

7

TMS320F206
DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

Table 2. Legend for the ’F206 Internal Hardware Functional Block Diagram

SYMBOL NAME DESCRIPTION

ACC Accumulator

ARAU

AUX
REGS

BR

C Carry

CALU

CNF

GREG

IMR

IFR

INTM Interrupt-Mode Bit
INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available.
ISCALE

MPY Multiplier

MSTACK Micro Stack
MUX Multiplexer Multiplexes buses to a common input
NPAR

OSCALE

PAR

PC Program Counter

PCTRL

Auxiliary Register
Arithmetic Unit

Auxiliary Registers
0–7

Bus Request
Signal

Central Arithmetic
Logic Unit

On-Chip RAM
Configuration
Control Bit

Global Memory
Allocation
Register

Interrupt Mask
Register

Interrupt Flag
Register

Input Data-Scaling
Shifter

Next Program
Address Register

Output
Data-Scaling
Shifter

Program Address
Register

Program
Controller

32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities

An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs

These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.

BR is asserted during access of the external global data memory space. READY is asserted to the device
when the global data memory is available for the bus transaction. BR
address space by up to 32K words.

Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.

32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.

If set to 0, the reconfigurable data dual-access RAM (DARAM) block B0 is mapped to data space; otherwise,
B0 is mapped to program space.

GREG specifies the size of the global data memory space.

IMR individually masks or enables the seven interrupts.
The 7-bit IFR indicates that the TMS320F206 has latched an interrupt from one of the seven maskable

interrupts.
When INTM is set to 0, all unmasked interrupts are enabled. When INTM is set to 1, all maskable interrupts

are disabled.

16 to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.

16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.

MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.

NPAR holds the program address to be driven out on the PAB on the next cycle.
16 to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization

management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the Data-Write Data
Bus (DWEB).

PAR holds the address currently being driven on P AB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.

PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.

PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.

can be used to extend the data memory

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 2. Legend for the ’F206 Internal Hardware Functional Block Diagram (Continued)

SYMBOL NAME DESCRIPTION

Product

PM

PREG Product Register 32-bit register holds results of 16 × 16 multiply.

PSCALE

TREG

SSPCR

SDTR

TCR

PRD

TIM

UART

ASPCR

ADTR

IOSR
BRD Baud-Rate Divisor Used to set the baud rate of the UART

ST0
ST1

IMR

IFR

STACK Stack

Shift-Mode
Register Bits

Product-Scaling
Shifter

T emporary
Register

Synchronous
Serial-Port Control
Register

Synchronous
Serial-Port
Transmit and
Receive Register

Timer-Control
Register

Timer-Period
Register

Timer-Counter
Register

Universal
Asynchronous
Receive/Transmit

Asynchronous
Serial-Port Control
Register

Asynchronous
Data Register

I/O Status
Register

Status Register
Interrupt Mask

Registers
Interrupt Flag

Register

These two bits identify which of the four product-shift modes (–6, 0, 1, 4) are used by PSCALE. PM resides
in ST1. See Table 6.

0-, 1- or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the Data-Write Data Bus (DWEB), and requires no cycle
overhead.

16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.

SSPCR is the control register for selecting the serial port’s mode of operation.

SDTR is the data-transmit and data-receive register.

TCR contains the control bits that define the divide-down ratio, start/stop the timer, and reload the period.
Also contained in TCR is the current count in the prescaler. Reset initializes the timer-divide-down ratio
to 0 and starts the timer.

PRD contains the 16-bit period that is loaded into the timer counter when the counter borrows or when the
reload bit is activated. Reset initializes the PRD to 0xFFFF.

TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF.

UART is the asynchronous serial port.

ASPCR controls the asynchronous serial-port operation.

Asynchronous data-transmit and data-receive register

IOSR detects current levels (and changes with inputs) on pins IO0–IO3 and the status of UART.

ST0 and ST1 contain the status of various conditions and modes. These registers can be stored in and
loaded from data memory , thereby allowing the status of the machine to be saved and restored.

IMR individually masks or enables the seven interrupts.

IFR indicates that the CPU has latched an interrupt pulse from one of the maskable interrupts.
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service

routines, or for storing data. The ’C20x stack is 16-bit wide and eight-level deep.

TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

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9

TMS320F206
DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

architectural overview

The ’F206 advanced Harvard-type architecture maximizes the processing power by maintaining two separate
memory bus structures — program and data — for full-speed execution. The multiple buses allow data and
instructions to be read simultaneously. Instructions support data transfers between the two spaces. This
architecture permits coefficients stored in program memory to be read in RAM, eliminating the need for a
separate coefficient ROM. This, coupled with a four-deep pipeline, allows the TMS320F206 to execute most
instructions in a single cycle.

status and control registers

Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thereby allowing the status of the machine to be
saved and restored for subroutines.

The load-status-register (LST) instruction is used to write to ST0 and ST1. The store-status-register (SST)
instruction is used to read from ST0 and ST1 (except the INTM bit, which is not affected by the LST instruction).
The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. T able 3
and Table 4 show the organization of status registers ST0 and ST1, indicating all status and control bits
contained in each. Several bits in the status registers are reserved and read as logic 1s. Refer to Table 5 for
status-register field definitions.

Table 3. Status and Control Register Zero

15 131211109876543210

ST0

ARP

OV OVM 1 INTM DP

Table 4. Status and Control Register One

15 131211109876543210

ST1

ARB

CNF TC SXM C 1 1 1 1 XF 1 1 PM

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

status and control registers (continued)

Table 5. Status Register Field Definitions

FIELD FUNCTION

ARB

ARP

C

CNF

DP

INTM

OV

OVM

PM

SXM

TC

XF

Auxiliary register pointer buffer . Whenever the ARP is loaded, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by an LST #1 instruction, the same value is also copied to the ARP.

Auxiliary register pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by
the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is
executed.

Carry Bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow .
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In
these cases, the ADD can only set and the SUB only reset the carry bit, but cannot affect it otherwise. The single-bit shift and
rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided
to branch on the status of C. C is set to 1 on a reset.

On-chip RAM configuration-control bit. If CNF is set to 0, the reconfigurable data DARAM blocks are mapped to data space;
otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF , CLRC CNF, and LST #1 instruc­tions. RS

Data memory page pointer . The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct
memory address of 16 bits. DP can be modified by the LST and LDP instructions.

Interrupt-mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are
disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS
the unmaskable RS
also set to 1 when a maskable interrupt trap is taken.

Overflow-flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the ALU. Once an overflow occurs, the
OV remains set until a reset, BCND/D on OV/NOV, or LST instructions clear OV.

Overflow-mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the
accumulator is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC
instructions set and reset this bit, respectively. LST can also be used to modify the OVM.

Product-shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the
PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, PREG output is left-shifted
by four bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of six bits, sign-extended. Note
that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM
is loaded by the SPM and LST #1 instructions. PM is cleared by RS

Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling
shifter. SXM = 0 suppresses sign extension. SXM does not af fect the definitions of certain instructions; for example, the ADDS
instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM and reset by the CLRC SXM
instructions, and can be loaded by the LST #1. SXM is set to 1 by reset.

T est/control flag bit. TC is affected by the BIT, BITT , CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by
BIT or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function
of the two MSBs of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute, based on the condition of TC.

XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF and reset by
the CLRC XF instructions. XF is set to 1 by reset.

sets the CNF to 0.

and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is

TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

also sets INTM. INTM has no effect on

.

central processing unit

The TMS320F206 central processing unit (CPU) contains a 16-bit scaling shifter, a 16x16-bit parallel multiplier ,
a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both
the accumulator and the multiplier. This section describes the CPU components and their functions. The
functional block diagram shows the components of the CPU.

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TMS320F206
DIGITAL SIGNAL PROCESSOR

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input scaling shifter

The TMS320F206 provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output
connected to the CALU. This shifter operates as part of the path of data coming from program or data space
to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit
CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.

The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to adapt to the
performance of the system.

multiplier

The TMS320F206 uses a 16x16-bit hardware multiplier that is capable of computing a signed or an unsigned
32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned)
instruction, perform a signed-multiply operation. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated
with the multiplier:

D

16-bit temporary register (TREG) that holds one of the operands for the multiplier, and

D

32-bit product register (PREG) that holds the product.

Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6.

Table 6. PSCALE Product Shift Modes

PM SHIFT DESCRIPTION

00 no shift Product fed to CALU or data bus with no shift
01 left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
10 left 4 Removes the extra four sign bits generated in a 16x13 2s-complement multiply to a produce a Q31

11 right 6 Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow

product when using the multiply by a 13-bit constant

The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY). A four-bit shift is used in conjunction with the MPY instruction with a short
immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by
a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.

The L T (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication can also be
performed with a 13-bit immediate operand when using the MPY instruction. A product is then obtained every
two cycles. For efficient implementation of multiple products, or multiple sums of products, the CPU provides
pipelining of the TREG load operation with certain CALU operations which use the PREG. These operations
include: load ACC with PREG (L TP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data
to next address in data memory (LTD); and subtract PREG from ACC (LTS).

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TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

multiplier (continued)

Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN), while the data addresses are generated
by data address generation (DAGEN). This allows the repeated instruction to access the values sequentially
from the coefficient table and step through the data in any of the indirect addressing modes.

The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
discard the oldest sample.

The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This allows the operands of greater than 16 bits to be
broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.

After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory through the SPH (store
product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data
memory passes through the PSCALE shifter and is therefore, affected by the product-shift mode value defined
by the PM bits in the ST1 register. This is important when saving PREG in an interrupt-service routine context
save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by
executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG
and executing a MPY #1 instruction. The high half is then loaded using the LPH instruction.

central arithmetic logic unit

The TMS320F206 CALU implements a wide range of arithmetic and logical functions, the majority of which
execute in a single clock cycle. This ALU is referred to as “central” to differentiate it from a second ALU used
for indirect address generation (called the ARAU). Once an operation is performed in the CALU, the result is
transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input
to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled
by PSCALE when coming from the multiplier.

The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or
derived from immediate instructions. In addition to arithmetic operations, the CALU can perform Boolean
operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the CALU
is always provided from the accumulator, and the other input can be provided from the product register (PREG)
of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After
the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.

The TMS320F206 supports floating-point operations for applications requiring a large dynamic range. The
NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by
performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the
LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These
instructions are useful in floating-point arithmetic where denormalization of a number is required; that is,
floating-point to fixed-point conversion. They are also useful in the implementation of automatic-gain control
(AGC) at the input of a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data
memory based on the value contained in the four LSBs of TREG.

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13

TMS320F206
DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

central arithmetic logic unit (continued)

The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. Setting
the OVM status register bit selects the overflow saturation mode. When the CALU is in the overflow saturation
mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive
or the most negative value representable in the accumulator, depending upon the direction of the overflow . The
value of the accumulator upon saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM
(overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the
accumulator without modification. (Note that logical operations cannot result in overflow.)

The CALU can execute a variety of branch instructions that depend on the status of the CALU and accumulator .
These instructions can be executed conditionally , based on various combinations of the associated status bits.
For overflow management, these conditions include the OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch-to-address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.

The CALU also has a carry bit (bit 9 of status register ST1) that facilitates efficient computation of
extended-precision products and additions or subtractions. The carry bit is also useful in overflow management.
The carry bit is affected by the following operations:

D

Additions to and subtractions from the accumulator:
C = 0: When the result of a subtraction generates a borrow.

When the result of an addition does not generate a carry . (Exception: When the ADD instruction is
used with a shift of 16 and no carry is generated, the ADD instruction has no effect on C.)

C = 1: When the result of an addition generates a carry.

When the result of a subtraction does not generate a borrow. (Exception: When the SUB instruction
is used with a shift of 16 and no borrow is generated, the SUB instruction has no effect on C.)

D

Single-bit shifts and rotations of the accumulator value. During a left shift or rotation, the most significant

bit of the accumulator is passed to C; during a right shift or rotation, the least significant bit is passed to C.
Note: the carry bit is set to “1” on a hardware reset.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions

provided, use the previous value of carry in their addition/subtraction operation.

accumulator

The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16–31), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0–15). When the post-scaling
shifter is used on the low word, the LSBs are zero-filled.

The SFL and SFR (in-place one-bit shift to the left / right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the accumulator contents through the carry bit. The SXM
bit affects the definition of the SFR (shift accumulator right) instruction. When SXM=1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM=0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions can be used with the shift and rotate instructions for multiple-bit shifts.

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TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

auxiliary registers and auxiliary-register arithmetic unit (ARAU)

The ’F206 provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. For indirect data memory
addressing, the address of the desired memory location is placed into the selected auxiliary register. These
registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7,
designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data
memory , the ACC, the product register , or by an immediate operand defined in the instruction. The contents of
these registers can also be stored in data memory or used as inputs to the CALU.

The auxiliary register file (AR0–AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU
can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either
by ±1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does
not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel.

memory

The ’F206 implements three separate address spaces for program memory , data memory, and I/O. Each space
accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the
top of the address range can be defined to be external global memory in increments of powers of two, as
specified by the contents of the global memory allocation register (GREG). Access to global memory is
arbitrated using the global memory bus request (BR

) signal.

On the ’F206, the first 96 (0– 5Fh) data memory locations are allocated for memory-mapped registers or
reserved. This memory-mapped register space contains various control and status registers including those for
the CPU.

The TMS320F206 device includes 544 x 16 words of dual-access RAM (DARAM), 4K x 16 single-access RAM
(SARAM), and 32K x 16 program flash memory. Table 7 shows the mapping of these memory blocks and the
appropriate control bits and pins. Figure 1 shows the effects of the memory control pin MP/MC and the control
bit CNF on the mapping of the respective memory spaces to on-chip or off-chip. The PON and DON bits select
the SARAM (4K) mapping in program, data, or both. See T able 8 for details of the PMST register, and PON and
DON bits. At reset, these bits are 11, which selects the SARAM in program and data space. The SARAM
addresses are 0x800h in data and 0x8000h in program memory.

At reset, if the MP/MC
to 0x0000h (external program space). The MP/MC pin status is latched in the PMST register (bit 0). As long as
this bit remains high, the device is in microprocessor mode. PMST register bits can be read and modified in
software. If bit 0 is cleared to 0, the device enters microcontroller mode and transfers control to the on-chip flash
memory at 0x0000.

The on-chip data memory blocks B0 and B1 are 256  16 words each, and these blocks are mapped to dual
address ranges within the ’F206 memory map. For example, when CNF = 0, B0 is mapped in data space at
addresses 0100–01FFh, and also at addresses 0200–02FFh. Corresponding addresses of the two ranges
(0100h and 0200h, 0101h and 0201h, ...) access the same memory locations within B0. Similarly, when
CNF = 1, B0 is mapped in program space at addresses 0FE00–0FEFFh, and also at addresses
0FF00–0FFFFh. The B1 block is always mapped in data space at addresses 0300–03FFh, and also at
0400–04FFh.

pin is held high, the device is in microprocessor mode and the program address branches

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15

TMS320F206
DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

Hex

0000

003F
0040

3FFF

4000

7FFF

8000

8FFF

9000

FDFF

FE00

FEFF

FF00

Program

Interrupt

Vectors

On-Chip 16K

Flash (0)

(MP/MC = 0)

External

= 1)

(MP/MC

On-Chip 16K

Flash (1)

(MP/MC

= 0)

External

(MP/MC

= 1)

On-Chip SARAM

4K

Internal

(PON = 1)

External

(PON = 0)

External

On-Chip

DARAM B0

(CNF = 1)

Also Mapped at

(0FF00–0FFFFh)

External

(CNF = 0)

On-Chip

DARAM B0

(CNF = 1)

Also Mapped at

(0FE00–0FEFFh)

†

Hex

0000

005F
0060

007F

0080

00FF

0100

01FF

0200

02FF

0300

03FF

0400

04FF

0500

07FF

0800

17FF

1800

Data

Memory-Mapped

Registers and

Reserved

On-Chip

DARAM B2

Reserved

On-Chip

DARAM B0

(CNF = 0)

Also Mapped at

(0200–02FFh)

Reserved
(CNF = 1)

On-Chip

DARAM B0

(CNF = 0)

Also Mapped at

(0100–01FFh)

Reserved
(CNF = 1)

On-Chip

DARAM B1

Also Mapped at

(0400–04FFh)

On-Chip

DARAM B1

Also Mapped at

(0300–03FFh)

Reserved

On-Chip SARAM

(DON = 1)

External

(DON = 0)

†

†

4K

Hex

0000

FEFF

FF00

FF0F
FF10

I/O Space

External

I/O Space

Reserved

for

Test

On-Chip I/O

Peripheral

Registers

External

FFFF

†

DARAM blocks B0 and B1 are 256  16 words each; however, these memory blocks are mapped to dual address ranges within the ’F206
memory map. For more details, see the last paragraph in the memory section.

(CNF = 0)

FFFF

External

FFFF

Figure 1. TMS320F206 Memory Map

16

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memory (continued)

TMS320F206

DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

Table 7. TMS320F206 Memory Map

DESCRIPTION OF MEMORY BLOCK

256 x 16 word dual-access RAM (DARAM)
(B0)

256 x 16 word DARAM (B0)

256 x 16 word DARAM (B1)
32 x 16 word DARAM (B2) 0x60 – 0x7Fh x x x x

32K x 16 word program flash memory
32K x 16 word external program memory 0x0000 – 0x7FFFh 1 x x x
32K x 16 word external program memory 0x8000h – 0xFFFFh x x 0 0
External 0x8000h – 0xFDFFh x x 0 1
4K x 16 word data single-access RAM

(SARAM)
4K x 16 word program SARAM 0x8000 – 0x8FFFh x x 1 x
4K x 16 word program and data SARAM
4K x 16 word SARAM not available not available x 0 0 x

†

Denotes don’t care condition

‡

The DARAM blocks B0 and B1 are mapped to dual address ranges as shown in the table. For more details on this mapping, see the last paragraph
in the memory section.

§

The 32K x 16 flash memory consists of two 16K x 16 flash modules designated by FLASH0 and FLASH1.

¶

The single SARAM (4K) block is accessible from both data and program memory space.

§

¶

DATA MEMORY

ADDRESS

0x100 – 0x1FFh

0x200 – 0x2FFh

0x300 – 0x3FFh

0x400 – 0x4FFh

0x800 – 0x17FFh x 1 x x

0x800 – 0x17FFh 0x8000 – 0x8FFFh x 1 1 x

PROG MEMORY

ADDRESS

‡

0xFE00 – 0xFEFFh

0xFF00 – 0xFFFFh

‡

0x0000 – 0x7FFFh 0 x x x

‡

†

MP/MC

x x x 0

x x x 1

x x x x

DON

†

PON

CNF

†

BIT

†

flash memory (EEPROM)

Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, flash is a nonvolatile
memory type; however, it has the advantage of “in-target” reprogrammability. The TMS320F206 incorporates
two 16K  16-bit flash EEPROM modules which provide a contiguous 32K  16-bit array in program space.
This type of memory expands the capabilities of the TMS320F206 in the areas of prototyping, early field-testing,
and single-chip applications.

Unlike most discrete flash memory, the ’F206 flash does not require a dedicated state machine, because the
algorithms for programming and erasing the flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and flash code. Other key features of the flash include zero-wait-state access rate and single 5-V
power supply.

An erased bit in the TMS320F206 flash is read as a logic 1, and a programmed bit is read as a logic 0. The flash
requires a block-erase of each of the two 16K modules; however, any combination of bits can be programmed.
The following four algorithms are required for flash operations: clear, erase, flash-write, and program. For an
explanation of these algorithms and a complete description of the flash EEPROM, refer to the

TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference

available during the 2nd quarter of 1998.

(literature number SPRU282)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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TMS320F206
DIGITAL SIGNAL PROCESSOR

SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998

flash serial loader

The on-chip flash is shipped with a serial bootloader programmed at the following addresses: 0x0000–0x00FFh.
All other flash addresses are in an erased state. The serial bootloader can be used to load flash-programming
algorithms or code to any destination RAM (SARAM or B0 RAM) through the on-chip UART or enhanced
synchronous serial port (ESSP). Refer to the serial loader documentation to understand on-chip flash
programming using the serial bootloader.

on-chip registers

The TMS320F206 includes three registers mapped to internal data space and eighteen (18) registers mapped
to internal I/O space. T able 8 describes these registers and shows their respective addresses. In the table, DS
refers to data space and IS refers to input/output ports.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443