Texas Instruments TLV5625CD, TLV5625IDR, TLV5625ID, TLV5625CDR Datasheet

TLV5625

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN

SLAS233A – JULY 1999 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D

Dual 8-Bit Voltage Output DAC

D

Programmable Internal Reference

D

Programmable Settling Time
– 2.5 µs in Fast Mode
– 12 µs in Slow Mode

D

Compatible With TMS320 and SPI Serial
Ports

D

Differential Nonlinearity <0.2 LSB Max

D

Monotonic Over Temperature

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5625 is a dual 8-bit voltage output DAC
with a flexible 3-wire serial interface. The serial
interface is compatible with TMS320, SPI,
QSPI, and Microwire serial ports. It is
programmed with a 16-bit serial string containing
4 control and 8 data bits.

The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a
Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC
allows the designer to optimize speed versus power dissipation.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC

(D)

0°C to 70°C TLV5625CD

–40°C to 85°C TLV5625ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW

Copyright  2000, Texas Instruments Incorporated

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

OUTA

V

DD

OUTB
REF
AGND

D PACKAGE

(TOP VIEW)

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

TLV5625

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN

SLAS233A – JULY 1999 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Serial

Interface

and

Control

8-Bit

DAC B

Latch

SCLK

DIN

CS

OUTA

Power-On

Reset

x2

8

Power and

Speed Control

2

8-Bit

DAC A

Latch

8

REF AGND V

DD

8 8

OUTB

x2

Buffer

8

Terminal Functions

TERMINAL

NAME NO.

I/O/P

DESCRIPTION

AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs.
DIN 1 I Digital serial data input
OUTA 4 O DAC A analog voltage output
OUTB 7 O DAC B analog voltage output
REF 6 I Analog reference voltage input
SCLK 2 I Digital serial clock input
V

DD

8 P Positive power supply

PRODUCT PREVIEW

TLV5625

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN

SLAS233A – JULY 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5625C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5625I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5

V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3
Power on reset, POR 0.55 2 V
High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V
Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V
Reference voltage, V

ref

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 kΩ

Load capacitance, C

L

100 pF

Clock frequency, f

CLK

20 MHz

p

p

TLV5625C 0 70

°

Operating free-air temperature, T

A

TLV5625I –40 85

°C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function.

PRODUCT PREVIEW

TLV5625

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN

SLAS233A – JULY 1999 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

pp

No load, All inputs = AGND or VDD,

Fast 1.8 2.3

I

Power su ly current

DD

mA

DD

y

DAC latch

= 0x

800

Slow

0.8

1

Power-down supply current 1 3 µA

pp

Zero scale, See Note 2 –65

PSRR

Power supply rejection ratio

Full scale, See Note 3 –65

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits
INL Integral nonlinearity See Note 4 ±0.3 ±0.5 LSB
DNL Differential nonlinearity See Note 5 ±0.07 ±0.2 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±12 mV
EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

E

G

Gain error See Note 8 ±0.5

% full

scale V

EG TCGain-error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.

5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal
1-LSB amplitude change of any two adjacent codes.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale error temperature coef ficient is given by: EZS TC = [EZS (T

max) – EZS

(T

min

)]/2V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ.

9. Gain temperature coefficient is given by: EG TC = [EG (T

max) – Eg

(T

min

)]/2V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage range RL = 10 kΩ 0 VDD–0.4 V
Output load regulation accuracy VO = 4.096 V , 2.048 V RL = 2 kΩ ±0.29 % FS

reference input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage range 0 V

DD–1.5

V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

p

Fast 1.3 MHz

Reference input bandwidth

REF

= 0.2

V

pp

+ 1.

024 V dc

Slow 525 kHz

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

PRODUCT PREVIEW

TLV5625

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN

SLAS233A – JULY 1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,C

= 100 pF,

Fast 2.5

t

s(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow 12

µ

s

p

R

= 10 kΩ,C

= 100 pF,

Fast 1

t

s(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow 2

µ

s

R

= 10 kΩ,C

= 100 pF,

Fast 3

SR

Slew rate

L

,

L

,

See Note 13

Slow 0.5

V/µs

Glitch energy

DIN = 0 to 1, FCLK = 100 kHz,
CS

= V

DD

5 nV–s

SNR Signal-to-noise ratio 52 54
SINAD Signal-to-noise + distortion

f

= 102 kSPS, f

= 1 kHz,

48 49

THD Total harmonic distortion

s

,

out

,

RL = 10 kΩ,CL = 100 pF

–50 –48

dB

SFDR Spurious free dynamic range 48 50

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.

PRODUCT PREVIEW