Texas Instruments TLV5624IDR, TLV5624IDGKR, TLV5624IDGK, TLV5624CDR, TLV5624ID Datasheet

TLV5624

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG

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features

D

8-Bit Voltage Output DAC

D

Programmable Internal Reference

D

Programmable Settling Time:

1 µs in Fast Mode,

3.5 µs in Slow Mode

D

Compatible With TMS320 and SPI Serial
Ports

D

Differential Nonlinearity...<0.2 LSB Typ

D

Monotonic Over Temperature

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5624 is a 8-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows
glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit
serial string containing 4 control and 8 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling
time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable
precision voltage reference, the TLV5624 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented
with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in
an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial
temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC

(D)

MSOP
(DGK)

0°C to 70°C TLV5624CD TLV5624CDGK

–40°C to 85°C TLV5624ID TLV5624IDGK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

FS

V

DD

OUT
REF
AGND

D OR DGK PACKAGE

(TOP VIEW)

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

TLV5624

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
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functional block diagram

Serial

Interface

and

Control

8-Bit
DAC

Latch

CS

DIN

OUT

Power-On

Reset

x2

8

2-Bit

Control

Latch

2

Power

and Speed

Control

2

Voltage

Bandgap

PGA With

Output Enable

8

REF

FS

SCLK

Terminal Functions

TERMINAL

NAME NO.

I/O/P

DESCRIPTION

AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs
DIN 1 I Digital serial data input
FS 4 I Frame sync input
OUT 7 O DAC A analog voltage output
REF 6 I/O Analog reference voltage input/output
SCLK 2 I Digital serial clock input
V

DD

8 P Positive power supply

TLV5624

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (V

DD

to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLV5624C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5624I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5 V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3 V
Power on reset, POR 0.55 2 V
High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V
Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V
Reference voltage, V

ref

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 kΩ

Load capacitance, C

L

100 pF

Clock frequency, f

CLK

20 MHz

p

p

TLV5624C 0 70

°

Operating free-air temperature, T

A

TLV5624I –40 85

°C

NOTE 1: Due to the x2 output buffer , a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function. The output buffer of the

internal reference must be disabled, if an external reference is used.

TLV5624

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
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electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

pp

No load,

p

Fast 2.3 3.3

IDDPower su ly current

All in uts = AGND or V

DD

,

DAC latch = 0x800

Slow 1.5 1.9

mA

Power down supply current See Figure 8 0.01 10 µA

pp

Zero scale, See Note 2 –65

PSRR

Power supply rejection ratio

Full scale, See Note 3 –65

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits
INL Integral nonlinearity, end point adjusted See Note 4 ±0.3 ±0.5 LSB
DNL Differential nonlinearity See Note 5 ±0.07 ±0.2 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±10 mV
EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

E

G

Gain error See Note 8 ±0.6

% full

scale V

EG TCGain error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the dif ference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage RL = 10 kΩ 0 VDD–0.4 V
Output load regulation accuracy VO = 4.096 V , 2.048 V RL = 2 kΩ ±0.10 ±0.25

% full

scale V

reference pin configured as output (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ref(OUTL)

Low reference voltage 1.003 1.024 1.045 V

V

ref(OUTH)

High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V

I

ref(source)

Output source current 1 mA

I

ref(sink)

Output sink current –1 mA
Load capacitance 100 pF

PSRR Power supply rejection ratio –65 dB

TLV5624

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG

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electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)

reference pin configured as input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage 0 V

DD–1.5

V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

p

Fast 1.3 MHz

Reference input bandwidth

REF

= 0.2

V

pp

+ 1.

024 V dc

Slow 525 kHz

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,C

= 100 pF,

Fast 1 3

t

s(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow 3.5 7

µ

s

p

R

= 10 kΩ,C

= 100 pF,

Fast 0.5 1.5

t

s(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow 1 2

µ

s

R

= 10 kΩ,C

= 100 pF,

Fast 8

SR

Slew rate

L

,

L

,

See Note 13

Slow 1.5

V/µs

Glitch energy

DIN = 0 to 1, f

CLK

= 100 kHz,

CS

= V

DD

5 nV–S

SNR Signal-to-noise ratio 53 57
S/(N+D) Signal-to-noise + distortion

f

= 480 kSPS, f

= 1 kHz,

48 47

THD Total harmonic distortion

s

,

out

,

RL = 10 kΩ,C

L

= 100 pF

–50 –48

dB

Spurious free dynamic range 50 62

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

TLV5624

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
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digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–FS)

Setup time, CS low before FS falling edge 10 ns

t

su(FS-CK)

Setup time, FS low before first negative SCLK edge 8 ns

t

su(C16-FS)

Setup time, 16th negative SCLK edge after FS low on which bit D0 is sampled before rising
edge of FS

10 ns

t

su(C16-CS)

Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of 16th positive edge to update DAC, then setup time between
FS rising edge and CS

rising edge.

10 ns

t

wH

SCLK pulse duration high 25 ns

t

wL

SCLK pulse duration low 25 ns

t

su(D)

Setup time, data ready before SCLK falling edge 8 ns

t

H(D)

Hold time, data held valid after SCLK falling edge 5 ns

t

wH(FS)

FS pulse duration high 25 ns

PARAMETER MEASUREMENT INFORMATION

t

wL

SCLK

CS

DIN

FS

D15 D14 D13 D12 D1 D0 XX

1

X

2 3 4 5 15 16

X

t

wH

t

su(D)th(D)

t

su(CS-FS)

t

wH(FS)

t

su(FS-CK)

t

su(C16-FS)

t

su(C16-CS)

Figure 1. Timing Diagram