Texas Instruments TLV5623IDR, TLV5623IDGKR, TLV5623ID, TLV5623IDGK, TLV5623CDR Datasheet

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

8-Bit Voltage Output DAC

D

Programmable Settling Time vs Power
Consumption

3 µs in Fast Mode
9 µs in Slow Mode

D

Ultra Low Power Consumption:

900 µW Typ in Slow Mode at 3 V

2.1 mW Typ in Fast Mode at 3 V

D

Differential Nonlinearity...<0.2 LSB Typ

D

Compatible With TMS320 and SPI Serial
Ports

D

Power-Down Mode

D

Buffered High-Impedance Reference Input

D

Monotonic Over Temperature

D

Available in MSOP Package

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5623 is a 8-bit voltage output digital-to­analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows
glueless interface to TMS320, SPI, QSPI, and
Microwire serial ports. The TLV5623 is pro­grammed with a 16-bit serial string containing 4
control and 12 data bits. Developed for a wide
range of supply voltages, the TLV5623 can
operate from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.

Implemented with a CMOS process, the TL V5623 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TL V5623C is characterized for operation from 0°C
to 70°C. The TLV5623I is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

†

(D)

MSOP
(DGK)

0°C to 70°C TLV5623CD TLV5623CDGK

–40°C to 85°C TLV5623ID TLV5623IDGK

†

Available in tape and reel as the TL V5623CDR and the TLV5623IDR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

FS

V

DD

OUT
REFIN
AGND

D OR DGK PACKAGE

(TOP VIEW)

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Serial Input

Register

16 Cycle

Timer

REFIN

CS

SCLK

FS

OUT

_
+

Power-On

Reset

DIN

8-Bit
Data

Latch

Speed/Power-Down

Logic

2

8

Update

6

1

2
3
4

7

x2

10

8

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 5 Analog ground
CS 3 I Chip select. Digital input used to enable and disable inputs, active low.
DIN 1 I Serial digital data input
FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
OUT 7 O DAC analog output
REFIN 6 I Reference analog input voltage
SCLK 2 I Serial digital clock input
V

DD

8 Positive power supply

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (V

DD

to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLV5623C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5623I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5 V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3 V

High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V

Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V

Reference voltage, V

ref

to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 10 kΩ

Load capacitance, C

L

100 pF

Clock frequency, f

CLK

20 MHz

p

p

TLV5623C 0 70 °C

Operating free-air temperature, T

A

TLV5623I –40 85 °C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ V

DD/2

causes clipping of the transfer function.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

VDD = 5 V, VREF = 2.048 V,
No load,

Fast 0.9 1.35 mA

pp

All inputs = AGND or VDD,
DAC latch = 0x800

Slow 0.4 0.6 mA

IDDPower supply current

VDD = 3 V, VREF = 1.024 V
No load,

Fast 0.7 1.1 mA

All inputs = AGND or VDD,
DAC latch = 0x800

Slow 0.3 0.45 mA

Power down supply current (see Figure 12) 1 µA

pp

Zero scale See Note 2 –68

PSRR

Power supply rejection ratio

Full scale See Note 3 –68

dB

Power on threshold voltage, POR 2 V

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

static DAC specifications RL = 10 kΩ, CL = 100 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits
INL Integral nonlinearity See Note 4 ± 0.3 ±0.5 LSB
DNL Dif ferential nonlinearity See Note 5 ± 0.07 ± 0.2 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±10 mV
EZS

TC

Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

E

G

Gain error See Note 8 ±0.6

% of

FS

voltage

Gain-error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coef ficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Voltage output range RL = 10 kΩ 0 VDD–0.1 V
Output load regulation accuracy RL = 2 kΩ, vs 10 kΩ ±0.1 ±0.25

% of FS

voltage

reference input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

I

Input voltage range 0 VDD–1.5 V

R

I

Input resistance 10 MΩ

C

I

Input capacitance 5 pF

p

Slow 525 kHz

Reference input bandwidth

REFIN

= 0.2

V

pp

+

1.024 V dc

Fast 1.3 MHz

Reference feed through

REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 10)

–75 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

±1 µA

I

IL

Low-level digital input current VI = 0 V ±1 µA

C

I

Input capacitance 3 pF

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,

CL = 100 pF,

Fast 3 5.5

t

s(FS)

Output settling time, full scale

L

,

See Note 11

Slow 9 20

µ

s

p

R

= 10 kΩ,

CL = 100 pF,

Fast 1 µs

t

s(CC)

Output settling time, code to code

L

,

See Note 12

Slow 2 µs

R

= 10 kΩ, C

= 100 pF,

Fast 3.6

SR

Slew rate

L

,

See Note 13

L

,

Slow 0.9

V/µs

Glitch energy Code transition from 0x7F0 to 0x800 10 nV–s
S/N Signal to noise 57 dB
S/(N+D) Signal to noise + distortion

fs = 400 KSPS fout = 1.1 kHz,

p

49 dB

THD Total harmonic distortion

R

L

=

10 kΩ,C

L

=

100 pF

,

BW = 2

0

kHz

–50 dB

Spurious free dynamic range

BW = 20 kHz

60 dB

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, ensured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–FS)

Setup time, CS low before FS↓ 10 ns

t

su(FS–CK)

Setup time, FS low before first negative SCLK edge 8 ns

t

su(C16–FS)

Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS

10 ns

t

su(C16–CS)

Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS

rising edge.

10 ns

t

wH

Pulse duration, SCLK high 25 ns

t

wL

Pulse duration, SCLK low 25 ns

t

su(D)

Setup time, data ready before SCLK falling edge 8 ns

t

h(D)

Hold time, data held valid after SCLK falling edge 5 ns

t

wH(FS)

Pulse duration, FS high 20 ns

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

123451516

D15 D14 D13 D12 D1 D0

t

su(FS-CK)

t

su(CS-FS)

t

wH(FS)

t

h(D)

t

su(D)

t

wH

t

wL

t

su(C16-CS)

t

su(C16-FS)

SCLK

DIN

CS

FS

Figure 1. Timing Diagram