Texas Instruments TLV5621IN, TLV5621IDR, TLV5621ID Datasheet

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

2.7-V to 5.5-V Single-Supply Operation

D

Four 8-Bit Voltage Output DACs

D

One-Half Power 8-Bit Voltage Output DAC

D

Fast Serial Interface...1 MHz Max

D

Simple Two-Wire Interface In Single
Buffered Mode

D

High-Impedance Reference Inputs For Each
DAC

D

Programmable for 1 or 2 Times Output
Range

D

Simultaneous-Update Facility In
Double-Buffered Mode

D

Internal Power-On Reset

D

Industry Temperature Range

D

Low Power Consumption

D

Half-Buffered Output

D

Power-Down Mode

applications

D

Programmable V oltage Sources

D

Digitally-Controlled Amplifiers/Attenuators

D

Cordless/Wireless Communications

D

Automatic Test Equipment

D

Portable Test Equipment

D

Process Monitoring and Control

D

Signal Synthesis

description

The TL V5621I is a quadruple 8-bit voltage output
digital-to-analog converter (DAC) with buffered
reference inputs (high impedance). The DAC
produces an output voltage that ranges between
either one or two times the reference voltages and
GND, and the DAC is monotonic. The device is
simple to use since it operates from a single
supply of 2.7 V to 5.5 V . A power-on reset function
is incorporated to provide repeatable start-up
conditions. A global hardware shut-down terminal
and the capability to shut down each individual
DAC with software are provided to minimize
power consumption.

Digital control of the TL V5621I is over a simple 3-wire serial bus that is CMOS compatible and easily interfaced
to all popular microprocessor and microcontroller devices. A TLV5621I 11-bit command word consists of
eight bits of data, two DAC select bits, and a range bit for selection between the times one or times two output
range. The TLV5621I digital inputs feature Schmitt triggers for high noise immunity. The DAC registers are
double buffered which allows a complete set of new values to be written to the device, and then under control
of the HWACT signal, all of the DAC outputs are updated simultaneously.

The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical
applications. The TLV5621I does not require external trimming. The TLV5621I is characterized for operation
from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(D)

–40°C to 85°C TLV5621ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND
REFA
REFB

REFC
REFD

DATA

CLK

1
2
3
4
5
6
7

14
13
12
11
10

9
8

V

DD

HWACT
DACA
DACB
DACC
DACD
EN

D PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Power-On

Reset

Serial

Interface

× 2

DAC

LatchLatch

Latch Latch

DAC

× 2

× 2

DAC

LatchLatch

Latch Latch

DAC

× 2

REFA

+
–

+
–

+
–

+
–

+
–

+
–

+
–

+
–

REFB

REFC

CLK

REFD

DATA

EN

DACA

DACB

DACC

DACD

8 8

8

8

8

8

8

8

HWACT

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

CLK 7 I Serial interface clock, data enters on the negative edge
DACA 12 O DAC A analog output
DACB 11 O DAC B analog output
DACC 10 O DAC C analog output
DACD 9 O DAC D analog output
DATA 6 I Serial-interface digital-data input
EN 8 I Input enable
GND 1 Ground return and reference
HWACT 13 I Global hardware activate
REFA 2 I Reference voltage input to DACA
REFB 3 I Reference voltage input to DACB
REFC 4 I Reference voltage input to DACC
REFD 5 I Reference voltage input to DACD
V

DD

14 Positive supply voltage

detailed description

The TLV5621 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in T able 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer . Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance
of the output buffer . Because the inputs are buf fered, the DACs always present a high-impedance load to the
reference source.

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times one
or times two gain.

On power-up, the DACs are reset to CODE 0.
Each output voltage is given by:

VO(DACA|B|C|D)+REF

CODE

256

(1)

RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal-Output Transfer

D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE

0 0 0 0 0 0 0 0 GND
0 0000001 (1/256) × REF (1+RNG)

• ••••••• •

•••••••• •

01111111 (127/256) × REF (1+RNG)
1 0000000 (128/256) × REF (1+RNG)

• ••••••• •

•••••••• •
11111111 (255/256) × REF (1+RNG)

data interface

The data interface has two modes of operation; single and double buffered. Both modes serially clock in bits
of data using DA T A and CLK whenever EN is high. When EN is low, CLK is disabled and data cannot be loaded
into the buffers.

In the single buffered mode, the DAC outputs are updated on the last/twelfth falling edge of CLK, so this mode
only requires a two-wire interface with EN tied high (see Figure 1 and Figure 2).

In the double buffered mode (startup default), the outputs of the DACs are updated on the falling edge of the
EN strobe (see Figure 3 and Figure 4). This allows multiple devices to share data and clock lines by having only
separate EN lines.

single-buffer mode (MODE = 1)

When a two wire interface is used, EN is tied high and the input to the device is always active; therefore, random
data can be clocked into the input latch. In order to regain word synchronization, twelve zeros are clocked in
as shown in Figure 1, and then a data or control word is clocked in. In Figure 1, the MODE bit is set to one, and
a control word is clocked in with the DAC outputs becoming active after the last falling edge of the control word.

Figure 2 shows valid data being written to a DAC, note that CLK is held low while the data is invalid. Data can
be written to all four DACs and then the control word is clocked in which sets the MODE bit to 1. At the end of
the control word, the data is latched to the inputs of the DACs.

Note that once the MODE bit has been set, it is not possible to clear it, i.e., it is not possible to move from single
to double-buffered mode.

SLAS138B – APRIL 1996 – REVISED FEBRUAR Y 1997

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

Template Release Date: 7–11–94

4

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

CLK

RS

MODE

RNGARNGBRNGCRNG

D

SIA SIB SIC SID ACT

DATA

DAC

EN

(Tied High)

NOTE A: Twelve zeros enable word synchronization and the output can change after the leading edge of CLK depending on the data in the latches.

Figure 1. Register Write Operation Following Noise or Undefined Levels on DATA or CLK (Single-Buffer Mode)

CLK

RS

MODE

RNGARNGBRNGCRNG

D

SIA SIB SIC SID ACTDATA

DAC

EN

(Tied High)

NOTE A: EN is held high and data is written to a DAC register. The data is latched to the output of the DAC on the falling edge of the last CLK of the control word, where the

mode is set.

RS A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 2. First Nonzero Write Operation After Startup (EN = High)

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

double-buffered mode (MODE = 0)

In this mode, data is only latched to the output of the DACs on the falling edge of the EN strobe. Therefore, all
four DACs can be written to before updating their outputs.

Any number of input data blocks can be written with all having the same length. Subsequent data blocks simply
overwrite previous ones with the same address until EN goes low.

Multiple data blocks can be written in any sequence provided signal timing limits are met. The negative going
edge of EN terminates and latches all data.

Data Latched Into DAC Control Registers and Control Word

Multiple Random Sequence Data Blocks

DATA

EN

Figure 3. Data and Control Serial Control

SLAS138B – APRIL 1996 – REVISED FEBRUAR Y 1997

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

Template Release Date: 7–11–94

6

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

CLK

ПППППППППППППППППП

RS

MODE

RNGARNGBRNGCRNG

D

SIA SIB SIC SID ACT

DATA

DAC

EN

NOTE A: Data is written to the output of a DAC, and the data is latched to the output on the falling edge of EN. A control word then selects double-buffered mode. When the

range is changed, the output changes on the falling edge of EN.

RS A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 4. First Nonzero Write Operation After Startup