TEXAS INSTRUMENTS TLV5620C, TLV5620I Technical data

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

D

Four 8-Bit Voltage Output DACs

D

3-V Single-Supply Operation

D

Serial Interface

D

High-Impedance Reference Inputs

D

Programmable for 1 or 2 Times Output
Range

D

Simultaneous Update Facility

D

Internal Power-On Reset

D

Low-Power Consumption

D

Half-Buffered Output

applications

D

Programmable V oltage Sources

D

Digitally Controlled Amplifiers/Attenuators

D

Mobile Communications

D

Automatic Test Equipment

D

Process Monitoring and Control

D

Signal Synthesis

description

D OR N PACKAGE

(TOP VIEW)

GND
REFA
REFB

REFC
REFD

DATA

CLK

1
2
3
4
5
6
7

14
13
12
11
10

9
8

V

DD

LDAC
DACA
DACB
DACC
DACD
LOAD

The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use,
because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure
repeatable start-up conditions.

Digital control of the TL V5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises eight bits of data, two DAC select bits, and a range bit, the latter allowing selection between the times
1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs
feature Schmitt triggers for high noise immunity.

The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical
applications. The TLV5620C is characterized for operation from 0°C to 70°C. The TLV5620I is characterized
for operation from –40°C to 85°C. The TLV5620C and TLV5620I do not require external trimming.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLV5620CD TLV5620CN

–40°C to 85°C TLV5620ID TLV5620IN

SMALL OUTLINE

(D)

PLASTIC DIP

(N)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

TLV5620C, TLV5620I

I/O

DESCRIPTION

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

functional block diagram

2

REFA

REFB

REFC

REFD

CLK

DATA

LOAD

+
–

8 8

Latch Latch

3

+
–

8

Latch

4

+
–

8

5

+
–

8

Latch Latch

7
6
8

Serial

Interface

Latch

LatchLatch

13

LDAC

DAC

DAC

8

DAC

8

DAC

8

Power-On

Reset

× 2

× 2

× 2

× 2

+
–

+
–

+
–

+
–

12

11

10

9

DACA

DACB

DACC

DACD

Terminal Functions

TERMINAL

NAME NO.

CLK 7 I Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock

applied to the CLK terminal.
DACA 12 O DAC A analog output
DACB 11 O DAC B analog output
DACC 10 O DAC C analog output
DACD 9 O DAC D analog output
DATA 6 I Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.

Each data bit is clocked into the register on the falling edge of the clock signal.
GND 1 I Ground return and reference terminal
LDAC 13 I Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial

interface. The DAC outputs are only updated when LDAC is taken from high to low.
LOAD 8 I Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital

data into the output latch and immediately produces the analog voltage at the DAC output terminal.
REFA 2 I Reference voltage input to DAC A. This voltage defines the output analog range.
REFB 3 I Reference voltage input to DAC B. This voltage defines the analog output range.
REFC 4 I Reference voltage input to DAC C. This voltage defines the analog output range.
REFD 5 I Reference voltage input to DAC D. This voltage defines the analog output range.

V

DD

14 I Positive supply voltage

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

detailed description

The TLV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in T able 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer . Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the
reference source.

Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.

On power up, the DACs are reset to CODE 0.
Each output voltage is given by:

VO(DACA|B|C|D)+REF

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE

0 0 0 0 0 0 0 0 GND
0 0000001 (1/256) × REF (1+RNG)

• ••••••• •

• ••••••• •

0 1111111 (127/256) × REF (1+RNG)
1 0000000 (128/256) × REF (1+RNG)

• ••••••• •

• ••••••• •

1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG)

CODE

256

(1)

RNG bit value)

Table 1. Ideal Output Transfer

data interface

With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low . When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two 8-clock-cycle periods are shown in Figures 3 and 4.

Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode

A1 A0 DAC UPDATED

0 0 DACA
0 1 DACB
1 0 DACC
1 1 DACD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

CLK

t

su(DATA-CLK)

t

v(DATA-CLK)

t

su(LOAD-CLK)

DATA

LOAD

CLK

DATA

LOAD

LDAC

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

t

su(CLK-LOAD)

DAC Update

Figure 1. LOAD-Controlled Update (LDAC = Low)

t

su(DATA-CLK)

t

v(DATA-CLK)

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

t

su(LOAD-LDAC)

Figure 2. LDAC-Controlled Update

t

w(LOAD)

t

w(LDAC)

DAC Update

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLK

CLK Low

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 5

DATA

LOAD
LDAC

CLK

DATA

LOAD

LDAC

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low)

CLK Low

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

Figure 4. LDAC Controlled Update Using 8-Bit Serial Word

QUADRUPLE 8-DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUAR Y 1995 – REVISED APRIL 1997

TLV5620C, TLV5620I