TEXAS INSTRUMENTS TLV2354, TLV2354Y Technical data

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TLV2354Y

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Wide Range of Supply Voltages

2 V to 8 V

Fully Characterized at 3 V and 5 V

Very-Low Supply-Current Drain

240 µA Typ at 3 V

Common-Mode Input Voltage Range Includes Ground

High Input Impedance ...1012 Ω Typ

description

TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

Fast Response Time . . . 200 ns Typ for TTL-Level Input Step

Extremely Low Input Bias Current

5 pA Typ

Output Compatible With TTL, MOS, and CMOS

Built-In ESD Protection

symbol (each comparator)

The TLV2354 consists of four independent, low-power comparators specifically designed for single power-supply applications and operateS with power-supply rails as low as 2 V. When

IN+

OUT

IN–

powered from a 3-V supply, the typical supply current is only 240 µA.

The TLV2354 is designed using the Texas Instruments LinCMOS technology and, therefore, features an extremely high input impedance (typically greater than 10

Ω), which allows direct interfacing with high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic wired-AND relationships. The TL V2354I is fully characterized for operation from – 40°C to 85°C. The TLV2354M is fully characterized for operation from – 55°C to 125°C.

The TLV2354 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a 1000-V ESD rating using Human Body Model testing. However, care should be exercised in handling this device as exposure to ESD may result in degradation of the device parametric performance.

AVAILABLE OPTIONS

PACKAGED DEVICES

–40°C to

85°C

–55°C to

125°C

†

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL V2352IDR).

‡

The PW packages are only available left-ended taped and reeled (e.g., TLV2354IPWLE).

VIOmax

at 25°C

5 mV TLV2354ID — — TLV2354IN TLV2354IPWLE —

5 mV — TLV2354MFK TLV2354MJ — — TLV2354MW

SMALL

OUTLINE

†

(D)

CHIP

CARRIER

(FK)

CERAMIC

DIP

(J)

PLASTIC

DIP

(N)

TSSOP

(PW)

CERAMIC

‡

FLATPACK

(W)

FORM

(Y)

These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LINCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

TLV2354I

D OR N PACKAGE

(TOP VIEW)

1OUT 2OUT

2IN– 2IN+ 1IN– 1IN+

1OUT 2OUT

2IN– 2IN+ 1IN– 1IN+

1 2

4 5 6 7

TLV2354M

J OR W PACKAGE

(TOP VIEW)

1 2

4 5 6 7

14 13 12 11 10

9 8

3OUT 4OUT V

DD–

4IN+ 4IN– 3IN+ 3IN–

3OUT 4OUT V

DD–

4IN+ 4IN– 3IN+ 3IN–

/GND

TLV2354I

PW PACKAGE

(TOP VIEW)

1OUT 2OUT

2IN– 2IN+ 1IN– 1IN+

1 2 3

DD+

4 5 6 7

TLV2354AM, TLV2354M

FK PACKAGE

(TOP VIEW)

2OUT

DD+

2IN–

2IN+

3 2 1 20 19

4 5 6 7 8

910111213

1OUT

14 13 12 11 10

9 8

3OUT

3OUT 4OUT V

DD–

4IN+ 4IN– 3IN+ 3IN–

4OUT

18 17 16 15 14

/GND

DD–

NC 4IN+ NC 4IN–

/GND

NC – No internal connection

1IN–

1IN+

3IN–

3IN +

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OUT

TLV2254, TLV2254Y

QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORSLinCMOS

SLCS012B – MAY 1992 – REVISED MARCH 1999

Common to All Channels

IN–

IN+

equivalent schematic

GND

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 3

TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

TLV2354Y chip information

This chip, when properly assembled, displays characteristics similar to the TL V2354. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with conductive epoxy or a gold-silicon preform.

(13)

(14)

(1)

(2)

BONDING PAD ASSIGNMENTS

(12)

(11)

(3)

(4)

(5)

(6)

(9)(10)

(8)

(7)

–

GND

(3)

(12)

(1)

OUT

(5)

–

(4)

(14)

(11)

(10)

IN+

IN–

OUT

IN+

IN–

(7)

IN+

(6)

IN–

(2)

OUT

(9)

IN+

(8)

IN–

(13)

OUT

CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (11) INTERNALLY CONNECTED

TO BACKSIDE OF CHIP.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

Common-mode input voltage, V

O erating free-air tem erature, T

°C

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VDD (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, VID (see Note 2) ±8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

Output voltage, VO 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, IO 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duration of output short-circuit current to GND (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package 260°C. . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FK, J, or W package 300°C. . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.

2. Differential voltages are at the noninverting input terminal with respect to the inverting input terminal.

3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.

PACKAGE

–0.3 to 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: TLV2354I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV2354M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DISSIPATION RATING TABLE

TA ≤ 25°C

POWER RATING

950 mW 1375 mW 1375 mW 1150 mW

700 mW

DERATING

FACTOR

7.6 mW/°C

11.0 mW/°C

9.2 mW/°C

5.6 mW/°C

5.5 mW/°C

TA = 85°C

POWER RATING

494 mW 715 mW 715 mW 598 mW 364 mW 370 mW

TA = 125°C

POWER RATING

275 mW 275 mW

150 mW

—

— —

†

recommended operating conditions

Supply voltage, V

VDD = 3 V 0 1.75 VDD = 5 V 0 3.75 TLV2354I –40 85 TLV2354M –55 125

MIN MAX UNIT

2 8 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

‡

VIOInput offset voltage

min

See Note 4

IIOInput offset current

IIBInput bias current

Common-mode input I

IDDSupply current

No load

PARAMETER

TEST CONDITIONS

UNIT

Response time

100-mV input step with 5-mV overdrive

640

PARAMETER

TEST CONDITIONS

UNIT

Response time

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

electrical characteristics at specified free-air temperature

PARAMETER TEST CONDITIONS

ICR

voltage range

High-level output

current Low-level output

voltage

† ‡

NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V , 2 V with VDD = 3 V , or

Low-level output

current

All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is –40°C to 85°C. IMPORTANT: See Parameter Measurement Information.

below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.

= 1

= –1 V,

VID = –1 V, VOL = 1.5 V 25°C 6 16 6 16 mA

= 1 V,

ICR

= 2

25°C

Full range

25°C 85°C 25°C 85°C 25°C 0 to 2 0 to 4

Full range

25°C

Full range

25°C

Full range

25°C

Full range

†

TLV2354I

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

1 5 1 5

7 7

1 1

5 5

2 2

0 to

1.75

0.1 0.1

115 300 150 400

240 500 290 600

0 to

3.75

1 1

600 700

700 800

UNIT

pA nA pA nA

µA

switching characteristics, V

CL includes probe and jig capacitance.

NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with

VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.

RL = 5.1 kΩ, See Note 5

= 3 V, T

CL = 15 pF§,

= 25°C

TLV2354I

MIN TYP MAX

switching characteristics, VDD = 5 V, TA = 25°C

TLV2354I

MIN TYP MAX

CL includes probe and jig capacitance.

NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with

VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.

RL = 5.1 kΩ, See Note 5

= 15 pF§,

100-mV input step with 5-mV overdrive 650 TTL-level input step 200

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

‡

VIOInput offset voltage

min

See Note 4

IIOInput offset current

IIBInput bias current

Common-mode input I

IDDSupply current

No load

PARAMETER

TEST CONDITIONS

UNIT

Response time

100-mV input step with 5-mV overdrive

1400

PARAMETER

TEST CONDITIONS

UNIT

Response time

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

electrical characteristics at specified free-air temperature

PARAMETER TEST CONDITIONS

ICR

voltage range

High-level output

current Low-level output

voltage Low-level output

current

†

All characteristics are measured with zero common-mode input voltage unless otherwise noted.

‡

Full range is –55°C to 125°C. IMPORTANT: See Parameter Measurement Information.

NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V , 2 V with VDD = 3 V , or

below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.

= 1

= –1 V,

VID = –1 V, VOL = 1.5 V 25°C 6 16 6 16 mA

= 1 V,

ICR

= 2

25°C

Full range

25°C

125°C

25°C

125°C

25°C 0 to 2 0 to 4

Full range

25°C

Full range

25°C

Full range

25°C

Full range

†

TLV2354M

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

1 5 1 5

10 10

1 1

10 10

5 5

20 20

0 to

1.75

0.1 0.1

115 300 150 400

240 500 290 600

0 to

3.75

1 1

600 700

700 800

UNIT

pA nA pA nA

µA

switching characteristics, V

CL includes probe and jig capacitance.

NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with

VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.

RL = 5.1 kΩ, See Note 5

= 3 V, T

CL = 100 pF§,

= 25°C

TLV2354M

MIN TYP MAX

switching characteristics, VDD = 5 V, TA = 25°C

TLV2354M

MIN TYP MAX

CL includes probe and jig capacitance.

NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with

VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.

RL = 5.1 kΩ, See Note 5

= 100 pF§,

100-mV input step with 5-mV overdrive 1300 TTL-level input step 900

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

electrical characteristics at specified free-air temperature, TA = 25°C

PARAMETER TEST CONDITIONS

V I I V I V I

I † NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V , 2 V with VDD = 3 V , or

Input offset voltage VIC = V

Input offset current 1 1 pA

Input bias current 5 5 pA

Common-mode input voltage range 0 to 2 0 to 4 V

ICR

High-level output current VID = 1 V 0.1 0.1 nA

Low-level output voltage VID = –1 V, IOL = 2 mA 115 300 150 400 mV

Low-level output current VID = –1 V, VOL = 1.5 V 6 16 6 16 mA

Supply current VID = 1 V, No load 240 500 290 600 µA

DD All characteristics are measured with zero common-mode input voltage unless otherwise noted.

below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.

min, See Note 4 1 5 1 5 mV

ICR

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

†

TLV2354Y

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

1100

VDD = 3 V

990

TA = 25°C

880

770

660 550

440

330

– Low-Level Output Voltage – mV

220

110

024681012

IOL – Low-Level Output Current – mA

Figure 1

14 16

SUPPLY CURRENT

FREE-AIR TEMPERATURE

380 360

340

Aµ

320 300

280

VDD = 3 V

260

– Supply Current –

240

220 200 180

– 75 – 50 –25 0 25 50 75

TA – Free-Air Temperature – °C

VDD = 5 V

Figure 2

No Load

100 125

COMMON-MODE INPUT VOLTAGE RANGE

FREE-AIR TEMPERATURE

VDD = 3 V

2.5

1.5

0.5

– Common-Mode Input Voltage Range – V

– 0.5

ICR

– 1

– 75 – 50 – 25 0 25 50

TA – Free-Air Temperature – °C

Positive Limit

Negative Limit

Figure 3

75 100 125

OUTPUT FALL TIME

CAPACITIVE LOAD

VDD = 3 V

Overdrive = 10 mV RL = 5.1 kΩ (pullup to VDD)

TA = 25°C

30 25

– Output Fall Time – nsf

5 0

0 102030405060

CL – Capacitive Load – pF

70 80 90 100

Figure 4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

TYPICAL CHARACTERISTICS

– Output

Voltage – V

100

– Differential

Input Voltage – mV

HIGH-TO-LOW-LEVEL OUTPUT

PROPAGATION DELAY

FOR VARIOUS OVERDRIVE VOLTAGES

VDD = 3 V CL = 15 pF RL = 5.1 kΩ (pullup to VDD) TA = 25°C

20 mV

0 100 200 300 400 500 600

– High-to-Low-Level Output

PHL

Propagation Delay Time – ns

5 mV

10 mV

700 800 900 1000

Figure 5

VDD = 3 V Overdrive = 10 mV RL = 5.1 kΩ (pullup to VDD) TA = 25°C

– Output

Voltage – V

100

– Differential

Input Voltage – mV

HIGH-TO-LOW-LEVEL OUTPUT

PROPAGATION DELAY

FOR VARIOUS CAPACITIVE LOADS

CL = 15 pF

0 100 200 300 400 500 6003700 800 900 1000

– High-to-Low-Level Output

PHL

Propagation Delay Time – ns

CL = 100 pF

CL = 50 pF

Figure 6

– Output

Voltage – V

100

– Differential

Input Voltage – mV

LOW-TO-HIGH-LEVEL OUTPUT

PROPAGATION DELAY

FOR VARIOUS OVERDRIVE VOLTAGES

VDD = 3 V CL = 15 pF RL = 5.1 kΩ (pullup to VDD) TA = 25°C

20 mV

5 mV

10 mV

0 100 200 300 400 500 600

– Low-to-High-Level Output

PLH

Propagation Delay Time – ns

700 800 900 1000

Figure 7

– Output

Voltage – V

100

– Differential

Input Voltage – mV

LOW-TO-HIGH-LEVEL OUTPUT

PROPAGATION DELAY

FOR VARIOUS CAPACITIVE LOADS

VDD = 3 V Overdrive = 10 mV RL = 5.1 kΩ (pullup to VDD) TA = 25°C

CL = 15 pF

0 100 200 300 400 500 6003700 800 900 1000

– Low-to-High-Level Output

PLH

Propagation Delay Time – ns

CL = 50 pF

CL = 100 pF

Figure 8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

PARAMETER MEASUREMENT INFORMATION

The digital output stage of the TLV2354 can be damaged if it is held in the linear region of the transfer curve. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are offered.

To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 9(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low.

A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 9(b) for the V accuracy.

5 V

test rather than changing the input voltages to provide greater

ICR

1 V

5.1 kΩ 5.1 kΩ

Applied V

Limit

–

– 4 V

Applied V

Limit

(a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V

–

Figure 9. Method for Verifying That Input Offset Voltage Is Within Specified Limits

A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal but opposite in polarity to the input offset voltage, the output changes states.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

PARAMETER MEASUREMENT INFORMATION

Figure 10 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer , with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test while the noninverting input is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage.

Voltage dividers R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower.

Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently , this open-socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device.

0.1 µF

U1b 1/4 TLV2354

R3 100 Ω

–

Buffer

240 kΩ

U1a 1/4 TLV2354

Triangle

Generator

10 kΩ

1 µF

47 kΩ

–

DUT

R10 100 Ω, 1%

1.8 kΩ, 1%

5.1 kΩ

1 MΩ

1.8 kΩ, 1%

10 kΩ, 1%

0.1 µF

0.68 µF

U1c 1/4 TLV2354

–

Integrator

(×100)

Figure 10. Circuit for Input Offset Voltage Measurement

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TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

PARAMETER MEASUREMENT INFORMATION

Propagation delay time is defined as the interval between the application of an input step function and the instant when the output crosses VO = 1 V with VDD = 3 V or when the output crosses VO = 1.4 V with VDD = 5 V . Propagation delay time, low-to-high-level output, is measured from the leading edge of the input pulse, while propagation delay time, high-to-low-level output, is measured from the trailing edge of the input pulse. Propagation-delay-time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then a low signal, for example a 105-mV or 5-mV overdrive, causes the output to change state.

Input Offset Voltage

Compensation

Adjustment

Input

Low- to High-

Level Output

Pulse

Generator

+ 1 V

– 1 V

Overdrive

10 Ω

10 Turn

10%

100 mV

90%

50 Ω

1 kΩ

TEST CIRCUIT

VO = 1 V With VDD = 3 V

VO = 1.4 V With VDD = 5 V

0.1 µF

5.1 kΩ

DUT

–

Overdrive

100 mVInput

90%

1 µF

(see Note A)

High- to LowLevel Output

10%

PLH

NOTE A: CL includes probe and jig capacitance.

VOLTAGE WAVEFORMS

PHL

Figure 11. Propagation Delay, Rise, and Fall Times Test Circuit and Voltage Waveforms

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TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.069 (1,75) MAX

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

PINS **

DIM

A MAX

A MIN

0.008 (0,20) NOM

Gage Plane

0°–8°

0.197

(5,00)

0.189

(4,80)

0.344 (8,75)

0.337

(8,55)

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

4040047/B 03/95

0.394

(10,00)

0.386

(9,80)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Four center pins are connected to die mount pad.

E. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

MECHANICAL INFORMATION

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

12826 27

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342 (8,69)

0.442

0.640

0.740

0.938

1.141

0.358

(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

(10,31)

(12,58)

NO. OF

TERMINALS

432

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307 (7,80)

0.406

0.495

0.850 (21,6)

1.047 (26,6)

0.080 (2,03)

0.064 (1,63)

MAX

0.358

(9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858

(21,8)

1.063

(27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/C 11/95

TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

MECHANICAL INFORMATION

J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE

14 PIN SHOWN

0.100 (2,54)

0.070 (1,78)

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.200 (5,08) MAX

PINS **

DIM

A MAX

A MIN

B MAX

B MIN

C MAX

C MIN

Seating Plane

0.310

(7,87)

0.290

(7,37)

0.785

(19,94)

0.755

(19,18)

0.280 (7,11)

0.245

(6,22)

0.310

(7,87)

0.290 (7,37)

0.785

(19,94)

0.755

(19,18)

0.300 (7,62)

0.245 (6,22)

0.310

(7,87)

0.290

(7,37)

0.910

(23,10)

0.300

(7,62)

0.245

(6,22)

20181614

0.310

(7,87)

0.290

(7,37)

0.975

(24,77)

0.930

(23,62)

0.300

(7,62)

0.245

(6,22)

0.410

(10,41)

0.390

(9,91)

1.100

(28,00)

0.388

(9,65)

0.100 (2,54)

0.023 (0,58)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

E. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22

0.130 (3,30) MIN

0°–15°

0.014 (0,36)

0.008 (0,20) 4040083/B 04/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

MECHANICAL INFORMATION

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

16 PIN SHOWN

0.035 (0,89) MAX

PINS **

DIM

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

A MAX

A MIN

Seating Plane

0.775

(19,69)

0.745

(18,92)

0.775

(19,69)

0.745

(18,92)

0.920

(23.37)

0.850

(21.59)

0.975

(24,77)

0.940

(23,88)

0.310 (7,87)

0.290 (7,37)

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

0.010 (0,25)

0.125 (3,18) MIN

0°–15°

0.010 (0,25) NOM

14/18 PIN ONL Y

4040049/C 08/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

MECHANICAL INFORMATION

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,65

1,20 MAX

0,10 MIN

0,32 0,19

4,50 4,30

6,70 6,10

0,13

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75 0,50

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

6,60

6,404,90

7,90

7,70

9,80

9,60

4040064/D 10/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

MECHANICAL INFORMATION

W (R-GDFP-F14) CERAMIC DUAL FLATPACK

0.080 (2,03)

0.045 (1,14)

0.390 (9,91)

0.335 (8,51)

0.360 (9,14)

0.240 (6,10)

0.260 (6,60)

0.235 (5,97)

0.280 (7,11)

0.255 (6,48)

Base and Seating Plane

0.007 (0,18)

0.004 (0,10)

0.045 (1,14)

0.026 (0,66)

0.360 (9,14)

141

0.240 (6,10)

0.019 (0,48)

0.015 (0,38)

0.050 (1,27)

0.025 (0,64)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

1.000 (25,40)

0.735 (18,67)

4040180-2/B 03/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

TEXAS INSTRUMENTS TLV2354, TLV2354Y Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual