TEXAS INSTRUMENTS TLV2354, TLV2354Y Technical data

CHIP

TLV2354Y

查询TLV2354供应商

D

Wide Range of Supply Voltages

2 V to 8 V

D

Fully Characterized at 3 V and 5 V

D

Very-Low Supply-Current Drain

240 µA Typ at 3 V

D

Common-Mode Input Voltage Range
Includes Ground

D

High Input Impedance ...1012 Ω Typ

description

TLV2354, TLV2354Y

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

D

Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step

D

Extremely Low Input Bias Current

5 pA Typ

D

Output Compatible With TTL, MOS, and
CMOS

D

Built-In ESD Protection

symbol (each comparator)

The TLV2354 consists of four independent,
low-power comparators specifically designed for
single power-supply applications and operateS
with power-supply rails as low as 2 V. When

IN+

OUT

IN–

powered from a 3-V supply, the typical supply
current is only 240 µA.

The TLV2354 is designed using the Texas Instruments LinCMOS technology and, therefore, features an
extremely high input impedance (typically greater than 10

12

Ω), which allows direct interfacing with
high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup
resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic
wired-AND relationships. The TL V2354I is fully characterized for operation from – 40°C to 85°C. The TLV2354M
is fully characterized for operation from – 55°C to 125°C.

The TLV2354 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a
1000-V ESD rating using Human Body Model testing. However, care should be exercised in handling this device
as exposure to ESD may result in degradation of the device parametric performance.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

–40°C to

85°C

–55°C to

125°C

†

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL V2352IDR).

‡

The PW packages are only available left-ended taped and reeled (e.g., TLV2354IPWLE).

VIOmax

at 25°C

5 mV TLV2354ID — — TLV2354IN TLV2354IPWLE —

5 mV — TLV2354MFK TLV2354MJ — — TLV2354MW

SMALL

OUTLINE

†

(D)

CHIP

CARRIER

(FK)

CERAMIC

DIP

(J)

PLASTIC

DIP

(N)

TSSOP

(PW)

CERAMIC

‡

FLATPACK

(W)

FORM

(Y)

These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LINCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

TLV2354I

D OR N PACKAGE

(TOP VIEW)

1OUT
2OUT

V

2IN–
2IN+
1IN–
1IN+

1OUT
2OUT

V

2IN–
2IN+
1IN–
1IN+

1
2

+

3

DD

4
5
6
7

TLV2354M

J OR W PACKAGE

(TOP VIEW)

1
2

+

3

DD

4
5
6
7

14
13
12
11
10

14
13
12
11
10

9
8

9
8

3OUT
4OUT
V

DD–

4IN+
4IN–
3IN+
3IN–

3OUT
4OUT
V

DD–

4IN+
4IN–
3IN+
3IN–

/GND

/GND

TLV2354I

PW PACKAGE

(TOP VIEW)

1OUT
2OUT

V

2IN–
2IN+
1IN–
1IN+

1
2
3

DD+

4
5
6
7

TLV2354AM, TLV2354M

FK PACKAGE

(TOP VIEW)

2OUT

V

DD+

NC

2IN–

NC

2IN+

3 2 1 20 19

4
5
6
7
8

910111213

1OUT

NC

14
13
12
11
10

9
8

3OUT

3OUT
4OUT
V

DD–

4IN+
4IN–
3IN+
3IN–

4OUT

18
17
16
15
14

/GND

V

DD–

NC
4IN+
NC
4IN–

/GND

NC – No internal connection

1IN–

1IN+

NC

3IN–

3IN +

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OUT

TLV2254, TLV2254Y

QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORSLinCMOS

SLCS012B – MAY 1992 – REVISED MARCH 1999

Common to All Channels

IN–

IN+

DD

equivalent schematic

V

GND

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 3

TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

TLV2354Y chip information

This chip, when properly assembled, displays characteristics similar to the TL V2354. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with
conductive epoxy or a gold-silicon preform.

65

(13)

(14)

(1)

(2)

BONDING PAD ASSIGNMENTS

(12)

(11)

(3)

90

(4)

(5)

(6)

(9)(10)

(8)

(7)

V

DD

+

–

+

–

GND

(3)

(12)

(1)

OUT

(5)

+

–

+

–

(4)

(14)

(11)

(10)

IN+

IN–

OUT

IN+

IN–

(7)

IN+

(6)

IN–

(2)

OUT

(9)

IN+

(8)

IN–

(13)

OUT

CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) INTERNALLY CONNECTED

TO BACKSIDE OF CHIP.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2354, TLV2354Y

Common-mode input voltage, V

V

O erating free-air tem erature, T

A

°C

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VDD (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, VID (see Note 2) ±8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

Output voltage, VO 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, IO 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duration of output short-circuit current to GND (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package 260°C. . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FK, J, or W package 300°C. . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.

2. Differential voltages are at the noninverting input terminal with respect to the inverting input terminal.

3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.

PACKAGE

–0.3 to 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

: TLV2354I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

TLV2354M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DISSIPATION RATING TABLE

D

FK

J

N

PW

W

TA ≤ 25°C

POWER RATING

950 mW
1375 mW
1375 mW
1150 mW

700 mW

700 mW

DERATING

FACTOR

7.6 mW/°C

11.0 mW/°C

11.0 mW/°C

9.2 mW/°C

5.6 mW/°C

5.5 mW/°C

TA = 85°C

POWER RATING

494 mW
715 mW
715 mW
598 mW
364 mW
370 mW

TA = 125°C

POWER RATING

275 mW
275 mW

150 mW

—

—
—

†

recommended operating conditions

Supply voltage, V

p

DD

p

IC

p

VDD = 3 V 0 1.75
VDD = 5 V 0 3.75
TLV2354I –40 85
TLV2354M –55 125

MIN MAX UNIT

2 8 V

°

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLV2354, TLV2354Y

‡

A

VIOInput offset voltage

V

V

min

See Note 4

mV

IIOInput offset current

IIBInput bias current

Common-mode input
I

g

V

V

V

V

I

mA

mA

IDDSupply current

V

No load

A

PARAMETER

TEST CONDITIONS

UNIT

Response time

L

100-mV input step with 5-mV overdrive

640

ns

PARAMETER

TEST CONDITIONS

UNIT

Response time

L

L

,

ns

LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS

SLCS012B – MAY 1992 – REVISED MARCH 1999

electrical characteristics at specified free-air temperature

PARAMETER TEST CONDITIONS

p

p

p

V

ICR

voltage range

High-level output

OH

current
Low-level output

OL

voltage

I

†
‡

NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V , 2 V with VDD = 3 V , or

Low-level output

OL

current

pp

All characteristics are measured with zero common-mode input voltage unless otherwise noted.
Full range is –40°C to 85°C. IMPORTANT: See Parameter Measurement Information.

below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and
checking for the appropriate output state.

p

=

IC

= 1

ID

= –1 V,

ID

VID = –1 V, VOL = 1.5 V 25°C 6 16 6 16 mA

= 1 V,

ID

ICR

,

= 2

OL

T

A

25°C

Full range

25°C
85°C
25°C
85°C
25°C 0 to 2 0 to 4

Full range

25°C

Full range

25°C

Full range

25°C

Full range

†

TLV2354I

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

1 5 1 5

7 7

1 1

1 1

5 5

2 2

0 to

1.75

0.1 0.1

115 300 150 400

240 500 290 600

0 to

3.75

1 1

600 700

700 800

UNIT

pA
nA
pA
nA

V

nA

µA

µ

switching characteristics, V

p

§

CL includes probe and jig capacitance.

NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with

VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.

RL = 5.1 kΩ,
See Note 5

= 3 V, T

DD

CL = 15 pF§,

= 25°C

A

TLV2354I

MIN TYP MAX

p

p

switching characteristics, VDD = 5 V, TA = 25°C

TLV2354I

MIN TYP MAX

p

§

CL includes probe and jig capacitance.

NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with

VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.

RL = 5.1 kΩ,
See Note 5

C

= 15 pF§,

100-mV input step with 5-mV overdrive 650
TTL-level input step 200

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265