TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023C – FEBRUARY 1989 – REVISED MAY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of equivalent input and output
EQUIVALENT OF ANALOG OUTPUTEQUIVALENT OF EACH DIGITAL INPUT
ANLG
‡
GND
A OUT
80 Ω
ANLG V
DD1
D
n
DGTL V
DD
ANLG
‡
GND
DGTL
‡
GND
DGTL V
DD
‡
ANLG GND and DGTL GND do not connect internally and should be tied together as close to the device terminals as possible.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, ANLG V
DD
, DGTL VDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, V
I
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog reference voltage range, V
ref
V
DD
– 1.7 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TLC5602C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC5602M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
DD
4.75 5 5.25 V
Analog reference voltage, V
ref
3.8 4 4.2 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
Pulse duration, CLK high or low, t
w
25 ns
Setup time, data before CLK↑, t
su
16.5 ns
Hold time, data after CLK↑, t
h
12.5 ns
Phase compensation capacitance, C
comp
(see Note 1) 1 µF
Load resistance, R
L
75k Ω