TEXAS INSTRUMENTS TLC3544, TLC3548 Technical data

查询TLC3544CDWR供应商

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548

SLAS266C – OCTOBER 2000 – REVISED MA Y 2003

D 14-Bit Resolution
D Maximum Throughput 200 KSPS
D Analog Input Range 0-V to Reference

Voltage

D Multiple Analog Inputs:

– 8 Channels for TLC3548
– 4 Channels for TLC3544

D Pseudodifferential Analog Inputs
D SPI/DSP-Compatible Serial Interfaces With

SCLK up to 25 MHz

D Single 5-V Analog Supply; 3-/5-V Digital

Supply

D Low Power:

– 4 mA (Internal Reference: 1.8 mA) for

Normal Operation

– 20 µA in Autopower-Down

D Built-In 4-V Reference, Conversion Clock

and 8x FIFO

D Hardware-Controlled and Programmable

Sampling Period

D Programmable Autochannel Sweep and

Repeat

D Hardware Default Configuration
D INL: ±1 LSB Max
D DNL: ±1 LSB Max
D SINAD: 80.8 dB
D THD: –95 dB

description

SCLK

FS

SDI

EOC/INT

SDO

DGND

DV

DD

CS

A0
A1
A2
A3

SCLK

FS

SDI

EOC/INT

SDO

DGND

DV

DD

CS

A0
A1

TLC3548

DW OR PW PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12

TLC3544

DW OR PW PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10

24
23
22
21
20
19
18
17
16
15
14
13

20
19
18
17
16
15
14
13
12
11

CSTART
AV

DD

AGND
BGAP
REFM
REFP
AGND
AV

DD

A7
A6
A5
A4

CSTART
AV

DD

AGND
BGAP
REFM
REFP
AGND
AV

DD

A3
A2

The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS
analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V
digital supply. The serial interface consists of four digital inputs [chip select (CS
input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS

), frame sync (FS), serial

(works as SS,
slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The
frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters
connect to one serial port of a DSP, CS
converter. CS

can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such

as in an SPI interface). When SDI is tied to DV

works as the chip select to allow the host DSP to access the individual

, the device is set in hardware default mode after power-on,

DD

and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS
are needed to interface with the host.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000 – 2003, Texas Instruments Incorporated

or FS)

1

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

description (continued)

In addition to being a high-speed ADC with versatile control capability , these devices have an on-chip analog
multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART
extend the sampling period (extended sampling). The normal sampling period can also be programmed as short
sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among
high-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low power
consumption. The power saving feature is further enhanced with software power-down/ autopower-down
modes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter
can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548
have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-V
external reference is used.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

0°C to 70°C TLC3544CPW TLC3544CDW TLC3548CDW TLC3548CPW

–40°C to 85°C TLC3544IPW TLC3544IDW TLC3548IDW TLC3548IPW

20-TSSOP

(PW)

20-SOIC

(DW)

24-SOIC

(DW)

24-TSSOP

(PW)

to

functional block diagram

REFP
BGAP
REFM

X4

X8

A0

A0

A1

A1

A2

A2

A3

A3

X

A4

X

A5

X

A6

X

A7

SDI

SCLK

CS

FS

CSTART

4-V

Reference

Command

CMR (4 MSBs)

Analog

MUX

Decode

4-Bit

Counter

OSC

DVDDAV

Conversion

DD

Clock

Control

Logic

SAR
ADC

CFR

FIFO

X8

SDO

EOC/INT

DGND AGND

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

I/O

DESCRIPTION

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

equivalent input circuit

V

DD

TLC3544, TLC3548

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

MUX

1.1 kΩ

Max

Ain

Diode Turn on Voltage: 35 V

Equivalent Analog Input Circuit

R

on

REFM

C

(sample)

= 30 pF Max

Digital Input

Equivalent Digital Input Circuit

V

DD

Terminal Functions

TERMINAL

NAME

A0
A1
A2
A3

AGND 14, 18 18, 22 I Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage

AV

DD

BGAP 17 21 I Internal bandgap compensation pin. Install compensation capacitors between BGAP and AGND.

CS 8 8 I Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is

CSTART 20 24 I External sampling trigger signal, which initiates the sampling from a selected analog input channel

DGND 6 6 I Digital ground return for the internal circuitry
DV

DD

TLC3544 TLC3548

A0
A1
A2
A3
A4
A5
A6
A7

NO.

9
10
11
12

13, 19 17, 23 I Analog supply voltage

7 7 I Digital supply voltage

10
11
12
13
14
15
16

I/O DESCRIPTION

9

I Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The

driving source impedance should be less than or equal to 1 kΩ for normal sampling. For larger
source impedance, use the external hardware conversion start signal CSTART (the low time of
CSTART
time.

measurements are with respect to AGND.

0.1 µF for external reference; 10 µF in parallel with 0.1 µF for internal reference.

disabled to clock data but works as conversion clock source if programmed. The falling edge of CS
input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from
high-impedance state.

If FS is high at CS
select (SS

If FS is low at CS
select to allow the host to access the individual converter.

when the device works in extended sampling mode (asynchronous sampling). A high-to-low
transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold
mode and starts the conversion. The low time of the CST ART
CSTART
after the low-to-high transition for the conversion to finish maturely. The activation of CSTART
independent of SCLK and the level of CS
before the rising edge of the 1 1th SCLK. Tie this terminal to DVDD if not used.

controls the sampling period) or reduce the frequency of SCLK to increase the sampling

falling edge, CS falling edge initiates the operation cycle. CS works as slave

) to provide an SPI interface.

falling edge, FS rising edge initiates the operation cycle. CS can be used as chip

signal must be long enough for proper sampling. CSTART must stay high long enough

signal controls the sampling period.

is

and FS. However, the first CSTART cannot be issued

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLC3544, TLC3548

I/O

DESCRIPTION

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

Terminal Functions (Continued)

TERMINAL

NAME

EOC(INT) 4 4 O End of conversion (EOC) or interrupt to host processor (INT)

FS 2 2 I Frame sync input from DSP. The rising edge of FS indicates the start of a serial data frame being

REFM 16 20 I External low reference input. Connect REFM to AGND.
REFP 15 19 I External positive reference input. When an external reference is used, the range of maximum input

SCLK 1 1 I Serial clock input from the host processor to clock in the input from SDI and clock out the output

SDI 3 3 I Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits,

SDO 5 5 O The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO.

TLC3544 TLC3548

NO.

I/O DESCRIPTION

EOC: used in conversion mode 00 only. EOC goes from high to low at the end of the sampling and
remains low until the conversion is complete and data is ready .

INT

: Interrupt to the host processor. The falling edge of INT indicates data is ready for output. INT

is cleared by the following CS↓, FS↑, or CSTART↓.

transferred (coming into or being sent out of the device). If FS is low at the falling edge of CS
rising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI,
SDO, and SCLK. Tie this pin to DVDD if FS is not used to initiate the operation cycle.

voltage is determined by the difference between the voltage applied to this terminal and to the
REFM terminal. Always install decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP
and REFM.

via SDO. It can also be used as the conversion clock source when the external conversion clock
is selected (see Table 2). When CS is low, SCLK is enabled. When CS is high, SCLK is disabled
for the data transfer, but can still work as the conversion clock source.

except for the CONFIGURE WRITE command, are filled with zeros. The CONFIGURE WRITE
command requires additional 12-bit data. The MSB of input data, ID[15], is latched at the first falling
edge of SCLK following FS falling edge, if FS starts the operation, or latched at the falling edge of
first SCLK following CS

The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the falling
edge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or a
low-to-high transition of CS
requirements. Tie SDI to DVDD if using hardware default mode (refer to device initialization).

SDO is in the high-impedance state when CS
output format is MSB (OD[15]) first.

When FS initiates the operation, the MSB of output via SDO, OD[15], is valid before the first falling
edge of SCLK following the falling edge of FS.

When CS
following the CS

The remaining data bits are shifted out on the rising edge of SCLK and are valid before the falling
edge of SCLK. Refer to the timing specification for the details.

In a select/conversion operation, the first 14 bits are the results from the previous conversion (data).
In READ FIFO operation, the data is from FIFO. In both cases, the last two bits are don’t care.

In a WRITE operation, the output from SDO is ignored.
SDO goes into high-impedance state at the sixteenth falling edge of SCLK after the operation cycle

is initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11.

initiates the operation, the MSB, OD[15], is valid before the first falling edge of SCLK

falling edge when CS initiates the operation.

, whichever happens first. Refer to the timing specification for the timing

is high. SDO is released after a CS falling edge. The

falling edge.

, the

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC3544, TLC3548

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, GND to AV
Analog input voltage range –0.2 V to AV

, DVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

†

DD

+0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input current 100 mA MAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage AV
Digital input voltage range –0.3 V to DV
Operating virtual junction temperature range, T
Operating free-air industrial temperature range, T

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

:I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

DD
DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1.16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC3544, TLC3548

VILLow level control in ut voltage

High level digital out ut

Low level digital out ut

OL

Off state out ut current

y

Power su ly
Autopower-down power supply

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V , external reference (V
V

= 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,

REFM

analog input signal source resistance = 25 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Digital Input

V

IH

V

I

IH

I

IL

Digital output

V

OH

V

OL

I

OZ

Power Supply

AV

DD

DV

DD

I

CC

I

CC(SW)

I

CC(Autodown)

Operating temperature

†

All typical values are at TA = 25°C.

High-level control input voltage

Low-level control input voltage

High-level input current VI = DV
Low-level input current VI = DGND –2.5 0.005 µA
Input capacitance 20 25 pF

High-level digital output,
VOH at 30-pF load

Low-level digital output,
VOL at 30-pF load

Off-state output current
(high-impedance state)

pp

Supply voltage

Power suppl
current

Software power-down power supply current

p

current

-

p

,

,

AVDD current­AI

CC
DVDD current­DI

CC

p

pp

DVDD = 5 V 3.8
DVDD = 3 V
DVDD = 5 V 0.8
DVDD = 3 V 0.6

DD

IO = –0.2 mA

DVDD = 5 V

DVDD = 3 V
VO = DV

VO = DGND

Conversion clock is internal OSC,
EXT. reference, A VDD = 5.5 V to 4.5 V,

= DGND

CS
For all digital inputs DVDD or

DGND, CS = DVDD,
AVDD = 5.5 V

For all digital inputs DVDD or
DGND, AVDD = 5.5 V,
External reference

C suffix 0 70
I suffix –40 85

DVDD = 5 V 4.2
DVDD = 3 V 2.4
IO = 0.8 mA 0.4
IO = 50 µA 0.1
IO = 0.8 mA 0.4
IO = 50 µA 0.1

DD

CS = DV

DD

SCLK ON 175 240
SCLK OFF 20
SCLK ON 175 230
SCLK OFF 20

2.1

0.005 2.5 µA

0.02 1

–1 –0.02

4.5 5 5.5 V

2.7 5 5.5 V

2.8 3.6

1.2 2

REFP

= 4 V ,

V

V

V

V

µA

mA

µA

µA

°C

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC3544, TLC3548

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V , external reference (V
V

= 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,

REFM

analog input signal source resistance = 25 Ω (unless otherwise noted) (continued)

PARAMETER TEST CONDITIONS MIN TYP

Resolution 14 bits
Analog Input

Voltage range 0 Reference V
Leakage current 0.01 0.05 µA
Capacitance 30 pF

Reference

Internal reference voltage 3.85 4 4.07 V
Internal reference temperature

coefficient
Internal reference source current 1.8 2.5 mA
Internal reference startup time 20 ms

V

REFP

V

REFM

Throughput Rate

f Internal oscillation frequency DVDD = 2.7 V to 5.5 V 6.5 MHz

t

(conv)

DC Accuracy—Normal Long Sampling

E

L

E

D

E

O

E

(g+)

†

All typical values are at TA = 25°C.

NOTES: 1. Conversion time t

External positive reference voltage 3 5 V
External negative reference voltage 0 AGND V

No conversion (AVDD = 5 V,
CS

= DVDD, SCLK = DGND)

External reference input impedance

External reference current

Conversion time

Acquisition time Normal short sampling 1.2 µs
Throughput rate (see Note 2)

Integral linearity error See Note 3 –1 ±0.5 1 LSB
Differential linearity error –1 ±0.5 1 LSB
Zero offset error See Note 4 –3 ±0.6 3 LSB
Gain error See Note 4 0 5 12 LSB

= (18x4 / SCLK) + 15 ns.

2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC (refer to Figure 8).

3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.

4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the
difference between 1 1111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the
reference voltage being used.

(conv)

Normal long sampling (AVDD = 5 V,

= DGND, SCLK = 25 MHz,

CS
External conversion clock)

No conversion (V
V

= AGND, External reference,

REFM

CS = DVDD)
Normal long sampling (AVDD = 5 V,

CS

= DGND, SCLK = 25 MHz external

conversion clock at V

Internal OSC, 6.5 MHz minute 2.785
Conversion clock is external source,

SCLK = 25 MHz (see Note 1)

Normal long sampling, fixed channel in mode
00 or 01

= AVDD = 5 V,

REFP

REF

= 5 V)

100 MΩ

8.3 12.5 kΩ

200 KSPS

†

100 ppm/°C

1.5 µA

0.4 0.6 mA

2.895

= 4 V ,

REFP

MAX UNIT

µs

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V , external reference (V
V

= 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,

REFM

analog input signal source resistance = 25 Ω (unless otherwise noted) (continued)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

DC Accuracy—Normal Short Sampling

E

L

E

D

E

O

E

(g+)

AC Accuracy—Normal Long Sampling

SINAD Signal-to-noise ratio + distortion

THD Total harmonic distortion

SFDR Spurious free dynamic range

ENOB Effective number of bits

SNR Signal-to-noise ratio

AC Accuracy—Normal Short Sampling

SINAD Signal-to-noise ratio + distortion

THD Total harmonic distortion

SNR Signal-to-noise ratio

ENOB Effective number of bits

SFDR Spurious free dynamic range

†

All typical values are at TA = 25°C.

NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required

Integral linearity error See Note 3 ±0.8 LSB
Differential linearity error ±0.6 LSB
Zero offset error See Note 4 –3 ±0.6 3 LSB
Gain error See Note 4 0 5 12 LSB

fi = 20 kHz 78.6 80.8
fi = 100 kHz
fi = 20 kHz –95 –90
fi = 100 kHz

p

Channel-to-channel isolation (see
Notes 2 and 5)

Analog input bandwidth

Channel-to-channel isolation (see
Notes 2 and 5)

Analog input bandwidth

3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.

4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the

5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the

p

p

p

to overcome the memory effect of the charge redistribution DAC (refer to Figure 8).

difference between 1 1111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the
reference voltage being used.

channel of interest. The converter samples this examined channel continuously . The channel-to-channel isolation is degraded if the
converter samples different channels alternately (refer to Figure 8).

fi = 20 kHz 90 97
fi = 100 kHz
fi = 20 kHz 12.8 13.1
fi = 100 kHz
fi = 20 kHz 79 81
fi = 100 kHz

Fixed channel in conversion mode 00, fi = 35 kHz 100 dB
Full power bandwidth, –1 dB 2

Full power bandwidth, –3 dB

fi = 20 kHz 78.9
fi = 100 kHz
fi = 20 kHz –95
fi = 100 kHz
fi = 20 kHz 79
fi = 100 kHz
fi = 20 kHz 12.8
fi = 100 kHz
fi = 20 kHz 97
fi = 100 kHz

Fixed channel in conversion mode 00, fi = 35 kHz 100 dB
Full power bandwidth, –1 dB 2

Full power bandwidth, –3 dB 2.5

77.6

–88

89

12.6

78

2.5

77.6

–88

78

12.6

89

REFP

= 4V ,

dB

dB

dB

Bits

dB

MHz

dB

dB

dB

Bits

dB

MHz

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC3544, TLC3548

g

Delay time, new SDO valid (reaches 90% of final level) after SCLK rising

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

timing requirements over recommended operating free-air temperature range, A VDD = 5 V, DV
= 5 V, V

SCLK, SDI, SDO, EOC and INT

t

Cycle time of SCLK at 25-pF load

c(1)

t

Pulse width, SCLK high time at 25-pF load 40% 60% t

w(1)

t

Rise time for INT, EOC at 10-pF load

r(1)

t

Fall time for INT, EOC at 10-pF load

f(1)

Setup time, new SDI valid (reaches 90% final level) before falling edge of SCLK, at 25-pF

t

su(1)

load
Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at

t

h(1)

25-pF load
Delay time, new SDO valid (reaches 90% of final level) after SCLK risin

t

d(1)

edge, at 10-pF load
Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF

t

h(2)

load
Delay time, delay from sixteenth SCLK falling edge to EOC falling edge, normal sampling,

td(2)

at 10-pF load
Delay time, delay from the sixteenth falling edge of SCLK to INT falling edge, at 10-pF

t

d(3)

load [see the (‡) double dagger note and Note 6]

†

The minimum pulse width of SCLK high is 12.5 ns. The minimum pulse width of SCLK low is 12.5 ns.

‡

Specified by design

NOTE 6: For normal short sampling, t

= 5 V, V

REFP

For normal long sampling, t
Conversion time, t
SCLK is conversion clock source.

(conv)

= 0 V, SCLK frequency = 25 MHz (unless otherwise noted)

REFM

p

d(3)

d(3)

is equal to 18 × OSC + 15 ns when using internal OSC as conversion clock, or 72 × t

PARAMETERS MIN TYP MAX UNIT

DVDD = 2.7 V 100
DVDD = 5 V

DVDD = 5 V 6
DVDD = 2.7 V
DVDD = 5 V 6
DVDD = 2.7 V

DVDD= 5 V 0 10
DVDD = 2.7 V

is the delay from 16th falling edge of SCLK to INT

is the delay from 48th falling edge of SCLK to the falling edge of INT

falling edge.

†

40

6 – ns

0 – ns

0 23
0 – ns

0 6 ns

t

(conv)

.

t

(conv)

+ 15 ns when external

c(1)

c(1)

10

10

‡

+ 6 µs

DD

ns

ns

ns

ns

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9

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

90%

t

su(1)

50%

10%

t

w(1)

ID15

t

t

h(2)

OD15

1

d(1)

ID1

OD1

t

f(1)

t

c(1)

t

h(1)

16

OD0

t

d(2)

See Note A

t

See Note B

d(3)

Don’t Care

t

r(1)

Hi-Z

OR

CS

SCLK

SDI

SDO

EOC

INT

Don’t Care ID0

Hi-Z

V

IH

V

IL

NOTES: A. For normal long sampling, t

B. For normal long sampling, t

– – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.

Normal sampling mode, CS
SDI) are inactive and are ignored.

Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT

t

f(1)

is the delay time of EOC low after the falling edge of 48th SCLK.

d(2)

is the delay time of INT

d(3)

initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z; all inputs (FS, SCLK,

low after the falling edge of 48th SCLK.

t

r(1)

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC3544, TLC3548

Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V , V

CS trigger

t

Setup time, CS falling edge before SCLK rising edge, at 25-pF load 12 ns

su(2)

t

Delay time, delay time from 16th SCLK falling edge to CS rising edge, at 25-pF load

d(4)

t

Pulse width, CS high time at 25-pF load 1 t

w(2)

Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%

t

d(5)

final level), at 10-pF load

t

Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load 0 6 ns

d(6)

t

Delay time, delay from CS falling edge to INT rising edge, at 10-pF load

d(7)

†

Specified by design

‡

For normal short sampling, td(4) is the delay time from 16th SCLK falling edge to CS
For normal long sampling, td(4) is the delay time from 48th SCLK falling edge to CS

CS

SCLK

REFP

= 5 V , V

t

su(2)

= 0 V , SCLK frequency = 25 MHz (unless otherwise noted) (continued)

REFM

PARAMETERS MIN TYP MAX UNIT

t

116

d(4)

‡

DVDD = 5 V 0 12
DVDD = 2.7 V

p

DVDD = 5 V 0 6
DVDD = 2.7 V 0 16

rising edge.

rising edge.

t

w(2)

5 ns

0 30

†

†

c(1)

ns

ns

V

IH

V

IL

SDI

SDO

EOC

OR

INT

NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.

Normal sampling mode, CS
SDI) are inactive and are ignored. Parts with date code earlier than 13XXXXX have these discrepancies:
(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,
in this case, is 2001 and the month of March.)
FS is not ignored even if the device is in microcontroller mode (CS
FS must be tied to DVDD.

Don’t Care ID0

t

d(5)

Hi-Z Hi-Z

ID15

ID1

OD1

OD15

initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,

OD0

Don’t Care

triggered).

t

Don’t Care

d(7)

Figure 2. Critical Timing for CS Trigger

t

d(6)

Hi-Z

OD7OD15

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11

TLC3544, TLC3548

Delay time, delay from FS rising edge to MSB of SDO valid

Delay time, delay from FS rising edge to INT rising edge at

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V , V

FS trigger

t

Delay time, delay from CS falling edge to FS rising edge, at 25-pF load 0.5 t

d(8)

t

Setup time, FS rising edge before SCLK falling edge, at 25-pF load 0.25×t

su(3)

t

Pulse width, FS high at 25-pF load 0.75×t

w(3)

Delay time, delay from FS rising edge to MSB of SDO valid

t

d(9)

(reaches 90% final level) at 10-pF load

t

Delay time, delay from FS rising edge to next FS rising edge at 25-pF load

d(10)

Delay time, delay from FS rising edge to INT rising edge at

t

d(11)

10-pF load

†

Specified by design

REFP

= 5 V , V

= 0 V , SCLK frequency = 25 MHz (unless otherwise noted) (continued)

REFM

PARAMETERS MIN TYP MAX UNIT

t

c(1)

0.5×t

c(1)
c(1)

DVDD = 5 V 26
DVDD = 2.7 V

Required
sampling time +
conversion time

DVDD = 5 V 0 6
DVDD = 2.7 V 16

c(1)

1.25×t

+5 ns

c(1)

†
†

30

†
†

c(1)

ns

ns

µs

ns

t

ID1

OD1

d(10)

16

ID0Don’t Care ID15

OD0

can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK, SDI)

instead of FS rising edge in DSP mode (FS triggered).

Don’t Care Don’t Care

Hi-Z

t

d(11)

OD15

CS

t

su(3)

OD15

t

w(3)

1

ID15

t

d(8)

FS

SCLK

SDI

t

d(9)

SDO

EOC

OR

INT

NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.

Normal sampling mode, FS initiates the conversion, CS
are inactive and are ignored.
Parts with date code earlier than 13XXXXX have these discrepancies:
(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,
in this case, is 2001 and the month of March.)
SDO MSB (OD[15]) comes out from the falling edge of CS

Hi-Z

V

OH

V

OH

Figure 3. Critical Timing for FS Trigger

Don’t Care

V

IH

V

IL

12

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