Texas Instruments TLC320AD75CDL Datasheet

TLC320AD75C

Data Manual

20-Bit Sigma-Delta Stereo ADA Circuit

SLAS144

February 1997

Printed on Recycled Paper

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Copyright  1997, Texas Instruments Incorporated

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 System Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Functions 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Detailed Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Power-Down and Reset Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 ADC Power Down 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Reset Function for ADC 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Reset/Initialization for DAC 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Differential Input to the ADC 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Sigma-Delta Modulator for the ADC 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Decimation Filter 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 High-Pass Filter 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Master Clock 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 Master-Clock Circuit for ADC 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 Master-Clock Circuit for DAC 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 T est 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Master Mode for ADC 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Slave Mode for ADC 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Digital-Audio-Data Interface for DAC 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Serial-Control Interface for DAC 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.1 Serial-Control-Data Input 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 DAC De-emphasis Filter 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 Digital Filter Mute for DAC 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14 DAC Digital Attenuation/Soft Mute 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15 Sigma-Delta DAC Modulator 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16 DAC Interpolation Filter 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.17 DAC PWM Output (L2–L1 and R2–R1) 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.18 DAC Control Register Set 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.19 Auto-Resynchronization Functionality 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 3–1. . . . .

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics, AV
PV

= XVDD = 5 V, V

DDR

= LVDD = V

DD

= V

35A

= V

DD1

= 3.3 V, TA = 25°C 3–2. . . . . . . . . . . . . . . . . .

35D

DD2

= PV

DDL

=

3.3.1 Digital Interface 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 Analog Interface 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 ADC Performance, f

3.3.4 DAC Performance, 20-Bit Mode, f

= 44.1 kHz, Bandwidth = 22.05 kHz 3–3. . . . . . . . . .

s

= 44.1 kHz,

s

Bandwidth = 22.05 kHz 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

Contents (Continued)

Section Title Page

3.3.5 ADC Inputs 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.6 ADC High-Pass Filter, f

3.3.7 ADC Decimation Filter, f

3.3.8 DAC Filter Characteristics, f

3.3.9 Power Supply Current, f

3.4 ADC Switching Characteristics 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 DAC Timing Requirements 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Parameter Measurement Information 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Information 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Circuit And Layout Considerations 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 PCB Footprint 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A Mechanical Data A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

= 44.1 kHz 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

s

= 44.1 kHz 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

s

= 44.1 kHz 3–4. . . . . . . . . . . . . . . . . . . . . . . . .

s

= 44.1 kHz 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

s

iv

List of Illustrations

Figure Title Page

Figure 2–1 ADC Start-Up Timing 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–2 DAC-Reset Timing Relationships 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–3 Differential Analog-Input Configuration 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–4 ADC Audio-Data Serial Timing – Master Mode 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–5 ADC Audio-Data Serial Timing – Slave Mode 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–6 Audio Data Serial Timing – ADC and All DAC Modes 2–6. . . . . . . . . . . . . . . . . . . . .

Figure 2–7 Control-Data Input Timing 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–8 De-emphasis Filter Characteristics 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–9 Digital Attenuation Characteristics 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2–10 DAC Digital Attenuation Operation With T apered Gain Response 2–8. . . . . . . . .

Figure 2–11 Oversampling Noise Power With and Without Noise Shaping 2–9. . . . . . . . . . . . .

Figure 4–1 ADC Audio-Data Serial Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4–2 DAC Control-Data Serial Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 5–1 TLC320AD75C Application Schematic 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 5–2 A-Weighted Function 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 5–3 Land Pattern for PCB Layout 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

Table 2–1 ADC Master Clock to Sample-Rate Comparison 2–4. . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2–2 DAC Master Clock to Sample-Rate Comparison 2–4. . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2–3 Attenuation Mode Register 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2–4 System Mode Register 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 5–1 TLC320AD75C Schematic Components 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 5–2 A-Weighted Data 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

vi

1 Introduction

The TLC320AD75C is a high-performance stereo 20-bit analog-to-digital and digital-to-analog converter
(ADA) using sigma-delta technology to provide four concurrent 20-bit resolution conversions from both
analog-to-digital (A/D) and digital-to-analog (D/A) signal paths. Additional functions provided are digital
attenuation, digital de-emphasis filtering, soft mute, and on-chip timing and control. Control words from a
host controller or processor are used to implement these functions.

The TLC320AD75C is characterized for operation from 0°C to 70°C.

1.1 Features

• Single 5-V (Analog/Digital) Power Level and 3.3-V to 5-V Digital Interface Level

• Sample Rates up to 48 kHz

• 20-Bit Resolution Conversions

• Signal-to-Noise Ratio (EIAJ) of 100 dB for the ADC

• Total Harmonic Distortion + Noise of 0.0017% for the ADC

• Signal-to-Noise Ratio (EIAJ) of 104 dB for the DAC

• Total Harmonic Distortion + Noise of 0.0013% for the DAC

• Internal Voltage Reference (V

• Serial Port Interface

• Differential Architecture

• DAC Provides PWM Output

ref

)

• Digital De-emphasis Filtering for 32-, 44.1-, and 48-kHz Sample Rates for the DAC

• Digital Attenuation/Soft Mute Function for the DAC

• Small 56-Pin DL Plastic Small-Outline Package

1–1

1.2 Functional Block Diagram

INLP

INLM

REFO

REFI

INRP

INRM

L1
L2

R1
R2

VREF

PWM

PWM

Sigma-Delta

Modulator

Sigma-Delta

Modulator

Digital

Modulator

Digital

Modulator

Stereo ADC

Decimation

Filter

Decimation

Filter

Stereo DAC

Interpolation

Filter

De-emphasis

Filter

De-emphasis

Filter

Interpolation

Filter

High-Pass

Filter

High-Pass

Filter

Digital

Attenuator

Digital

Attenuator

3 V or 5 V

V

Serial

Interface

Serial

Interface

35A

ADOUT
SCLKA

LRCKA

MCLKI

256CK
512CK

XOUT
XIN

LRCKD
SCLKD

DDATA

1–2

CDIN

SHIFT

LATCH

CPU

Interface

V

3 V or 5 V

35D

1.3 System Block Diagram

Right

Audio Input

Left

Audio Input

Single to

Differential

Single to

Differential

TLC320AD75C

INRP

ADC

Serial Port

INRM

INLP

INRM

LRCKA
SCLKA

ADOUT

REFI

REFO

M_S

MCLKI

256CK

XIN

AV

SS

ADC Data Out

V

SS1

XV

SS

Audio Output

Right

Left

Audio Output

Analog

Low-Pass Filter

Analog

Low-Pass Filter

R1
R2

L1
L2

XOUT

512CK

DAC

Serial Ports

LRCKD

SCLKD
DDATA

CDIN

SHIFT

LATCH

Microcontroller/
Microprocessor

XV

SCLK
LRCK

DAC Data In

DAC
Control Data

SS

1–3

1.4 Terminal Assignments

DL PACKAGE

(TOP VIEW)

INRP

INRM

REFI

AV

DD

AV

SS

APD

NU
NU

TEST1
LRCKA
SCLKA

ADOUT

V

35A

V

SS1B

MCLKI

DPD

V

SS2B

INIT

CDIN

SHIFT

LATCH

256CK

V

35D

V

SS2

512CK
SCLKD

DDATA

LRCKD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

INLP
INLM
REFO
LV

SS

LV

DD

AV

SSB

NU
NU
V

SS1B

M_S
TEST2
V

SS1

V

DD1

V

DD1

V

DD2

L1
PV

DDL

L2
PV

SSL

XV

SS

XIN
XOUT
XV

DD

PV

SSR

R2
PV

DDR

R1
V

DD2

1.5 Ordering Information

1–4

PACKAGE

T

A SMALL OUTLINE

0°C to 70°C TLC320AD75CDL

(DL)

1.6 Terminal Functions

I/O

DESCRIPTION

TERMINAL

NAME NO.

20-bit ADC data output. ADOUT provides the MSB first in 2’s-complement data format

ADOUT 12 O

APD 6 I

AV

DD

AV

SS

AV

SSB

CDIN 19 I

DDATA 27 I

DPD 16 I

INIT 18 I

INLM 55 I Inverting input for the left channel analog modulator
INLP 56 I Noninverting input for the left channel analog modulator
INRM 2 I Inverting input for the right channel analog modulator
INRP 1 I Noninverting input for the right channel analog modulator

LATCH 21 I

LRCKA 10 I/O

LRCKD 28 I

LV

DD

LV

SS

L1 41 O Left channel DAC PWM output 1
L2 39 O Left channel DAC PWM output 2

MCLKI 15 I

4 Analog power supply voltage for ADC modulators
5 Analog ground for ADC modulators

51 Analog substrate ground for ADC modulators

52

53

and is left justified within the 32-bit packet for each channel. The output level is 3.3 V
for V

Analog power-down mode. APD disables the ADC analog modulators. The ADC
single-bit modulator outputs become invalid, rendering the outputs of the digital filters
invalid. When APD

Attenuation mode and system control mode input for DAC. CDIN is a 24-bit stream
with a 16-bit data word followed by an 8-bit device address. This stream is configured
with the MSB first (see Section 2.15,

DAC input data in 2’s-complement data format. MSB/LSB first and 20-bit/16-bit input
formats are selectable by using the DAC control registers (see Section 2.15,

Sigma-Delta DAC Modulator

Digital power-down mode. The DPD shuts down the ADC digital decimation filters and
clock generators, and provides a digital reset. All digital outputs of the ADC function,
are brought to unasserted states. When DPD
device is resumed. When in slave mode operation, after the rising edge of DPD
ADC system is synchronized.

Initial DAC reset signal. The DAC device is activated on the rising edge of INIT . When
INIT

Latch signal for the DAC control serial data. Attenuation/system-control data loads
into the internal registers when LATCH

Left/right clock for ADC. LRCKA signifies whether the serial data is associated with
the left channel ADC (when LRCKA is high) or the right channel ADC (when LRCKA
is low). LRCKA is normally connected to LRCKD. LRCKA is output when configured
in master mode.

Left/right clock for DAC. LRCKD signifies whether the serial data is associated with
the left channel DAC (when LRCKD is high) or the right channel DAC (when LRCKD
is low). LRCKD is normally connected to LRCKA.

Digital power supply for analog modulators. LVDD is normally connected to AV
through a 50-Ω resistor.

Digital ground for analog modulators. L VSS is normally connected to AVSS through a
50-Ω resistor.

Master clock input for ADC. MCLKI operates at 256 times the sample rate (i.e. 256
times LRCKA). MCLKI is normally connected to 256CK through a 50-Ω resistor.

= 3.3 V (see Figure 2–6).

35A

is pulled high, normal operation of the device is resumed.

Sigma-Delta DAC Modulator

).

is pulled high, normal operation of the

is brought low, the DAC is reset when LRCKD is present.

is brought low.

).

, the

DD

1–5

Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

M_S

NU
PV

DDL

PV

DDR

PV

SSL

PV

SSR

REFI 3 I
REFO 54 O Internal ADC reference voltage (normally connected to REFI).

R1 30 O Right channel DAC PWM output 1
R2 32 O Right channel DAC PWM output 2

SCLKA 11 I/O

SCLKD 26 I

SHIFT 20 I
TEST1 9 I Factory test terminal1. TEST1 should be connected to V

TEST2 46 I Factory test terminal2. TEST2 should be connected to V
XIN 36 I
XOUT 35 O Oscillator output terminal for 512 times the DAC sample rate

V

DD1

V

DD2

V

SS1

V

SS1B

V

SS2

V

SS2B

V

35A

V

35D

XV

DD

XV

SS

256CK 22 O

512CK 25 O

47

7, 8,

49, 50

40 PWM power supply for left channel DAC
31 PWM power supply for right channel DAC
38 PWM ground for left channel DAC
33 PWM ground for right channel DAC

43, 44 Digital power supply for ADC
29, 42 Digital power supply voltage for DAC

45 Digital ground for ADC digital flters

14, 48 Digital substrate ground for ADC

24 Digital ground for the DAC
17 Digital sustrate ground for DAC
13 Digital power supply for ADC interface logic. V
23 Digital power supply for DAC interface logic. V
34 Oscillator power-supply voltage for DAC
37 Oscillator circuit ground for DAC

Master/slave selection. The ADC serial port is configured as master mode when M_S

I

is pulled high. M_S is connected to V

– Not used

Input reference voltage. REFI provides reference voltage for the ADC modulator
(normally connected to REFO).

Shift clock for the ADC. The shift clock clocks serial data out of the ADC, and operates
at 64 times the sample rate (i.e. 64 times LRCKA). SCLKA is normally connected to
SCLKD. SCLKA is output when configured in master mode.

Shift clock for the DAC. The shift clock clocks serial audio data into the DAC, and
operates at 64 times the sample rate (i.e. 64 times LRCKD). SCLKD is normally
connected to SCLKA.

Shift data. SHIFT clocks the control data (CDIN) into the internal control registers for
the DAC.

Oscillator input terminal for 512 times the DAC sample rate. XIN derives all of the key
logic signals of the DAC device. (XIN can also be driven by an external oscillator.)

256 times sample rate clock output. 256CK is normally connected to MCLKI through
a 50-Ω resistor. 256CK is the XIN frequency divided by two.

512 times sample rate clock output (output level is 3.3 V for V
a buffered version of XIN (master clock input).

for slave mode.

SS1

35A
35D

SS1
SS1

is connected to 3 V or 5 V.
is connected to 3 V or 5 V.

for normal operation.
for normal operation.

= 3.3 V). 512CK is

35D

1–6

2 Detailed Description

The sigma-delta ADC converter consists of an oversampling analog modulator and digital decimation filter.
The sigma-delta DAC incorporates an interpolation finite impulse-response (FIR) filter and oversampled

modulator. The pulse-width-modulation (PWM) digital output feeds an external low-pass filter to recover the
analog audio signal.

Two control registers configure the DAC. The attenuation register controls the attenuation range,
de-emphasis enable, and mute selection. The system register controls the data format and de-emphasis
filter-sample rate.

2.1 Power-Down and Reset Functions

2.1.1 ADC Power Down

The power-down state is comprised of a separate digital and analog power down for the ADC. The power
consumption of each is detailed in the electrical characteristics section.

The digital power-down mode shuts down the digital filters and clock generators. When the digital
power-down terminal is pulled high, normal operation of the device is initiated. In slave mode, the conversion
process must synchronize to an input on LRCKA as well as SCLKA. Therefore, the conversion process is
not initiated until the first rising edges of both SCLKA and LRCKA are detected after DPD is pulled high. This
synchronizes the conversion cycle; all conversions are performed at a fixed LRCKA rate after the initial
synchronization. After DPD
cycles which consists of group delays of the decimation and high-pass filter.

The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid, which renders the outputs of the digital filters invalid. When the APD
modulators are brought back online; however, the settling time of the modulator stage is normally 100 ms.

is brought high, the output of the digital filters remains invalid for 26 LRCKA

terminal is brought high, the

2.1.2 Reset Function for ADC

The conversion process is not initiated until the first rising edges of both SCLKA and LRCKA are detected
after DPD
LRCKA rate after the initial synchronization.

is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed

2–1