Texas Instruments TLC320AD56CPT, TLC320AD56CFNR, TLC320AD56CFN Datasheet

TLC320AD56C

Data Manual

Sigma-Delta Analog Interface Circuit

SLAS101A

September 1996

Printed on Recycled Paper

IMPORTANT NOTICE

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Copyright  1996, Texas Instruments Incorporated

iii

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Definitions and Terminology 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Register Functional Summary 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Device Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Operating Frequencies 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 ADC Signal Channel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 DAC Signal Channel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Serial Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 Register Programming 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 Sigma-Delta ADC 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 Decimation Filter 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 Sigma-Delta DAC 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.9 Interpolation Filter 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.10 Digital Loopback 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.11 FIR Overflow Flag 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Terminal Functions 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Reset and Power-Down Functions 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Master Clock Circuit 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Data Out (DOUT) 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Data In (DIN) 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5 Hardware Program Terminal (FC) 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.6 Frame-Sync Function 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7 Multiplexed Analog Input 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8 Analog Input 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.9 Analog Output 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Serial Communications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Primary Serial Communication 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Secondary Serial Communication 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Conversion Rate vs Serial Port 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Phone Mode Control 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Specifications 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Absolute Maximum Ratings Over Operating

Free-Air Temperature Range 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Recommended Operating Conditions 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Recommended Operating Conditions, DV

DD

= 5 V, AVDD = 5 V 4–1. . . . .

4.2.2 Recommended Operating Conditions, DV

DD

= 3 V, AVDD = 5 V 4–1. . . . .

iv

Contents (Continued)

Section Title Page

4.3 Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, DV

DD

= 5 V, AVDD = 5 V 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Digital Inputs and Outputs, MCLK = 4.096 MHz,

f

s

= 8 kHz, Outputs Not Loaded 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 Digital Inputs and Outputs, MCLK = 4.096 MHz,

f

s

= 8 kHz, Outputs Not Loaded, DVDD = 3 V 4–2. . . . . . . . . . . . . . . . . . . . .

4.3.3 ADC Path Filter, MCLK = 4.096 MHz, f

s

= 8 kHz 4–2. . . . . . . . . . . . . . . . . .

4.3.4 ADC Dynamic Performance, MCLK = 4.096 MHz, f

s

= 8 kHz 4–2. . . . . . . .

4.3.5 ADC Channel 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.6 DAC Path Filter, MCLK = 8.192 MHz, f

s

= 8 kHz 4–4. . . . . . . . . . . . . . . . . .

4.3.7 DAC Dynamic Performance, DV

DD

= 5 V or 3 V 4–5. . . . . . . . . . . . . . . . . . .

4.3.8 DAC Channel, DV

DD

= 5 V or 3 V 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.9 Power Supplies, No Load 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.10 Power-Supply Rejection 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.11 Timing Requirements 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Information 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A Register Set A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B Mechanical Data B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Illustrations

Figure Title Page

1–1. Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2. Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3. Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1. Internal Power-Down Logic 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2. Differential Analog-Input Configuration 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1. Primary Serial Communication Timing 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2. Hardware and Software Ways to Make a Secondary Request 3–3. . . . . . . . . . . . . . . . . . .

3–3. Hardware FC Secondary Request

(Phone Mode Disabled) 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4. Software FC Secondary Request (Phone Mode Disabled) 3–5. . . . . . . . . . . . . . . . . . . . . .

3–5. Phone Mode Timing 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6. Secondary DIN Format 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1. ADC Decimation Filter Response 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2. ADC Decimation Filter Passband Ripple 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3. DAC Interpolation Filter Response 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4. DAC Interpolation Passband Ripple 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1. Application Schematic For Single-Ended Input/Output 5–1. . . . . . . . . . . . . . . . . . . . . . . . . .

5–2. Application Schematic For Differential Input/Output 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

3–1. Secondary Request Format 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2. Least Significant Bit Control Function 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3. Secondary Communication Data Format 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1–1

1 Introduction

The TLC320AD56C provides high resolution low-speed signal conversion from digital-to-analog (D/A) and
from analog-to-digital (A/D) using oversampling sigma-delta technology . This device consists of two serial
synchronous conversion paths (one for each data direction) and includes an interpolation filter before the
digital-to-analog converter (DAC) and a decimation filter after the analog-digital-converter (ADC) (see
Figure 1–1). Other overhead functions provide on-chip timing and control. The sigma-delta architecture
produces high resolution A/D and D/A conversion at low system speeds and low cost.

The options and the circuit configurations of this device can be programmed through the serial interface.
The options include reset, power-down, communications protocol, serial clock rate, and test mode as
outlined in Appendix A. The TLC320AD56C is characterized for operation from 0°C to 70°C.

1.1 Features

The TLC320AD56C includes the following features:

• Single 5-V power supply voltage or 5 V analog and 3 V digital supply voltages

• Power dissipation (P

D

) of 150 mW maximum in the operating mode

• Power-down mode to 2.5 mW typical

• General-purpose 16-bit signal processing

• 2’s-complement data format

• Typical dynamic range of 85 dB for the DAC and 87 dB for the ADC

• Minimum 79-dB total signal-to-(noise + distortion) for the ADC

• Minimum 80-dB total signal-to-(noise + distortion) for the DAC

• Differential architecture throughout the device

• Internal reference voltage (V

ref

)

• Internal 64X oversampling

• Serial port interface

• Phone-mode output control

• System test mode, digital loopback test mode

• Capable of supporting all V.34 sample rates by varying MCLK frequency

• Supports business audio applications

• Variable conversion rate selected as MCLK/512

1–2

1.2 Functional Block Diagram

INM

INP

Sigma-

Delta

ADC

Decimation Filter

Buffer

Digital

Loopback

AUXP

AUXM

V

ref

DOUT (2’s­complement)

OUTP

OUTM

Sigma-

Delta

DAC

Interpolation Filter

Buffer

DIN (2’s­complement)

I/O
Control

MCLK

÷8

SCLK

MUX

V

ref

SINC
Filter

FIR

Filter

FILT

fclk

IGAIN

MONOUT

FLAG 0
FLAG 1
ALT DATA

÷4

FC
FS

Figure 1–1. Functional Block Diagram

1–3

1.3 Terminal Assignments

321

13 14

5
6
7
8
9

10

11

INM
INP
AV

DD

VSS

(SUB)

AV

SS

DV

SS

ALT DATA

PWRDWN

RESET

DV

DD

DIN

4

15 16 17 18

FS

SCLK

MCLK

FC

FLAG 0

FLAG 1

NC

IGAIN

FN PACKAGE

(TOP VIEW)

28 27 26

25
24
23
22
21
20
19

12

DOUT

MONOUT

AUXP

AUXM

V

COM(ADC)

FIL T

OUTP

OUTM

V

COM(DAC)

NC – No internal connection

Figure 1–2. Terminal Assignments

1–4

14 15

INM
INP
NC
AV

DD

NC
NC
V

SS(SUB)

NC
AV

SS

NC
DV

SS

ALT DATA

36
35
34
33
32
31
30
29
28
27
26
25

16

1
2
3
4
5
6
7
8
9
10
11
12

OUTP

OUTM

NC

17 18 19 20

PT PACKAGE

(TOP VIEW)

NC

MONOUT

AUXP

AUXM

47 46 45 44 4348 42

NC

FIL T

IGAIN

NC

NC

FLAG0

FLAG1

NC

MCLK

NC

NC

NC

FC

40 39 3841

21

22 23 24

37

13

NC

NC

FS

SCLK

NC

NC

NC – No internal connection

V

COM(ADC)

V

COM(DAC)

NC

PWRDWN

RESET

NC

DV

DD

DIN

NC

DOUT

Figure 1–3. Terminal Assignments

1.4 Ordering Information

PACKAGE

T

A

CHIP CARRIER

(FN)

QUAD FLAT PACK

(PT)

0°C to 70°C TLC320AD56CFN TLC320AD56CPT

1–5

1.5 Terminal Functions

TERMINALS

NUMBER

I/O DESCRIPTION

NAME

PT FN

ALT DATA 25 19 I

Signals on this terminal are routed to DOUT during secondary communication
if phone mode is enabled.

AUXM 38 26 I

Inverting input to auxiliary analog input. AUXM requires an external RC antialias
filter.

AUXP 39 27 I

Noninverting input to auxiliary analog input. Requires an external RC antialias
filter.

AV

DD

33 23 I Analog ADC path supply (5 V only)

DIN 10 11 I

Data input. DIN receives the DAC input data and command information from the
DSP and is synchronized to SCLK.

DOUT 12 12 O

Data output. DOUT transmits the ADC output bits and is synchronized to SCLK.
This terminal is at high-Z when FS

is not activated.

DV

DD

9 10 I Digital power supply (5 V or 3 V)

DV

SS

26 20 I Digital ground

FC 21 16 I

Function code. FC is sampled and latched on the rising edge of FS for the primary
serial communication. Refer to the Serial Communications section for more
details.

FLAG 0 23 17 O

Output flag 0. During phone mode, FLAG 0 contains the value set in Control 2
register.

FLAG 1 24 18 O

Output flag 1. During phone mode, FLAG 1 contains the value set in Control 2
register.

FILT 47 3 O

Bandgap filter. FILT is provided for decoupling of the bandgap reference, and
provides 2.5 V to which the analog inputs or outputs can be referenced. The
optimal capacitor value is 0.1 µF (ceramic). This voltage node should be loaded
only with a high-impedance dc load.

FS 13 13 O

Frame sync. When FS goes low, the serial communication port is activated. In
all serial transmission modes, FS

is held low during bit transmission. Refer to

section 3

Serial Communications

for detailed description.

INM 36 25 I Inverting input to analog modulator. INM requires an external RC antialias filter.
INP 35 24 I

Noninverting input to analog modulator. INP requires an external RC antialias
filter.

IGAIN 45 1 O

Current gain reference scaling. IGAIN is provided for decoupling of the current
gain reference and provides a 1.35-V reference. The optimal load is a
27-K resistor.

MCLK 17 15 I

Master clock. The master clock derives the internal clocks of the sigma-delta
analog interface circuit.

MONOUT 40 28 O

Monitor output. MONOUT allows for monitoring of the analog input and is a
high-impedance output. The gain or mute is selected using Control 2 register .

OUTM 2 6 O

Inverting current output of the DAC. OUTM is functionally identical with and
complementary to OUTP. OUTM and OUTP current outputs can be loaded with
5 kΩ differentially or single-ended. This signal can also be used alone for
single-ended operation.

NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.

1–6

1.5 Terminal Functions (Continued)

TERMINALS

NUMBER

I/O DESCRIPTION

NAME

PT FN

OUTP 1 5 O

Noninverting current output of the DAC. OUTM and OUTP current outputs can
be loaded with 5 kΩ differentially or single ended. This signal can also be used
alone for single-ended operation.

PWRDWN 6 8 I Power down. When this terminal is pulled low, the device goes into a power-down

mode; the serial interface is disabled and most of the high-speed clocks are
disabled. However, all the register values are sustained and the device resumes
full power operation without reinitialization when this terminal is pulled high
again. PWRDWN

resets the counters only and preserves the programmed

register contents. See subsection 2.21.

Reset and Power-Down Functions.

RESET 7 9 I Reset. The reset function is provided to initialize all the internal registers to their

default values. The serial port can be configured to the default state accordingly .
Refer to section 1.7

Register Functional Summary

and subsection 2.2.1

Reset

and Power-Down Functions

for more detailed descriptions.

SCLK 16 14 O Shift clock. The shift clock signal is derived from MCLK and is used to clock serial

data into DIN and out of DOUT.

V

SS(SUB)

30 22 I Analog substrate. This terminal must be grounded.

V

COM(ADC)

46 2 O Common mode filter. This terminal is provided for decoupling of the common

mode reference and provides a 2.5 V reference. The optimal capacitor value is

0.10 µF. This node should be loaded only with a high-impedance dc load.

V

COM(DAC)

4 7 O Common mode filter. This terminal is provided for decoupling of the common

mode reference and provides a 2.5 V reference. The optimal capacitor value is

0.10 µF. This node should be loaded only with a high-impedance dc load.

AV

SS

28 21 I Analog ground

NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.

1.6 Definitions and Terminology

Data Transfer Interval This is time during which data is transferred from DOUT and to DIN. This interval

is 16 shift clocks and this data transfer is initiated by the falling edge of the
frame-sync signal.

Signal Data This refers to the input signal and all of the converted representations through the

ADC channel and return through the DAC channel to the analog output. This is
contrasted with the purely digital software control data.

Primary
Communications This refers to the digital data transfer interval. Since the device is synchronous, the

signal data words from the ADC channel and to the DAC channel occur
simultaneously.

Secondary
Communications This refers to the digital control and configuration data transfer interval into DIN and

the register read data cycle from DOUT. The data transfer interval occurs when
requested by hardware or software.

Frame Sync Frame sync refers only to the falling edge of the signal that initiates the data transfer

interval. The primary frame sync starts the primary communications, and the
secondary frame sync starts the secondary communications.

1–7

Frame Sync and
Sampling Period The time between the falling edges of successive primary frame-sync signals.

f

s

The sampling frequency that is the reciprocal of the sampling period.

Frame-Sync Interval The time period occupied by 16 shift clocks. It goes high on the sixteenth rising

edge of SCLK after the falling edge of the frame sync.

ADC Channel This term refers to all signal processing circuits between the analog input and the

digital conversion results at DOUT.

DAC Channel This term refers to all signal processing circuits between the digital data word

applied to DIN and the differential output analog signal available at OUTP and
OUTM.

Host Any processing system that interfaces to DIN, DOUT, SCLK, or FS

.
Dxx Bit position in the primary data word (xx is the bit number).
DSxx Bit position in the secondary data word (xx is the bit number).
d The alpha character d represents valid programmed or default data in the control

register format (see section 3.2

Secondary Serial Communications

) when

discussing other data bit portions of the register.

X The alpha character X represents a do-not-care bit position within the control

register format.

FIR Finite duration impulse response.

1.7 Register Functional Summary

There are three data and control registers that are used as follows:
Register 0 The No-Op register. The 0 address allows secondary requests without altering any other

register.

Register 1 The Control 1 register. The data in this register controls:

• The software reset

• The software power down

• Selection of the normal or auxiliary analog inputs

• Selection of the digital loopback

• 16-bit or 15-bit mode of operation

• Selection of monitor amp output

Register 2 The Control 2 register. The data in this register:

• Contains the output flag indicating a decimator FIR filter overflow

• Contains Flag 0 and Flag 1 output values for use in the phone mode

• Selects the phone mode