Texas Instruments TLC320AD545-EVM, TLC320AD545PTR, TLC320AD545PT, TLC320AD545IPT Datasheet

TLC320A545C/I

Single Channel Data/Fax Codec

1999 Mixed Signal Products

Data Manual

SLAS206B

2

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated

iii

Contents

Section Title Page

Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Analog Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Functions 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Device Requirements and System Overview 2–1. . . . . . . . . . . . . . . . . . . .

2.2 Codec Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Hybrid Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Miscellaneous Logic and Other Circuitry 2–1. . . . . . . . . . . . . . . . . . . . . . . .

3 Codec Functional Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Operating Frequencies 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 ADC Signal Channel 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 DAC Signal Channel 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Sigma-Delta ADC 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Decimation Filter 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Sigma-Delta DAC 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Interpolation Filter 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Analog and Digital Loopbacks 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 Software Power Down 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 Test Module 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 Power Supply Options 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Serial Communications 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Primary Serial Communication 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 FS Low Mode Primary Communication Timing 4–2. . . . . . . . . . . . . . . . . .

4.3 Secondary Serial Communication 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 FS High Mode Secondary Communication Timing 4–4. . . . . . . . . . . . . . .

4.5 FS Low Mode Secondary Communication Timing 4–4. . . . . . . . . . . . . . . .

5 Specifications 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Absolute Maximum Ratings Over Operating Free-Air

Temperature Range 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Recommended Operating Conditions 5–1. . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range DV

DD

= 5 V/3.3 V, AVDD = 5 V/3.3 V,

MV

DD

= 5 V/3.3 V 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.1 Digital Inputs and Outputs, f

s

= 8 kHz,

Outputs Not Loaded 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

5.3.2 ADC Channel, fs = 8 kHz 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.3 ADC Dynamic Performance, f

s

= 8 kHz 5–2. . . . . . . . . . . . . . . .

5.3.3.1 ADC Signal-to-Noise 5–2. . . . . . . . . . . . . . . . . . . . .

5.3.3.2 ADC Signal-to-Distortion 5–2. . . . . . . . . . . . . . . . . .

5.3.3.3 ADC Signal-to-Distortion + Noise 5–3. . . . . . . . . .

5.3.4 ADC Characteristics 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.5 DAC Channel, f

s

= 8 kHz 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.6 DAC Dynamic Performance 5–3. . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.6.1 DAC Signal-to-Noise 5–3. . . . . . . . . . . . . . . . . . . . .

5.3.6.2 DAC Signal-to-Distortion 5–3. . . . . . . . . . . . . . . . . .

5.3.6.3 DAC Signal-to-Distortion + Noise 5–4. . . . . . . . . .

5.3.7 DAC Characteristics 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.8 Logic DC Electrical Characteristics 5–4. . . . . . . . . . . . . . . . . . . .

5.3.9 Power-Supply Rejection 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.10 Power-Supply 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.11 Flash Write Enable Circuit 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Timing Characteristics 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 Timing Requirements 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.2 Switching Characteristics 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Parameter Measurement Information 5–5. . . . . . . . . . . . . . . . . . . . . . . . . .

6 Application Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A – Programmable Register Set A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Illustrations

Figure Title Page

4–1 Primary Communication DIN and DOUT Data Format 4–1. . . . . . . . . . . . . . . . .

4–2 FS High Mode Primary Serial Communication Timing 4–2. . . . . . . . . . . . . . . . . .

4–3 FS Low Mode Primary Serial Communication Timing 4–2. . . . . . . . . . . . . . . . . .

4–4 Secondary Communication DIN and DOUT Data Format 4–3. . . . . . . . . . . . . . .

4–5 FS Output During Software Secondary Serial Communication Request

(FS High Mode) 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 FS Output During Software Secondary Serial Communication Request

(FS Low Mode) 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 Serial Communication Timing 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 ADC Decimation Filter Response 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 ADC Decimation Filter Passband Ripple 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 DAC Interpolation Filter Response 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 DAC Interpolation Filter Passband Ripple 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Functional Block of a Typical Application 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Differential Configuration Typical Application 6–2. . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Single-Ended Configuration Typical Application 6–3. . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

4–1 Least-Significant-Bit Control Function 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1–1

Introduction

The TLC320AD545 single channel data/fax codec is a mixed signal broadband connectivity device. The
TLC320AD545 is comprised of a single channel codec and analog hybrid circuitry with a serial port for communication
with the host processor. The device also contains programmable gain control and one AT41 speaker driver. The
device operates with either a 5-V analog, a 5-V digital, and a 5-V monitor power supply or a 3.3-V analog, a 3.3-V
digital, and a 3.3-V monitor power supply or 5-V analog, 3.3-V digital, and a 5-V monitor power supply . The device
will be packaged in a single 48-pin PT (TQFP) package.

1.1 Features

• Analog, Digital, and Monitor Amp Power Supplies: 5 V or 3.3 V

• Differential and Single-Ended Driving of Analog Output

• Software Power-Down Mode

• Sample Rate Up to 11.025 kHz

• 16-Bit Signal Processing in the Codec With 2s-Complement Data Format

• Typical 80-db Dynamic Range

• Total Signal-to-Noise + Distortion of 80 dB for the ADCs

• Total Signal-to-Noise + Distortion of 78 dB for the DACs

• Programmable Gain Amplifier

• 600-Ω Driver

• 8-Ω AT41 Differential Speaker Driver With Programmable Gain Amplifier

• Flash Write Enable Circuit Provide Power for Writing the Flash Memory Device

• Available in 48-Pin PT (TQFP) Package Operating From –40_C to 85_C

• Transformer Reference ( 2.5 mA Source and Sink at 2.5 V for 5 V -Supply and 1.5 V for 3.3-V Supply) to allow

Single-Ended Driving

1.2 Functional Block Diagram

1–2

Data

Channel

Serial

Port

Data Channel

Codec

H
Y
B
R

I

D

A
M
P

DRVR

Flash
Write

Enable

Control

Logic

1.3 Analog Block Diagram

+

–

DTRX_FB

DTRXM

DTRXP

+

–

16-Bit
ADC

Data (Hybrid)

2.5 V

Data_In PGA
0/6/12/18 dB Gain
with Mute

+

–

Data (Hybrid)

DTTX_OUTP

DT_REF

DTTX_INM

2.5 V/1.5 V

+

–

2.5 V/1.5 V

16-Bit
DAC

DT_BUFP

+

–

+

–

0/-6/-12/-18 dB or Mute
600-Ω Data_Out PGA

8-Ω Speaker Buffer

0 dB or Mute

MonOut PGA

0/3/6/9/12 dB Gain

with Mute

MONOUTP

MONOUTM

2.5 V/1.5 V

M
U
X

+
–

DTTX_INP

DTTX_OUTM

+
–

DT_BUFM

1–3

1.4 Terminal Assignments

1
2
3

4
5
6
7
8
9

10

27

28

29

30

31

32

33

34

35

36

NC

DREFP_DAC

NC
DT_MCLK

DREFM_DAC

RESET
DV

SS

DTRXM

DT_DIN
DT_SCLK

DAV

DD

DAV

SS

NC

NC

DTRX_FB

DT_DOUT
NC

DT_FS

11
12

25

26

NC

DTRXP

NC

NC

1314 151617 1819 20 21 222324

484746 45 44 43 42 4140 39

3837

DT_REF

DTTX_OUTM

DT_BUFP

DT_BUFM

DV

DD

V

NC

FLSH_OUT

FLSH_IN

DTTX_OUTP

DTTX_INM

DTTX_INP

NC
NC

DREFM_ADC

TEST1

MONOUTM

MV

SS

MV

MONOUTP

TCLK

SI_SEL

FILTNCDREFP_ADC

TEST2

DD

TLC320AD545

NC–Make no external connection

SS

1.5 Ordering Information

PACKAGE

T

A

PLASTIC QUAD
FLATPACK (PT)

0°C to 70°C TLC320AD545PT

–40°C to 85°C TLC320AD545IPT

1.6 Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

NC 3, 4, 7, 8,

11, 21, 25,

26, 35, 36,

45

No connection

DAV

DD

5 I Analog power supply (5 V/3.3 V)

DAV

SS

6 I Analog ground

DREFM_ADC 48 O ADC voltage reference filter output. DREFM_ADC provides lowpass filtering for the internal bandgap

reference. The optimal ceramic capacitor value is 0.1 uF connected between DREFM_ADC and
DREFP_ADC. The nominal dc voltage at this terminal is 0 V.

DREFM_DAC 2 O DAC voltage reference filter output. DREFM_DAC provides for lowpass filtering the internal bandgap

reference. The optimal ceramic capacitor value is 0.1 µF connected between DREFM_ADC and
DREFP_ADC. The nominal dc voltage at this terminal is 0 V.

1–4

1.6 Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

DREFP_ADC 47 O ADC voltage reference filter output. DREFP_ADC provides lowpass filtering for the internal bandgap reference.

The optimal ceramic capacitor value is 0.1 µF connected between DREFM_ADC and DREFP_ADC. The dc
voltage at this terminal is 3.375 V with a 5-V DAVDD supply and 2.25 V with a 3.3-V DAVDD supply.

DREFP_DAC 1 O DAC voltage reference filter output. DREFP_DAC provides for lowpass filtering the internal bandgap reference.

The optimal ceramic capacitor value is 0.1 µF connected between DREFM_DAC and DREFP_DAC. The dc
voltage at this terminal is 3.375 V at 5-V DAVDD supply and 2.25 V at 3.3-V DAVDD supply.

DT_BUFM 19 O Buf fer amp analog inverting output. DT_BUFM can be programmed for 0 dB, -6 dB, -12dB, and -18 dB gain or

muted using the control registers. This output is normally fed to the DTTX_INM terminal through an input resistor.

DT_BUFP 18 O Buffer amp analog noninverting output. DT_BUFP can be programmed for 0 dB, -6 dB, -12 dB and -18 dB gain

or muted using the control registers. This output is normally fed to the DTTX_INP terminal through an input
resistor. DT_BUFP must be left unconnected in single-ended hybrid.

DT_DIN 33 I Digital data input. DT_DIN handles DAC input data as well as control register programming information during

frame sync interval and is synchronized to DT_SCLK.

DT_DOUT 31 O Digital data output. ADC output bits transmit data during the frame sync period which is synchronized to

DT_SCLK. DT_DOUT is at high impedance when DT_FS is not activated.

DT_FS 30 O Serial port frame sync signal. DT_FS signals the beginning of transmit for ADC data and receiving of DAC data.

This signal can be active high (FS high mode) or active low (FS low mode) depending on the voltage applied to
SI_SEL (see Section 4,

Serial Communications

).
DT_MCLK 34 I Master clock input. All internal clocks are derived from this clock.
DT_REF 13 O Reference voltage for the transformer at 2.5 V for a 5-V DAVDD supply and 1.5 V for a 3.3-V DAVDD supply. The

maximum source or sink current at this terminal is 2.5 mA. DT_REF must be left unconnected in differential hybrid.

DTRX_FB 9 O Receive path amplifier feedback node. DTRX_FB terminal is connected to the noninverting output of the receive

path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain

and filter poles.
DTRXM 10 I Receive path amplifier analog inverting input
DTRXP 12 I Receive path amplifier analog noninverting input
DT_SCLK 32 O Shift clock signal. DT_SCLK clocks serial data into DT_DIN and out of DT_DOUT during the frame-sync interval.

DT_SCLK rate is DT_MCLK/2.
DTTX_INM 15 I Transmit amplifier analog inverting input. This node is normally fed by the DT_BUFM output through an input

resistor.
DTTX_INP 16 I Transmit amplifier analog noninverting input. This node is normally fed by the DT_BUFP output through an input

resistor. DTTX_INP must be shorted to DTTX_OUTM in single-ended hybrid.
DTTX_OUTM 17 O Transmit amplifier analog inverting output. DTTX_OUTM must be shorted to DTTX_INP in single-ended hybrid.
DTTX_OUTP 14 O Transmit amplifier analog noninverting output
DV

DD

22 I Digital and RESET circuit power supply (5 V/3.3 V)

DV

SS

27 I Digital and RESET circuit ground

FILT 46 O Bandgap filter node. FILT provides decoupling of the bandgap reference voltage. This reference is 3.375 V with

a 5-V supply and 2.25 V with a 3.3-V supply. The optimal capacitor value is 0.1 µF (ceramic). This node should

not be used as a voltage source.
FLSH_IN 24 I External ASIC logic input. When brought low, FLSH_IN enables the FLSH_OUT output.
FLSH_OUT 23 O Power output to write/erase flash EEPROM device (such as Intel 28F400B or AMD Am29F400). Supplies 45

mA maximum from 5 V when FLSH_IN

is brought low.

MONOUTM 42 O Analog output from 8-Ω monitor speaker amplifier which can be set for 0-dB gain or muted through the control

registers.
MONOUTP 40 O Analog output from 8-Ω monitor speaker amplifier which can be set for 0-dB gain or muted through the control

registers.
MV

DD

41 I Monitor amplifier supply (5 V/3.3 V)
Intel is a trademark of Intel Systems, Inc.
AMD is a trademark of Advanced Micro Devices, Inc.

1–5

1.6 Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

MV

SS

39 I Monitor amplifier ground
RESET 28 I Codec device reset. RESET initializes all device internal registers to default values. This signal is active low.
SI_SEL 37 I Serial interface mode select. When SI_SEL is tied to DV

DD,

the serial port is in FS high mode. When SI_SEL is

tied to DVSS, the serial port is in FS low mode. (see Section 4,

Serial Communications

).
TCLK 38 O Test output port. TCLK is for factory test only and should be either connected to ground or left unconnected.
TEST1 43 I/O Test input port. TEST1 is for factory test only and should be either connected to ground or left unconnected.
TEST2 44 I/O Test input port. TEST2 is for factory test only and should be either connected to ground or left unconnected.
V

SS

20 I Internal substrate connection. VSS should be tied to DAVSS

.