Texas Instruments TL 16 C 2550 INSTALLATION INSTRUCTIONS

www.DataSheet4U.com

www.ti.com

2.5-V to 5-V DUAL UART WITH 16-BYTE FIFOS

TL16C2550

SLWS161 – JUNE 2005

FEATURES

• Internal Diagnostic Capabilities:

• Programmable Auto-RTS and Auto-CTS – Loopback Controls for Communications

• In Auto-CTS Mode, CTS Controls Transmitter

• In Auto-RTS Mode, RCV FIFO Contents and

Threshold Control RTS

• Serial and Modem Control Outputs Drive a

Link Fault Isolation

– Break, Parity, Overrun, and Framing Error

Simulation

• Fully Prioritized Interrupt System Controls

RJ11 Cable Directly When Equipment Is on • Modem Control Functions ( CTS, RTS, DSR,
the Same Power Drop DTR, RI, and DCD)

• Capable of Running With All Existing • Available in 48-Pin TQFP (PFB), 44-Pin PLCC

TL16C450 Software (FN), or 32-Pin QFN (RHB) Packages

• After Reset, All Registers Are Identical to the • Pin Compatible with TL16C752B (48-Pin

TL16C450 Register Set Package)

• Up to 24-MHz Clock Rate for up to 1.5-Mbaud

Operation With V

= 5 V

CC

• Up to 20-MHz Clock Rate for up to 1.25-Mbaud

Operation With V

= 3.3 V

CC

• Up to 16-MHz Clock Rate for up to 1-Mbaud

Operation With V

= 2.5 V

CC

• In the TL16C450 Mode, Hold and Shift

Registers Eliminate the Need for Precise

APPLICATIONS

• Point-of-Sale Terminals

• Gaming Terminals

• Portable Applications

• Router Control

• Cellular Data

• Factory Automation

Synchronization Between the CPU and Serial
Data

• Programmable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1 to

16

(2

- 1) and Generates an Internal 16 × Clock

• Standard Asynchronous Communication Bits

(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream

• 5-V, 3.3-V, and 2.5-V Operation

• Independent Receiver Clock Input

• Transmit, Receive, Line Status, and Data Set

Interrupts Independently Controlled

DESCRIPTION

The TL16C2550 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
functionality of two TL16C550D UARTs, each UART
having its own register set and FIFOs. The two
UARTs share only the data bus interface and clock
source, otherwise they operate independently.
Another name for the uart function is Asynchronous
Communications Element (ACE), and these terms will
be used interchangeably. The bulk of this document
will describe the behavior of each ACE, with the
understanding that two such devices are incorporated
into the TL16C2550.

• Fully Programmable Serial Interface

Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation and

Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 1 Mbit/s)

• False-Start Bit Detection

• Complete Status Reporting Capabilities

• 3-State Output TTL Drive Capabilities for

Bidirectional Data Bus and Control Bus

• Line Break Generation and Detection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the forma­tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.

Copyright © 2005, Texas Instruments Incorporated

www.ti.com

PRODUCT PREVIEW

NC−No internal connection

14 15

RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC

36
35
34
33
32
31
30
29
28
27
26
25

16

1
2
3
4
5
6
7
8
9
10
11
12

D5
D6

D7
RXB
RXA

TXRDYB

TXA

TXB
OPB
CSA
CSB

NC

17 18 19 20

PFB PACKAGE

(TOP VIEW)

RA

CDA

DSRA

CTSA

47 46 45 44 4348 42

D4D3D2D1D0

TXRDYA

RTSB

CTSB

NC

IOW

CDB

GND

IOR

DSRB

RIB

40 39 3841

21

22 23 24

37

13

XTAL1

NC

V

CC

XTAL2

RXRDYB

TL16C2550PFB

RESET

OPA

D5
D6

A0

A2

A1

INTB

INTA

RXRDYA

RTSA

DTRA

DTRB

39

35

31

29

30

32

33

34

36

37

38

246 1 42 4041434435

7
8

9
10
11
12
13
14
15
16
17

1918 26 2820 21 22 23 24 25 27

RXB
RXA

TXRDYB

TXA
TXB

OPB
CSA

CSB

D7

IOW

XTAL1

XTAL2

CDB

GND

RXRDYB

IOR

DSRB

RIB

RTSB

CTSB

D4

D0

CDA

CTSA

DSRA

RIA

V

CC

TXRDYA

D1

D2

D3

TL16C2550FN

FN PACKAGE

(TOP VIEW)

TL16C2550

SLWS161 – JUNE 2005

Each ACE is a speed and voltage range upgrade of
the TL16C550C, which in turn is a functional upgrade
of the TL16C450. Functionally equivalent to the
TL16C450 on power up or reset (single character or
TL16C450 mode), each ACE can be placed in an
alternate FIFO mode. This relieves the CPU of
excessive software overhead by buffering received
and to be transmitted characters. Each receiver and
transmitter store up to 16 bytes in their respective
FIFOs, with the receive FIFO including three ad­ditional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can
significantly reduce software overload and increase
system efficiency by automatically controlling serial
data flow using handshakes between the RTS#
output and CTS# input, thus eliminating overruns in
the receive FIFO.

Each ACE performs serial-to-parallel conversions on
data received from a peripheral device or modem and
stores the parallel data in its receive buffer or FIFO,
and each ACE performs parallel-to-serial conversions
on data sent from its CPU after storing the parallel
data in its transmit buffer or FIFO. The CPU can read
the status of either ACE at any time. Each ACE
includes complete modem control capability and a
processor interrupt system that can be tailored to the
application.

Each ACE includes a programmable baud rate gener­ator capable of dividing a reference clock with div­isors of from 1 to 65535, thus producing a 16×
internal reference clock for the transmitter and re­ceiver logic. Each ACE accommodates up to a

1.5-Mbaud serial data rate (24-MHz input clock). As a
reference point, that speed would generate a 667-ns
bit time and a 6.7-µs character time (for 8,N,1 serial
data), with the internal clock running at 24 MHz.

Each ACE has a TXRDY# and RXRDY# output that
can be used to interface to a DMA controller.

2

www.ti.com

1
2
3
4
5
6
7
8

9

10

11

12

13

14

15

16

24
23
22
21
20
19
18
17

D6

D7
RXB
RXA

TXA

TXB
CSA
CSB

RESET
RTSA
INTA
INTB
A0
A1
A2
NC

32

31

30

29

28

27

26

25

D5D4D3D2D1D0VCCCTSA

NC

XTAL1

XTAL2

IOW

GND

IOR

RTSB

CTSB

RHB PACKAGE

(TOP VIEW)

NC − No internal connection

TL16C2550RHB

Crystal

OSC

Buffer

Data Bus
Interface

A2 − A0
D7 − D0

CSA
CSB

IOR

IOW

INTA

INTB

TXRDYA

TXRDYB
RXRDYA
RXRDYB

RESET

XTAL1
XTAL2

BAUD

Rate

Gen

16 Byte Tx FIFO

16 Byte Rx FIFO

Tx

Rx

UART Channel A

BAUD

Rate

Gen

16 Byte Tx FIFO

16 Byte Rx FIFO

Tx

Rx

UART Channel B

CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA

CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB

V

CC

GND

TXA

RXA

TXB

RXB

UART Regs

UART Regs

TL16C2550

SLWS161 – JUNE 2005

NOTE: The 32-pin RHB package does not provide access to DSRA, DRRB, RIA, RIB, CDA, CDB inputs, and OPA, OPB,

RXRDYA, RXRDYB, TXRDYA, TXRDYB outputs.

Figure 1. TL16C2550 Block Diagram

3

www.ti.com

PRODUCT PREVIEW

TL16C2550

SLWS161 – JUNE 2005

TERMINAL

NAME PFB NO. FN NO. RHB NO.

A0 28 31 20 I Address 0 select bit. Internal registers address selection
A1 27 30 19 I Address 1 select bit. Internal registers address selection
A2 26 29 18 I Address 2 select bit. Internal registers address selection

CDA, CDB 40, 16 42, 21 – I

CSA, CSB 10, 11 16, 17 7, 8 I

CTSA, or data set is ready to accept transmit data from the 2550. Status can be
CTSB tested by reading MSR bit 4. These pins only affect the transmit and receive

D0-D4 44 - 48 2 - 6 27 - 31 Data bus (bidirectional). These pins are the eight bit, 3-state data bus for

D5-D7 1 - 3 7 - 9 32, 1, 2

DSRA, UART channels A and B. A logic low on these pins indicates the modem or
DSRB data set is powered on and is ready for data exchange with the UART. The

DTRA, theTLl16C2550 is powered on and ready. These pins can be controlled
DTRB through the modem control register. Writing a 1 to MCR bit 0 sets the DTR

GND 17 22 13 Signal and power ground.

INTA, a logic 1, interrupt sources are enabled in the interrupt enable register
INTB (IER). Interrupt conditions include: receiver errors, available receiver buffer

IOR 19 24 14 I contents of an internal register defined by address bits A0-A2 onto the

IOW 15 20 12 I the contents of the data bus (D0-D7) from the external CPU to an internal

NC – 9, 17 No internal connection

OPA, OPB 32, 9 35, 15 – O a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state

RESET 36 39 24 I

38, 23 40, 28 25, 16 I

39, 20 41, 25 – I

34, 35 37, 38 – O

30, 29 33, 32 22, 21 O

12, 24, 25,

37

DEVICE INFORMATION

TERMINAL FUNCTIONS

I/O DESCRIPTION

Carrier detect (active low). These inputs are associated with individual
UART channels A and B. A low on these pins indicates that a carrier has
been detected by the modem for that channel. The state of these inputs is
reflected in the modem status register (MSR).

Chip select A and B (active low). These pins enable data transfers between
the user CPU and the TL16C2550 for the channel(s) addressed. Individual
UART sections (A, B) are addressed by providing a low on the respective
CSA and CSB pins.

Clear to send (active low). These inputs are associated with individual
UART channels A and B. A logic low on the CTS pins indicates the modem

operations when auto CTS function is enabled through the enhanced
feature register (EFR) bit 7, for hardware flow control operation.

I/O

transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.

Data set ready (active low). These inputs are associated with individual

state of these inputs is reflected in the modem status register (MSR).
Data terminal ready (active low). These outputs are associated with

individual UART channels A and B. A logic low on these pins indicates that

output to low, enabling the modem. The output of these pins is high after
writing a 0 to MCR bit 0, or after a reset.

Interrupt A and B (active high). These pins provide individual channel
interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to

data, available transmit buffer space or when a modem status flag is
detected. INTA-B are in the high-impedance state after reset.

Read input (active low strobe). A high to low transition on IOR will load the
TL16C2550 data bus (D0-D7) for access by an external CPU.

Write input (active low strobe). A low to high transition on IOW will transfer
register that is defined by address bits A0-A2 and CSA and CSB

User defined outputs. This function is associated with individual channels A
and B. The state of these pins is defined by the user through the software
settings of the MCR register, bit 3. INTA-B are set to active mode and OP to

mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3,
modem control register (MCR bit 3). The output of these two pins is high
after reset.

Reset. RESET will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during reset
time. See TL16C2550 external reset conditions for initialization details.
RESET is an active-high input.

4

www.ti.com

SLWS161 – JUNE 2005

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME PFB NO. FN NO. RHB NO.

RIA, RIB 41, 21 43, 26 – I

RTSA,
RTSB

RXA, RXB 5, 4 11, 10 4, 3 I

RXRDYA,
RXRDYB

TXA, TXB 7, 8 13, 14 5, 6 O channel data from the 2550. During the local loopback mode, the TX input

TXRDYA,
TXRDYB

V

CC

XTAL1 13 18 10 I

XTAL2 14 19 11 O

33, 22 36, 27 23, 15 O (MCR bit 1) sets these pins to low, indicating data is available. After a reset,

31, 18 34, 23 – O level has been reached or a timeout interrupt occurs. They go high when

43, 6 11, 12 – O a trigger level numbers of spaces available. They go high when the TX

42 44 26 I Power supply inputs.

I/O DESCRIPTION

Ring indicator (active low). These inputs are associated with individual
UART channels A and B. A logic low on these pins indicates the modem
has received a ringing signal from the telephone line. A low to high
transition on these input pins generates a modem status interrupt, if
enabled. The state of these inputs is reflected in the modem status register
(MSR)

Request to send (active low). These outputs are associated with individual
UART channels A and B. A low on the RTS pin indicates the transmitter has
data ready and waiting to send. Writing a 1 in the modem control register

these pins are set to high. These pins only affects the transmit and receive
operation when auto RTS function is enabled through the enhanced feature
register (EFR) bit 6, for hardware flow control operation.

Receive data input. These inputs are associated with individual serial
channel data to the 2550. During the local loopback mode, these RX input
pins are disabled and TX data is internally connected to the UART RX input
internally.

Receive ready (active low). RXRDY A and B goes low when the trigger
the RX FIFO is empty or there is an error in RX FIFO.

Transmit data. These outputs are associated with individual serial transmit
pin is disabled and TX data is internally connected to the UART RX input.

Transmit ready (active low). TXRDY A and B go low when there are at least
buffer is full.

Crystal or external clock input. XTAL1 functions as a crystal input or as an
external clock input. A crystal can be connected between XTAL1 and
XTAL2 to form an internal oscillator circuit (see Figure 10). Alternatively, an
external clock can be connected to XTAL1 to provide custom data rates.

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is
used as a crystal oscillator output or buffered a clock output.

TL16C2550

Detailed Description

Autoflow Control (see Figure 2)

Autoflow control is comprised of auto- CTS and auto- RTS. With auto- CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto- RTS, RTS becomes active when the receiver needs more data and
notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2550 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.

5

www.ti.com

PRODUCT PREVIEW

RCV
FIFO

Serial to

Parallel

Flow

Control

XMT
FIFO

Parallel

to Serial

Flow

Control

Parallel

to Serial

Flow

Control

Serial to

Parallel

Flow

Control

XMT

FIFO

RCV
FIFO

ACE1 ACE2

D7−D0

SIN SOUT

RTS CTS

SOUT SIN

CTS RTS

D7−D0

Start Bits 0−7 Start Bits 0−7 Start Bits 0−7

Stop Stop Stop

SOUT

CTS

TL16C2550

SLWS161 – JUNE 2005

Figure 2. Autoflow Control (Auto- RTS and Auto- CTS) Example

Auto- RTS (see Figure 2)

Auto- RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it
may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.

When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.

Auto- CTS (see Figure 2)

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 2). The auto- CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto- CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.

Enabling Autoflow Control and Auto- CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 ( RTS) to a 1.
Autoflow incorporates both auto- RTS and auto- CTS. When only auto- CTS is desired, bit 1 in the modem control
register should be cleared (this assumes that a control signal is driving CTS).

Auto- CTS and Auto- RTS Functional Timing

6

Figure 3. CTS Functional Timing Waveforms

www.ti.com

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

SIN

RTS

RD

(RD RBR)

1 2

N N+1

Byte 14 Byte 15

SIN

RTS

RD

(RD RBR)

Start Byte 18 StopStart Byte 16 Stop

RTS Released After the

First Data Bit of Byte 16

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes

TL16C2550

SLWS161 – JUNE 2005

Figure 5. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

7

www.ti.com

PRODUCT PREVIEW

Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding
Register

Modem

Control

Register

Modem

Status

Register

Line

Control

Register

Transmitter

FIFO

Interrupt

Enable

Register

Interrupt

Identification

Register

FIFO

Control

Register

Select

and

Control

Logic

Interrupt

Control

Logic

S
e

l
e
c

t

Data

Bus

Buffer

RXA, B

TXA, B

CTSA, B
DTRA, B
DSRA, b
CDA,B
RIA, B
OPA, B

INTA, B

38, 23
34, 35
39, 20
40, 16
41, 21

32, 9

30, 29

7, 8

5,4

A0

28

D(7−0)

3 −1
48−44

Internal
Data Bus

27
26

10
11

14

36
19

15

13

43
31

A1
A2

CSA
CSB

XTAL2

RESET

IOR

IOW

XTAL1

TXRDYA
RXRDYA

S
e

l
e
c

t

Receiver

Shift

Register

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Register

Modem

Control

Logic

8

42
17

V

CC

GND

Power
Supply

RTSA, B

33, 22

Autoflow
Control
(AFE)

8

8

8

8

8

8

8

6
18

TXRDYB

RXRDYB

Crystal

OSC

Buffer

TL16C2550

SLWS161 – JUNE 2005

A. Pin numbers shown are for 48-pin TQFP PFB package.

8

Figure 6. Functional Block Diagram

www.ti.com

SLWS161 – JUNE 2005

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

UNIT

Supply voltage range, V
Input voltage range at any input, V
Output voltage range, V

O

(2)

(see

CC

) -0.5 V to 7 V

I

-0.5 V to 7 V

-0.5 V to 7 V
Operating free-air temperature, TA, TL16C2550 0°C to 70°C
Operating free-air temperature, TA, TL16C2550I -40°C to 85°C
Storage temperature range, T

stg

-65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

2.5 V ±10% MIN NOM MAX UNIT

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

Supply voltage 2.25 2.5 2.75 V
Input voltage 0 V

CC

High-level input voltage 1.8 2.75 V
Low-level input voltage -0.3 0.6 V
Output voltage 0 V

CC

High-level output current (all outputs) 1 mA
Low-level output current (all outputs) 2 mA
Oscillator/clock speed 16 MHz

TL16C2550

V

V

3.3 V ±10% MIN NOM MAX UNIT

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

Supply voltage 3 3.3 3.6 V
Input voltage 0 V
High-level input voltage 0.7V

CC

Low-level input voltage 0.3V
Output voltage 0 V

CC

CC
CC

High-level output current (all outputs) 1.8 mA
Low-level output current (all outputs) 3.2 mA
Oscillator/clock speed 20 MHz

5 V ±10% MIN NOM MAX UNIT

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

Supply voltage 4.5 5 5.5 V
Input voltage 0 V

CC

High-level input voltage All except XTAL1, XTAL2 2 V

XTAL1, XTAL2 0.7V

CC

Low-level input voltage All except XTAL1, XTAL2 0.8 V

XTAL1, XTAL2 0.3V

Output voltage 0 V

CC
CC

High-level output current (all outputs) 4 mA
Low-level output current (all outputs) 4 mA
Oscillator/clock speed 24 MHz

V
V
V
V

V

V

9

www.ti.com

PRODUCT PREVIEW

TL16C2550

SLWS161 – JUNE 2005

ELECTRICAL CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

2.5 V Nominal
PARAMETER TEST CONDITIONS MIN TYP

V

OH

V

OL

I

I

I

OZ

I

CC

C

i(CLK)

C

O(CLK)

C

I

C

O

High-level output voltage
Low-level output voltage
Input current V

High-impedance-state output current V

Supply current V

Clock input impedance V
Clock output impedance 20 30 pF
Input impedance 6 10 pF
Output impedance 10 20 pF

(1) All typical values are at V
(2) These parameters apply for all outputs except XTAL2.

ADDED SPACE

3.3V Nominal
PARAMETER TEST CONDITIONS MIN TYP

V

OH

V

OL

I

I

I

OZ

I

CC

C

i(CLK)

C

O(CLK)

C

I

C

O

High-level output voltage
Low-level output voltage
Input current V

High-impedance-state output current V

Supply current V

Clock input impedance V
Clock output impedance 20 30 pF
Input impedance 6 10 pF
Output impedance 10 20 pF

(1) All typical values are at V
(2) These parameters apply for all outputs except XTAL2.

(2)

(2)

= 2.5 V and TA= 25°C.

CC

(2)

(2)

= 3.3 V and TA= 25°C.

CC

IOH= -1 mA 1.8 V
IOL= 2 mA 0.5 V

= 3.6 V, V

CC

V, All other terminals floating

= 3.6 V, V

CC

V, Chip slected in write mode or chip

= 0, VI= 0 to 3.6 10 µA

SS

= 0, VI= 0 to 3.6 ±20 µA

SS

deselcted

= 3.6 V, TA= 25°C, RXA, RXB, 16 mA

CC

DSRA, DSRB, CDA, CDB, CTSA,
CTSB, RIA, and RIB at 2 V, All other
inputs at 0.8 V, XTAL1 at 4 MHz, No
load on outputs,

= 0, V

CC

25°C, All other terminals grounded

= 0, f = 1 MHz, TA= 15 20 pF

SS

IOH= -1.8 mA 2.4 V
IOL= 3.2 mA 0.5 V

= 3.6 V, V

CC

V, All other terminals floating

= 3.6 V, V

CC

V, Chip slected in write mode or chip

= 0, VI= 0 to 3.6 10 µA

SS

= 0, VI= 0 to 3.6 ±20 µA

SS

deselcted

= 3.6 V, TA= 25°C, RXA, RXB, 20 mA

CC

DSRA, DSRB, CDA, CDB, CTSA,
CTSB, RIA, and RIB at 2 V, All other
inputs at 0.8 V, XTAL1 at 4 MHz, No
load on outputs,

= 0, V

CC

25°C, All other terminals grounded

= 0, f = 1 MHz, TA= 15 20 pF

SS

(1)

(1)

MAX UNIT

MAX UNIT

10

www.ti.com

5 V Nomial

PARAMETER TEST CONDITIONS MIN TYP

V

OH

V

OL

I

I

I

OZ

High-level output voltage
Low-level output voltage
Input current V

High-impedance-state output current V

(2)

(2)

IOH= -4 mA 4 V
IOL= 4 mA 0.4 V

= 5.25 V, V

CC

V, All other terminals floating

= 5.25 V, V

CC

V, Chip slected in write mode or chip

= 0, VI= 0 to 5.25 10 µA

SS

= 0, VI= 0 to 5.25 ±20 µA

SS

(1)

deselcted

I

CC

Supply current V

= 5.25 V, TA= 25°C, RXA, 24 mA

CC

RXB, DSRA, DSRB, CDA, CDB,
CTSA, CTSB, RIA, and RIB at 2 V,
All other inputs at 0.8 V, XTAL1 at 4
MHz, No load on outputs,

C

i(CLK)

C

O(CLK)

C

I

C

O

(1) All typical values are at V
(2) These parameters apply for all outputs except XTAL2.

Clock input impedance V
Clock output impedance 20 30 pF

= 0, V

CC

25°C, All other terminals grounded

SS

= 0, f = 1 MHz, TA= 15 20 pF

Input impedance 6 10 pF
Output impedance 10 20 pF

= 5 V and TA= 25°C.

CC

TIMING REQUIREMENTS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER 2.5 V 3.3 V 5 V UNIT

ALT. SYM- FIG- TEST

BOL URE CONDITIONS

MIN MAX MIN MAX MIN MAX

t

Cycle time, read (tw7+ td8+ td9) RC 87 ns

cR

t

Cycle time, write (tw6+ td5+ td6) WC 87 ns

cW

t

Pulse duration, clock high t

w1

t

Pulse duration, clock low t

w2

t

Pulse duration, clock high t

w1

t

Pulse duration, clock low t

w2

t

Pulse duration, clock high t

w1

t

Pulse duration, clock low t

w2

t

Pulse duration, IOW t

w6

t

Pulse duration, IOR t

w7

t

Pulse duration, RESET t

w8

t

Setup time, data valid before IOW↑ t

SU3

t

Setup time, CTS↑ before midpoint of 17 10 ns

SU4

stop bit

t

Hold time, CS valid after IOW↑ t

h3

t

Hold time, address valid after IOW↑ t

h4

t

Hold time, data valid after IOW↑ t

h5

t

Hold time, chip select valid after IOR↑ t

h6

t

Hold time, address valid after IOR↑ t

h7

t

Delay time, CS valid before IOW↓ t

d4

t

Delay time, address valid before t

d5

IOW↓

t

Delay time, CS valid to IOR↓ t

d7

t

Delay time, address valid to IOR↓ t

d8

t

Delay time, IOR↓ to data valid t

d10

t

Delay time, IOR↑ to floating data t

d11

XH
XL
XH
XL
XH

XL
IOW
IOR

RESET

DS

WCS

WA

DH

RCS

RA

CSW

AW

CSR

AR

RVD

HZ

5 f = 16 MHz Max, 25 ns

V

= 2.5 V

CC

5 f = 20 MHz Max, 20 ns

V

= 3.3 V

CC

5 f = 24 MHz Max, 18 ns

V

= 5 V

CC

6 40 ns
7 40 ns

1 µs

6 15 ns

6 10 ns

6 5 ns
7 10 ns
7 20 ns
6 7 ns

7 7 ns

7 CL= 75 pF 45 ns
7 CL= 75 pF 20 ns

LIMITS

TL16C2550

SLWS161 – JUNE 2005

MAX UNIT

11