THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
High Speed
– 180 MHz Bandwidth (G = 1, –3 dB)
– 400 V/µs Slew Rate
– 40-ns Settling Time (0.1%)
D
High Output Drive, IO = 115 mA (typ)
D
Excellent Video Performance
– 75 MHz 0.1 dB Bandwidth (G = 1)
– 0.02% Differential Gain
– 0.02° Differential Phase
D
Very Low Distortion
– THD = –72 dBc at f = 1 MHz
D
Wide Range of Power Supplies
– VCC = ±5 V to ±15 V
D
Available in Standard SOIC, MSOP
PowerPAD, JG, or FK Package
D
Evaluation Module Available
description
The THS4061 and THS4062 are generalpurpose, single/dual, high-speed voltage feedback amplifiers ideal for a wide range of
applications including video, communication, and
imaging. The devices offer very good ac
performance with 180-MHz bandwidth, 400-V/µs
slew rate, and 40-ns settling time (0.1% ). The
THS4061/2 are stable at all gains for both
inverting and noninverting configurations. These
amplifiers have a high output drive capability of
1 15 mA and draw only 7.8 mA supply current per
channel. Excellent professional video results can
be obtained with the low differential gain/phase
errors of 0.02%/0.02° and wide 0.1 db flatness to
75 MHz. For applications requiring low distortion,
the THS4061/2 is ideally suited with total
harmonic distortion of –72 dBc at f = 1 MHz.
PowerPAD is a trademark of Texas Insruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
THS4062
D AND DGN PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
–V
CC
V
CC+
2OUT
2IN–
2IN+
1
2
3
4
8
7
6
5
NULL
IN–
IN+
V
CC–
NULL
V
CC+
OUT
NC
THS4061
JG, D AND DGN PACKAGE
(TOP VIEW)
NC – No internal connection
_
+
THS4061
2 kΩ
V
I
2 kΩ
75 Ω
75 Ω
V
O
75 Ω
LINE DRIVER (G = 2)
Cross-Section View Showing
PowerPAD Option (DGN)
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
V
CC+
NC
OUT
NC
NC
IN–
NC
IN+
NC
NC
NULLNCNULL
NC
V
NCNCNC
NC
THS4061
FK PACKAGE
(TOP VIEW)
CC–
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CAUTION: The THS4061 and THS4062 provide ESD protection circuitry. However , permanent damage can still occur if this
device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any
performance degradation or loss of functionality
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RELATED DEVICES
DEVICE DESCRIPTION
THS4011/2
THS4031/2
THS4061/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
NUMBER OF
CHANNELS
PLASTIC
SMALL
OUTLINE
†
(D)
PLASTIC
MSOP
†
(DGN)
CERAMIC
DIP
(JG)
CHIP
CARRIER
(FK)
MSOP
SYMBOL
EVALUATION
MODULES
0°C to
1 THS4061CD THS4061CDGN — — TIABS THS4061EVM
70°C
2 THS4062CD THS4062CDGN — — TIABM THS4062EVM
–40°C to
1 THS4061ID THS4061IDGN — — TIABT —
85°C
2 THS4062ID THS4062IDGN — — TIABN —
–55°C to
125°C
1 — — THS4061MJG THS4061MFK — —
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4061CDGNR).
functional block diagram
OUT
8
6
1
IN–
IN+
2
3
Null
–
+
Figure 1. THS4061 – Single Channel
1OUT
1IN–
1IN+
V
CC
2OUT
2IN–
2IN+
–V
CC
8
6
1
2
3
5
7
4
–
+
–
+
Figure 2. THS4062 – Dual Channel
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, VCC+ to VCC– 33 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI ±V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
IO
±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M-suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D and DGN package 300°C. . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package 300°C. . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C DERATING FACTOR T
= 70°C T
= 85°C T
= 125°C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATING
A
POWER RATING
A
POWER RATING
D 740 mW 6 mW/°C 475 mW 385 mW —
DGN
‡
2.14 W 17.1 mW/°C 1.37 W 1.11 W —
JG 1057 mW 8.4 mW/°C 627 mW 546 mW 210 mW
FK 1375 mW 11 mW/°C 880 mW 715 mW 275 mW
‡
The DGN package incorporates a PowerPAD on the underside of the device. This acts as a heatsink and must be connected to a thermal dissipation
plane for proper power dissipation. Failure to do so can result in exceeding the maximum specified junction temperature, which could permanently
damage the device.
recommended operating conditions
MIN NOM MAX UNIT
pp
Dual supply ±4.5 ±16
Suppl
y v
oltage, V
CC
+
and V
CC
–
Single supply 9 32
V
C-suffix 0 70
Operating free-air temperature, T
A
I-suffix –40 85
°C
M-suffix –55 125
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
dynamic performance
PARAMETER
TEST CONDITIONS
†
THS4061C/I,
THS4062C/I
UNIT
MIN TYP MAX
VCC = ±5 V Gain = 1 180 MHz
Dynamic performance small-signal
–
VCC = ±15 V
50
BW
bandwidth (–3 dB)
VCC = ±5 V
Gain
= –
1
50
MH
z
VCC = ±15 V
75
Bandwidth for 0.1 dB flatness
VCC = ±5 V
Gain
=
1
20
MH
z
VCC = ±15 V
400
SR
Slew rate
VCC = ±5 V
Gain
= –
1
350
V/µs
VCC = ±15 V, 5-V step (0 V to 5 V)
40
Settling time to 0.1%
VCC = ±5 V, VO = –2.5 V to 2.5 V,
Gain
= –
1
40
ns
t
s
VCC = ±15 V, 5-V step (0 V to 5 V)
140
Settling time to 0.01%
VCC = ±5 V, VO = –2.5 V to 2.5 V,
Gain
= –
1
150
ns
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
noise/distortion performance
PARAMETER
TEST CONDITIONS
†
THS4061C/I,
THS4062C/I
UNIT
MIN TYP MAX
THD Total harmonic distortion f = 1 MHz –72 dBc
V
n
Input voltage noise f = 10 kHz, VCC = ±5 V or ±15 V 14.5 nV/√Hz
I
n
Input current noise f = 10 kHz, VCC = ±5 V or ±15 V 1.6 pA/√Hz
VCC = ±15 V
0.02
%
Differential gain error
Gain
= 2,
NTSC
, 40
IRE modulation
VCC = ±5 V
0.02
%
p
VCC = ±15 V 0.02°
Differential phase error
Gain
= 2,
NTSC
, 40
IRE modulation
VCC = ±5 V 0.06°
Channel-to-channel crosstalk
(THS4062 only)
VCC = ±5 V or ±15 V, f = 1 MHz 65 dB
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
dc performance
PARAMETER
TEST CONDITIONS
†
THS4061C/I,
THS4062C/I
UNIT
MIN TYP MAX
TA = 25°C 5 15
p
p
V
CC
=
±15 V,V
O
=
±10 V
,
R
L
=
1 kΩ
TA = full range 4
V/mV
Open loop gain
TA = 25°C 2.5 8
V
CC
= ±5 V,
V
O
= ±2.5 V,
R
L
= 1
kΩ
TA = full range 2
V/mV
Input offset voltage VCC = ±5 V or ±15 V
2.5 8 mV
V
OS
Offset drift VCC = ±5 V or ±15 V
T
A
=
full range
15 µV/°C
I
IB
Input bias current VCC = ±5 V or ±15 V TA = full range 3 6 µA
I
OS
Input offset current VCC = ±5 V or ±15 V TA = full range 75 250 nA
Offset current drift TA = full range 0.3 nA/°C
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
input characteristics
PARAMETER
TEST CONDITIONS
†
THS4061C/I,
THS4062C/I
UNIT
MIN TYP MAX
p
VCC = ±15 V ±13.8 ±14.1
V
ICR
Common-mode input voltage range
VCC = ±5 V ±3.8 ±4.3
V
VCC = ±15 V , V
ICR
= ±12 V
70 110
CMRR
Common mode rejection ratio
VCC = ±5 V, V
ICR
= ±2.5 V
T
A
=
full range
70 95
dB
R
I
Input resistance 1 MΩ
C
i
Input capacitance 2 pF
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
output characteristics
PARAMETER
TEST CONDITIONS
†
THS4061C/I,
THS4062C/I
UNIT
MIN TYP MAX
VCC = ±15 V RL = 250 Ω ±11.5 ±12.5
p
VCC = ±5 V RL = 150 Ω ±3.2 ±3.5
V
VOOutput voltage swing
VCC = ±15 V
±13 ±13.5
VCC = ±5 V
R
L
= 1
kΩ
±3.5 ±3.7
V
p
VCC = ±15 V
80 115
IOOutput current
VCC = ±5 V
R
L
= 20
Ω
50 75
mA
I
SC
Short-circuit current VCC = ±15 V 150 mA
R
O
Output resistance Open loop 12 Ω
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
power supply
PARAMETER
TEST CONDITIONS
†
THS4061C/I,
THS4062C/I
UNIT
MIN TYP MAX
pp
p
Dual supply ±4.5 ±16.5
VCCSuppl
y v
oltage operating range
Single supply 9 33
V
p
p
VCC = ±15 V
7.8 10.5
ICCQuiescent current (per amplifier)
VCC = ±5 V
T
A
=
full range
7.3 10
mA
pp
TA = 25°C 70 78
PSRR
Power supply rejection ratio
V
CC
= ±5 V or
±15 V
TA = full range 68
dB
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
dynamic performance
THS4061M
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX
UNIT
Unity-gain bandwidth Closed loop, RL = 1 kΩ VCC = ±15 V *140 180 MHz
VCC = ±15 V
180
Dynamic performance small-signal
VCC = ±5 V
Gain
=
1
180
MH
z
BW
yg
bandwidth (–3 dB)
VCC = ±15 V
50
VCC = ±5 V
Gain
= –
1
50
MH
z
VCC = ±15 V
75
Bandwidth for 0.1 dB flatness
VCC = ±5 V
Gain
=
1
20
MH
z
SR Slew rate VCC = ±15 V RL = 1 kΩ *400 500 V/µs
VCC = ±15 V, 5-V step (0 V to 5 V)
40
Settling time to 0.1%
VCC = ±5 V, VO = –2.5 V to 2.5 V,
Gain
= –
1
40
ns
t
s
VCC = ±15 V, 5-V step (0 V to 5 V)
140
Settling time to 0.01%
VCC = ±5 V, VO = –2.5 V to 2.5 V,
Gain
= –
1
150
ns
†
Full range = –55°C to 125°C for M suffix
*This parameter is not tested.
noise/distortion performance
THS4061M
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX
UNIT
THD Total harmonic distortion f = 1 MHz –72 dBc
V
n
Input voltage noise f = 10 kHz, VCC = ±5 V or ±15 V 14.5 nV/√Hz
I
n
Input current noise f = 10 kHz, VCC = ±5 V or ±15 V 1.6 pA/√Hz
VCC = ±15 V 0.02
Differential gain error
Gain
= 2,
NTSC
, 40
IRE Modulation
VCC = ±5 V 0.02
%
p
VCC = ±15 V 0.02°
Differential phase error
Gain
= 2,
NTSC
, 40
IRE Modulation
VCC = ±5 V 0.06°
†
Full range = –55°C to 125°C for M suffix
dc performance
THS4061M
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX
UNIT
p
p
VCC = ±15 V , VO = ±10 V, RL = 1 kΩ
5 9
Open loop gain
VCC = ±5 V, VO = ±2.5 V, RL = 1 kΩ
T
A
= full
range
2.5 6
V/mV
p
TA = 25°C 2.5 8 mV
V
IO
Input offset voltage
V
CC
=
±5 V or ±15 VR
L
=
1 kΩ
TA = full range 9 mV
Offset drift VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 15 µV/°C
I
IB
Input bias current VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 3 6 µA
I
IO
Input offset current VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 75 250 nA
Offset current drift VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 0.3 nA/°C
†
Full range = –55°C to 125°C for M suffix
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
input characteristics
THS4061M
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX
UNIT
p
VCC = ±15 V ±13.8 ±14.1
V
ICR
Common-mode input voltage range
VCC = ±5 V ±3.8 ±4.3
V
VCC = ±15 V , V
ICR
= ±12 V 70 86
CMRR
Common mode rejection ratio
VCC = ±5 V, V
ICR
= ±2.5 V 80 90
dB
R
I
Input resistance 1 MΩ
C
i
Input capacitance 2 pF
†
Full range = –55°C to 125°C for M suffix
output characteristics
THS4061M
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX
UNIT
VCC = ±15 V RL = 250 Ω ±12 ±13.1
p
VCC = ±5 V RL = 150 Ω ±3.2 ±3.5
V
VOOutput voltage swing
VCC = ±15 V
±13 ±13.5
VCC = ±5 V
R
L
= 1
kΩ
±3.5 ±3.7
V
p
VCC = ±15 V
70 115
IOOutput current
VCC = ±5 V
R
L
= 20
Ω
50 75
mA
I
SC
Short-circuit current VCC = ±15 V TA = 25°C 150 mA
R
O
Output resistance Open loop 12 Ω
†
Full range = –55°C to 125°C for M suffix
power supply
THS4061M
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX
UNIT
pp
p
Dual supply ±4.5 ±16.5
VCCSuppl
y v
oltage operating range
Single supply 9 33
V
VCC = ±15 V
°
7.8 9
VCC = ±5 V
T
A
=
25°C
7.3 8.5
ICCQuiescent current
VCC = ±15 V
11
mA
VCC = ±5 V
T
A
= full
range
10.5
pp
TA = 25°C 76 80
PSRR
Power supply rejection ratio
V
CC
= ±5 V or
±15 V
TA = full range 74 78
dB
†
Full range = –55°C to 125°C for M suffix
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
FIGURE
I
IB
Input bias current vs Free-air temperature 3
V
IO
Input offset voltage vs Free-air temperature 4
Open-loop gain vs Frequency 5
Phase vs Frequency 5
Differential gain vs Number of loads 6, 8
Differential phase vs Number of loads 7, 9
Closed-loop gain vs Frequency 10, 11
Output Amplitude vs Frequency 12, 13
CMRR Common-mode rejection ratio vs Frequency 14
pp
vs Frequency 15
PSRR
Power-supply rejection ratio
vs Free-air temperature 16
V
O(PP)
Output voltage swing vs Supply voltage 17
I
CC
Supply current vs Free-air temperature 18
E
nv
Noise spectral density vs Frequency 19
THD Total harmonic distortion vs Frequency 20, 21
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
–40 –20 0 20 80
TA – Free-Air Temperature – °C
6040
4
3
2
3.5
2.5
100
I
IB
– Input Bias Current – Aµ
VCC = ±15 V, ±5 V
Figure 4
TA – Free-Air Temperature – °C
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
–40 –20 0 804020
–1.5
–0.5
–2.5
V
IO
– Input Offset Voltage – mV
60
0
–1
–2
–3.5
100
VCC = ±5 V
VCC = ±15 V
–3
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
40
20
0
10k 1M
f – Frequency – Hz
50
30
10
100k 10M 100M
60
80
1k
Open-Loop Gain – dB
70
90
–135°
–180°
–90°
Phase
–45°
0°
1G
VCC = ±5 V
VCC = ±15 V
Phase
Figure 5
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
1
0.12%
0.08%
0.04%
23
Number of 150 Ω Loads
0.14%
Differential Gain
0.1%
0.06%
0.02%
4
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
Gain = 2
RF = 680 Ω
40 IRE – NTSC
Worst Case ±100 IRE Ramp
0%
VCC = ±5
Gain
VCC = ±15
Gain
Figure 7
1
0.6
0.4°
0.2°
23
Number of 150 Ω Loads
0.7°
0.5°
0.3°
0.1°
4
Differential Phase
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
Gain = 2
RF = 680 Ω
40 IRE – NTSC
Worst Case ±100 IRE Ramp
0°
VCC = ±15
Phase
VCC = ±5
Phase
Figure 8
1
0.18%
0.14%
0.1%
0.06%
23
Number of 150 Ω Loads
Differential Gain
0.16%
0.12%
0.08%
4
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
0.04%
0%
0.2%
Gain = 2
RF = 680 Ω
40 IRE – PAL
Worst Case ±100 IRE Ramp
0.02%
VCC = ±5
Gain
VCC = ±15
Gain
Figure 9
1
0.9°
0.7°
0.5°
0.3°
23
Number of 150 Ω Loads
0.8°
0.6°
0.4°
4
Differential Phase
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.2°
0°
1°
Gain = 2
RF = 680 Ω
40 IRE – PAL
Worst Case ±100 IRE Ramp
0.1°
VCC = ±15
Phase
VCC = ±5
Phase
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
CLOSED-LOOP GAIN
vs
FREQUENCY
–8
–12
–14
1M 100M
f – Frequency – Hz
–6
–10
10M 1G
–4
0
100k
Closed-Loop Gain – dB
–2
2
Gain = 1
RF = 270 Ω
RL = 150 Ω
VCC = ±15 V
VCC = ±5 V
Figure 11
CLOSED-LOOP GAIN
vs
FREQUENCY
–15
–20
1M 100M
f – Frequency – Hz
–10
10M 1G
–5
5
100k
Closed-Loop Gain – dB
0
VCC = ±15 V , ±5 V
Gain = –1
RF = 510 Ω
RL = 150 Ω
Figure 12
OUTPUT AMPLITUDE
vs
FREQUENCY
100k 1M 10M 100M 1G
f – Frequency – Hz
–4
–8
–6
Output Amplitude – dB
4
0
2
–2
Gain = 1
RL = 150 Ω
RF = 1 kΩ
RF = 200 Ω
RF = 270 Ω
Figure 13
OUTPUT AMPLITUDE
vs
FREQUENCY
100k 1M 10M 100M 1G
f – Frequency – Hz
–6
–10
–8
Output Amplitude – dB
2
–2
0
–4
Gain = –1
RL = 150 Ω
RF = 3 kΩ
RF = 510 Ω
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
CMRR – Common-Mode Rejection Ratio – dB
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
10k 10M 100M
f – Frequency – Hz
1M100k
100
60
20
0
80
40
120
VCC = ±15 V , ±5 V
Figure 15
f – Frequency – Hz
PSRR – Power Supply Rejection Ratio – dB
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
1k 10k 10M 100M1M100k
–40
–20
0
–30
–10
–80
–60
–70
–50
VCC = ±15 V , ±5 V
Figure 16
TA – Free-Air Temperature – °C
PSRR – Power Supply Rejection Ratio – dB
POWER SUPPLY REJECTION RATIO
vs
FREE-AIR TEMPERATURE
–40 –20 0 804020
88
84
80
72
86
82
90
60 100
78
74
76
VCC = –15 V
VCC = 15 V
Figure 17
OUTPUT VOLTAGE SWING
vs
SUPPLY VOLTAGE
±4 ±6 ±8 ±10 ±16
VCC – Supply Voltage – V
±14±12
30
20
10
0
25
15
5
V
O(PP)
– Output Voltage Swing – V
RL = 1 kΩ
RL = 150 Ω
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
–40 –20 0 20 80
TA – Free-Air Temperature – °C
6040
7
5
4
8
6
9
10
I
CC
– Supply Current – mA
100
VCC = ±15 V
VCC = ±5 V
Figure 19
NOISE SPECTRAL DENSITY
vs
FREQUENCY
10 100 1k 10k
f – Frequency – Hz
100k
140
0
180
100
60
E
nv
– Noise Spectral Density –
nV/
Hz
160
120
80
20
40
TA = 25°C
Figure 20
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
1M
f – Frequency – MHz
THD – Total Harmonic Distortion – dB
10M
100k
–50
–70
–90
–110
–40
–60
–80
–100
2nd Harmonic
Gain = 2
VCC = ±15 V
RL = 150 Ω
3rd Harmonic
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
1M
f – Frequency – MHz
THD – Total Harmonic Distortion – dB
10M
100k
–50
–70
–90
–110
–40
–60
–80
–100
2nd Harmonic
Gain = 2
VCC = ±5 V
RL = 150 Ω
3rd Harmonic
Figure 21
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
theory of operation
The THS406x is a high speed, operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V , dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of
several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 22.
IN– (2)
IN+ (3)
NULL (1) NULL (8)
(6) OUT
(4) VCC–
(7) VCC+
Figure 22. THS4061 Simplified Schematic
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
offset nulling
The THS4061 has very low input offset voltage for a high-speed amplifier . However, if additional correction is
required, an offset nulling function has been provided. By placing a potentiometer between terminals 1 and 8
and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in
Figure 23.
_
+
THS4061
VCC–
VCC+
0.1 µF
0.1 µF
10 kΩ
Figure 23. Offset Nulling Schematic
optimizing unity gain response
Internal frequency compensation of the THS406x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 270 Ω should
be used as shown in Figure 24. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
_
+
THS406x
270 Ω
Input
Output
Figure 24. Noninverting, Unity Gain Schematic
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS406x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 25. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
+
_
THS406x
C
LOAD
510 Ω
Input
Output
510 Ω
20 Ω
Figure 25. Driving a Capacitive Load
circuit layout considerations
In order to achieve the levels of high frequency performance of the THS406x, it is essential that proper
printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below.
In addition, a THS406x evaluation board is available to use as a guide for layout or for evaluating the device
performance.
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
circuit layout considerations (continued)
D
Surface-mount passive components – Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance
of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the
small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both
stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths
be kept as short as possible.
evaluation board
An evaluation board is available for the THS4061 (literature number SLOP226) and THS4062 (literaure number
SLOP235). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 26. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. To order the
evaluation board contact your local TI sales office or distributor. For more detailed information, refer to the
THS4061 EVM User’s Manual
(literature number SLOU038) or the
THS4062 EVM User’s Manual
(literature
number SLOU040)
_
+
THS4061
VCC–
VCC+
C1
6.8 µF
C4
0.1 µF
C2
6.8 µF
C3
0.1 µF
R4
1 kΩ
R2
1 kΩ
R3
49.9 Ω
R5
49.9 Ω
R1
49.9 Ω
IN–
IN+
NULL
OUT
NULL
+
+
Figure 26. THS4061 Evaluation Board Schematic
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
Thermal Pad
(See Note D)
0,15 NOM
Gage Plane
4073271/A 01/98
4,98
0,25
5
3,05
4,78
2,95
8
4
3,05
2,95
1
0,38
0,15
0,05
1,07 MAX
Seating Plane
0,10
0,65
M
0,25
0°–6°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,20)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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