查询THS4011供应商
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
D
Very High Speed
– 290 MHz Bandwidth (G = 1, –3 dB)
– 310 V/µs Slew Rate
– 37 ns Settling Time (0.1%)
D
Very Low Distortion
– THD = –80 dBc (f = 1 MHz, R
D
110 mA Output Current Drive (Typical)
D
7.5 nV/√Hz Voltage Noise
D
Excellent Video Performance
= 150 Ω)
L
– 70 MHz Bandwidth (0.1 dB, G = 1)
– 0.006% Differential Gain Error
– 0.01° Differential Phase Error
D
±5 V to ±15 V Supply Voltage
D
Available in Standard SOIC, MSOP
PowerPAD, JG, or FK Packages
D
Evaluation Module Available
description
The THS401 1 and THS4012 are very high speed,
single/dual, voltage feedback amplifiers ideal for
a wide range of applications. The devices offer
very good ac performance with 290-MHz
bandwidth, 310-V/µs slew rate, and 37-ns settling
time (0.1%). These amplifiers have a high output
drive capability of 110 mA and draw only 7.8-mA
supply current per channel. For applications
requiring low distortion, the THS4011/12 operate
with a total harmonic distortion (THD) of –80 dBc
at f = 1 MHz. For video applications, the
THS401 1/12 offer 0.1 dB gain flatness to 70-MHz,
0.006% differential gain error, and 0.01°
differential phase error.
JG, D AND DGN PACKAGE
NULL
V
NC – No internal connection
THS4011
(TOP VIEW)
1
IN–
2
IN+
3
4
CC–
†
This device is in the Product Preview stage of development.
Please contact your local TI sales office for availability.
NULL
8
V
7
CC+
OUT
6
5
NC
Cross Section View Showing
PowerPAD Option (DGN)
FK PACKAGE
(TOP VIEW)
NC
NC
4
IN–
5
NC
6
IN+
7
NC
8
NC
1OUT
1IN–
1IN+
–V
THS4011
NULLNCNULL
NCNCNC
CC–
V
THS4012
D AND DGN† PACKAGE
(TOP VIEW)
1
2
3
4
CC
NC
1920132
NC
18
V
17
CC+
NC
16
OUT
15
NC
14
1312119 10
8
7
6
5
V
CC+
2OUT
2IN–
2IN+
DEVICE DESCRIPTION
THS4011/2
THS4031/2
THS4061/2
CAUTION: THE THS4011 AND THS4012 provide ESD protection circuitry . However , permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
RELATED DEVICES
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
DISTORTION
vs
VCC = ± 15 V
RL = 150 Ω
G = 2
f – Frequency – Hz
†
‡
‡
FREQUENCY
2nd Harmonic
3rd Harmonic
CERAMIC
DIP
(JG)
— — TIABD THS4012EVM
— — TIABZ —
–40
–50
–60
–70
–80
Distortion – dB
–90
–100
–110
100k 1M 10M
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
0°C to
70°C
–40°C to
85°C
–55°C to
125°C
NUMBER OF
CHANNELS
1 THS4011CD THS4011CDGN — — TIACM THS4011EVM
2 THS4012CD THS4012CDGN
1 THS4011ID THS4011IDGN — — TIACN —
2 THS4012ID THS4012IDGN
1 — — THS4011MJG THS4011MFK — —
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS401 1CDGNR).
‡
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
PLASTIC
SMALL
OUTLINE
(D)
PLASTIC
†
MSOP
(DGN)
CHIP
CARRIER
(FK)
MSOP
SYMBOL
EVALUATION
MODULE
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
Null
1
IN–
IN+
2
3
+
Figure 1. THS4011 – Single Channel
8
–
V
CC
6
OUT
THS4011, THS4012
SLOS216B – JUNE 1999 – FEBRUARY 2000
1IN–
1IN+
2IN–
2IN+
2
3
6
5
8
–
+
–
+
4
–V
CC
1
7
Figure 2. THS4012 – Dual Channel
1OUT
2OUT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
THS4011, THS4012
PACKAGE
JA
JC
A
Suppl
oltage, V
V
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC ±16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI ±V
Output current, IO 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, T
Operating free-air temperature, TA, THS401xC 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds, D, DGN package 300°C. . . . . . . . . . . . . . .
Lead temperature, 1,6 mm (1/16 inch) from case for 60 seconds, JG package 300°C. . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J
THS401xI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS4011M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
DISSIPATION RATING TABLE
θ
(°C/W)
D 167
‡
DGN
JG 119 28 1050 mW
FK 87.7 20 1375 mW
†
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed
High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
‡
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
PC. For further information, refer to
†
58.4 4.7 2.14 W
Application Information
θ
(°C/W)
38.3 740 mW
section of this data sheet.
T
= 25°C
POWER RATING
†
CC
recommended operating conditions
pp
y v
Operating free-air temperature, T
CC
A
MIN NOM MAX UNIT
Split supply ±4.5 ±16
Single supply 9 32
C suffix 0 70
I suffix –40 85
M suffix –55 125
°C
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
†
Unity-gain bandwidth (–3 dB)
Gain
1
MH
BW
Bandwidth for 0.1 dB flatness
Gain
1
MH
Full power bandwidth (see Note 2)
MH
SR
Slew rate
Gain
R
150 Ω
V/µs
Settling time to 0.1%
V
Gain
1
ns
t
Settling time to 0.01%
V
Gain
1
ns
†
Differential gain error
R
150 Ω
Differential phase error
R
150 Ω
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics, VCC = ±15 V, RL = 150 Ω, TA = 25°C, (unless otherwise noted)
dynamic performance
THS4011C/I,
PARAMETER
=
=
p
s
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
VCC = ±15 V, RL = 150 Ω V
VCC = ±5 V, RL = 150 Ω, V
= –1,
= –2.5 V to 2.5 V,
I
= –2.5 V to 2.5 V,
I
TEST CONDITIONS
=
L
= –
= –
VCC = ±15 V 290
VCC = ±5 V 270
VCC = ±15 V 70
VCC = ±5 V 35
= 20 V, 4.9
O(PP)
= 5 V, 16
O(PP)
VCC = ±15 V 310
VCC = ±5 V 260
VCC = ±15 V 37
VCC = ±5 V 35
VCC = ±15 V 90
VCC = ±5 V 70
THS4012C/I
MIN TYP MAX
UNIT
z
z
z
noise/distortion performance
PARAMETER
THD Total harmonic distortion
V
I
n
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
Input voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 7.5 nV/√Hz
n
Input current noise VCC = ±5 V or ±15 V, f = 10 kHz 1 pA/√Hz
p
VCC = ±15 V,
V
= 2 V
O(PP)
Gain = 2,
=
L
NTSC
Gain = 2,
=
L
NTSC
,
,
TEST CONDITIONS
THS4011C/I,
THS4012C/I
MIN TYP MAX
fc = 1 MHz,
VCC = ±15 V 0.01%
VCC = ±5 V 0.01%
VCC = ±15 V 0.01°
VCC = ±5 V 0.001°
–80 dBc
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
THS4011, THS4012
†
V
±10 V
V/mV
Open loop gain
V
V/mV
VIOInput offset voltage
V
±15 V
mV
IIBInput bias current
V
±5 V or ±15 V
A
IIOInput offset current
V
±15 V
nA
†
V
Common-mode input voltage range
V
CC
,
CMRR
Common-mode rejection ratio
CC
,
dB
†
R
kΩ
VOOutput voltage swing
V
IOOutput current
R
mA
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
dc performance
THS4011C/I,
PARAMETER
VCC = ±15 V,
=
O
p
p
p
Input offset voltage drift 15 µV/°C
p
p
Offset current drift VCC = ±5 V or ±15 V 0.3 nA/°C
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
RL = 1 kΩ
VCC = ±5 V,
O
RL = 250 Ω
CC
CC
CC
,
= ±2.5 V,
= ±5 V or
=
= ±5 V or
TEST CONDITIONS
TA = 25°C 10 25
TA = full range 8
TA = 25°C 7 12
TA = full range 5
TA = 25°C 1 6
TA = full range 8
TA = 25°C 2 6
TA = full range 8
TA = 25°C 25 250
TA = full range 400
THS4012C/I
MIN TYP MAX
UNIT
µ
input characteristics
PARAMETER
ICR
R
C
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
Input resistance 2 MΩ
I
Input capacitance 1.2 pF
I
p
VCC = ±15 V ±13 ±14.1
VCC = ±5 V ±3.8 ±4.3
V
= ±15 V,
VIC = ±12 V
V
= ±5 V,
VIC = ±2.5 V
TEST CONDITIONS
output characteristics
PARAMETER
VCC = ±15 V
p
p
I
OS
R
O
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
Short-circuit output current VCC = ±15 V 150 mA
Output resistance Open loop 12 Ω
VCC = ±5 V
VCC = ±15 V RL = 250 Ω ±12 ±13
VCC = ±5 V RL = 150 Ω ±3 ±3.4
= 20 Ω,
L
TEST CONDITIONS
THS4011C/I,
THS4012C/I
MIN TYP MAX
TA = 25°C 82 110 dB
TA = full range 77 dB
TA = 25°C 90 95
TA = full range 83
THS4011C/I,
THS4012C/I
MIN TYP MAX
= 1
L
VCC = ±15 V 70 110
VCC = ±5 V 50 75
±13 ±13.5
±3.4 ±3.7
UNIT
UNIT
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
†
VCCSuppl
oltage
V
V
±15 V
ICCSupply current (each amplifier)
mA
V
V
PSRR
Power supply rejection ratio
V
±15 V
dB
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
power supply
THS4011C/I,
PARAMETER
pp
y v
pp
pp
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
p
Dual supply ±4.5 ±16.5
Single supply 9 33
CC
CC
CC
TEST CONDITIONS
=
= ±5
= ±5 V to
TA = 25°C 7.8 9.5
TA = full range 11
TA = 25°C 6.9 8.5
TA = full range 10
TA = 25°C 75 83
TA = full range 68
THS4012C/I
MIN TYP MAX
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
THS4011, THS4012
PARAMETER
TEST CONDITIONS
†
UNIT
BW
Full power bandwidth (see Note 1)
MH
Settling time to 0.1%
V
Gain
1
ns
t
Settling time to 0.01%
V
Gain
1
ns
PARAMETER
TEST CONDITIONS
†
UNIT
Differential gain error
R
150 Ω
%
Differential phase error
R
L
150 Ω
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics, VCC = ±15 V, RL = 150 Ω, TA = 25°C, (unless otherwise noted)
dynamic performance
THS4011M
MIN TYP MAX
Unity-gain bandwidth Closed loop, RL = 1 kΩ VCC = ±15 V *160 200 MHz
VCC = ±15 V 70
Bandwidth for 0.1 dB flatness Gain = 1
p
SR Slew rate VCC = ±15 V, RL = 1 kΩ *300 400 V/µs
s
†
Full range = –55°C to 125°C for the M suffix.
*This parameter is not tested.
NOTE 1: Full pwer bandwidth = slew rate/2π V
VCC = ±15 V, RL = 150 Ω, V
VCC = ±5 V, RL = 150 Ω, V
= –2.5 V to 2.5 V,
I
= –2.5 V to 2.5 V,
I
.
(PP)
= –
= –
noise/distortion performance
THD Total harmonic distortion
V
I
n
†
Full range = –55°C to 125°C for the M suffix.
Input voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 7.5 nV/√Hz
n
Input current noise VCC = ±5 V or ±15 V, f = 10 kHz 1 pA/√Hz
p
VCC = ±15 V, fc = 1 MHz,
V
= 1 V
O(PP)
Gain = 2,
L
NTSC
Gain = 2,
NTSC
=
=
,
,
VCC = ±5 V 35
VCC = ±2.5 V 30
= 20 V 2.5
O(PP)
= 20 V 8
O(PP)
VCC = ±15 V 37
VCC = ±5 V 35
VCC = ±15 V 90
VCC = ±5 V 70
THS4011M
MIN TYP MAX
–80 dBc
VCC = ±15 V 0.006
VCC = ±5 V 0.001
VCC = ±15 V 0.01°
VCC = ±5 V 0.002°
MHz
z
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
†
UNIT
Open loop gain
VIOInput offset voltage
V
±15 V
mV
IIBInput bias current
V
±15 V
A
PARAMETER
TEST CONDITIONS
†
UNIT
V
Common-mode input voltage range
V
CMRR
Common-mode rejection ratio
dB
PARAMETER
TEST CONDITIONS
†
UNIT
R
kΩ
VOOutput voltage swing
V
IOOutput current
R
20 Ω
mA
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
dc performance
THS4011M
MIN TYP MAX
p
p
p
Input offset voltage drift VCC = ±5 V or ±15 V 15 µV/°C
p
I
IO
†
Full range = –55°C to 125°C for the M suffix.
Input offset current VCC = ±5 V or ±15 V 25 250 nA
Offset current drift VCC = ±5 V or ±15 V TA = 25°C 0.3 nA/°C
input characteristics
ICR
R
C
†
Full range = –55°C to 125°C for the M suffix.
Input resistance 2 MΩ
I
Input capacitance 1.2 pF
I
p
VCC = ±15 V, VO = ±10 V,
RL = 1 kΩ
VCC = ±5 V, VO = ±2.5 V,
RL = 1 kΩ
= ±5 V or
CC
= ±5 V or
CC
VCC = ±15 V ±13 ±14.1
VCC = ±5 V ±3.8 ±4.3
VCC = ±15 V, VIC = ±12 V 75 90
VCC = ±5 V, VIC = ±2.5 V 84 95
TA = full range 6 14 V/mV
TA = full range 5 10 V/mV
TA = 25°C 2 6
TA = full range 2 8
TA = 25°C 2 6
TA = full range 4 8
THS4011M
MIN TYP MAX
µ
output characteristics
p
p
I
OS
R
O
†
Full range = –55°C to 125°C for the M suffix.
Short-circuit output current VCC = ±15 V TA = 25°C 150 mA
Output resistance Open loop 12 Ω
THS4011M
MIN TYP MAX
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V RL = 250 Ω ±12 ±13
VCC = ±5 V RL = 150 Ω ±3 ±3.4
VCC = ±15 V
VCC = ±5 V
L
L
= 1
=
±13 ±13.5
±3.4 ±3.7
70 115
50 75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
THS4011, THS4012
PARAMETER
TEST CONDITIONS
†
UNIT
VCCSuppl
oltage
V
V
±15 V
ICCQuiescent current
mA
V
V
PSRR
Power supply rejection ratio
V
±5 V to ±15 V
dB
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
power supply
THS4011M
MIN TYP MAX
pp
y v
pp
†
Full range = –55°C to 125°C for the M suffix.
PARAMETER MEASUREMENT INFORMATION
Dual supply ±4.5 ±16.5
Single supply 9 33
CC
CC
CC
=
= ±5
=
TA = 25°C 7.8 9.5
TA = full range 11
TA = 25°C 6.9 8.5
TA = full range 10
TA = 25°C 80 86
TA = full range 78 83
1.5 kΩ
V
I1
50 Ω
1.5 kΩ
_
+
CH1
1.5 kΩ 1.5 kΩ
V
150 Ω
O1
V
O2
150 Ω
CH2
Figure 3. THS4012 Crosstalk Test Circuit
_
+
50 Ω
V
I2
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
1.4
1.2
1
0.8
0.6
0.4
– Input Offset Voltage – mV
IO
V
0.2
0
–40 –20 0 20 40 60
TA – Free-AIR Temperature – _C
VCC = ±15 V
80 100
Figure 4
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
14
± V
13.5
13
12.5
12
4.5
VCC = ± 5 V
RL = 1 kΩ
4
3.5
Maximum Output Voltage Swing –
3
2.5
–40 –20 0 20 40 60 80 100
TA – Free-Air Temperature – _C
VCC = ± 15 V
RL = 1 kΩ
VCC = ± 15 V
RL = 250 Ω
VCC = ± 5 V
RL = 150 Ω
Figure 7
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
3
2.5
2
1.5
1
Iib – Input Bias Current – uA
0.5
0
–40 –20 0 20 40 60 80
TA – Free-Air Temperature – _C
VCC = ±15 V or ±5 V
Figure 5
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
15
TA = 25° C
13
11
9
7
Input Common-Mode Range – V
–
5
IC
V
3
57 9111315
± VCC – Supply Voltage – V
Figure 8
100
OUPUT VOLTAGE
vs
SUPPLY VOLTAGE
14
TA = 25° C
12
10
8
6
– Output Voltage Swing –
|
O
4
|V V
2
57 9111315
RL = 1 kΩ
RL = 150 Ω
± VCC – Supply Voltage – V
Figure 6
PSRR
vs
100
90
80
70
60
50
40
30
20
10
PSRR – Power-Supply Rejection Ratio – dB
0
1k 10k 100k 1M
FREQUENCY
VCC = ±15 V or ±5 V
10M
f – Frequency – Hz
Figure 9
100M
CMRR
vs
FREQUENCY
120
100
80
60
40
20
CMRR – Common-Mode Rejection Ratio – dB
VCC ±5V
VCC ±15V
0
1k 10k 100k 1M
f – Frequency – Hz
10M
Figure 10
100M
CROSSTALK
vs
FREQUENCY
0
VCC ±15V
–10
–20
–30
–40
VI = CH2
–50
VO = CH1
Crosstalk – dB
–60
–70
–80
–90
100k 10M 100M
VI = CH1
VO = CH2
1M
f – Frequency – Hz
Figure 11
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Open0Loop Gain – dB
1G
OPEN-LOOP GAIN RESPONSE
100
VCC ±15V
80
VCC ±5V
60
40
20
0
–20
10K
1k 100K 1M
f – Frequency – Hz
10M 100M 1G
Figure 12
11
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
TYPICAL CHARACTERISTICS
DISTORTION
vs
FREQUENCY
–40
VCC = ± 15 V
RL = 1 kΩ
–50
G = 2
–60
–70
–80
Distortion – dB
–90
–100
–110
100k 1M 10M
2nd Harmonic
3rd Harmonic
f – Frequency – Hz
Figure 13
DISTORTION
vs
FREQUENCY
–40
VCC = ± 5 V
RL = 150 Ω
–50
G = 2
–60
–70
–80
Distortion – dB
–90
–100
–110
100k 1M 10M
2nd Harmonic
3rd Harmonic
f – Frequency – Hz
Figure 16
NOISE SPECTRAL DENSITY
FREQUENCY
100
vs
DISTORTION
vs
FREQUENCY
–40
VCC = ± 5 V
RL = 1 kΩ
–50
G = 2
–60
–70
–80
Distortion – dB
–90
–100
–110
100k 1M 10M
f – Frequency – Hz
2nd Harmonic
3rd Harmonic
Figure 14
OUTPUT AMPLITUDE
vs
5
0
–5
–10
–15
Output Amplitude – dB
0
–20
–25
100k 1M 10M 100M
FREQUENCY
VCC = ± 15 V
RL = 150 Ω
G = 1
f – Frequency – Hz
Rf = 270 Ω
Rf = 100 Ω
Figure 17
–40
VCC = ± 15 V
RL = 150 Ω
–50
G = 2
–60
–70
–80
Distortion – dB
–90
–100
–110
100k 1M 10M
OUTPUT AMPLITUDE
5
0
–5
–10
Output Amplitude – dB
–15
VCC = ± 5 V
RL = 150 Ω
G = 1
–20
1G
100k 1M 10M 100M
DIFFERENTIAL PHASE
NUMBER OF 150-Ω LOADS
0.35°
Gain = 2
RF = 1 kΩ
0.3°
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
0.25°
DISTORTION
vs
FREQUENCY
2nd Harmonic
3rd Harmonic
f – Frequency – Hz
Figure 15
vs
FREQUENCY
Rf = 270 Ω
Rf = 100 Ω
1G
f – Frequency – Hz
Figure 18
vs
VCC = ± 15 V
12
10
Noise Spectral Density
VCC = ±15 V or ±5 V
1
10 100 1k
f – Frequency – Hz
Figure 19
10k
100k
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.2°
0.15°
Differential Phase
0.1°
0.05°
0°
1234
Number of 150-Ω Loads
VCC = ± 5 V
Figure 20
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
TYPICAL CHARACTERISTICS
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.4°
Gain = 2
RF = 1 kΩ
0.35°
40 IRE-PAL Modulation
0.3°
Worst Case ± 100 IRE Ramp
0.25°
0.2°
0.15°
Differential Phase
0.1°
0.05°
0°
1234
VCC = ± 15 V
VCC = ± 5 V
Number of 150-Ω Loads
Figure 21
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.05
Gain = 2
RF = 1 kΩ
40 IRE-NTSC Modulation
0.04
Worst Case ± 100 IRE Ramp
0.03
0.02
Differential Gain – %
VCC = ± 15 V
0.01
VCC = ± 5 V
0
1234
Number of 150-Ω Loads
Figure 22
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.06
Gain = 2
RF = 1 kΩ
0.05
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.04
0.03
0.02
Differential Gain – %
0.01
VCC = ± 15 V
VCC = ± 5 V
0
1234
Number of 150-Ω Loads
Figure 23
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THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
theory of operation
The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V , dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.
(7) VCC+
(6) OUT
IN– (2)
IN+ (3)
(4) VCC–
NULL (1) NULL (8)
Figure 24. THS4011 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:
• e
= Amplifier internal voltage noise (nV/√Hz)
n
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• e
= Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
Rx
14
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APPLICATION INFORMATION
noise calculations and noise figure (continued)
THS4011, THS4012
SLOS216B – JUNE 1999 – FEBRUARY 2000
e
)
ǒ
IN
Rs
)
R
e
ni
The total equivalent input noise density (eni) is calculated by using the following equation:
eni+
Where:
S
Ǹ
2
ǒ
Ǔ
e
n
k = Boltzmann’s constant = 1.380658 × 10
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and R
e
n
IN+
IN–
Figure 25. Noise Model
2
Ǔ
R
)ǒIN–
S
Noiseless
+
_
e
Rf
e
Rg
R
G
ǒRFø
R
–23
G
e
no
R
F
2
Ǔ
Ǔ
)
G
4kTRs)
4kTǒRFø
Ǔ
R
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
R
eno+
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the
Circuits Applications Report
eniAV+
ǒ
e
ni
(literature number SLVA043).
F
)
Ǔ
(noninverting case)
R
G
Noise Analysis
section in
Operational Amplifier
1
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THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
ȱ
NF
+
10log
ȧ
ȧ
ǒ
e
Ȳ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
ȱ
ȧ
NF
+
10log
ȧ
ȧ
1
ȧ
ȧ
Ȳ
Figure 26 shows the noise figure graph for the THS401x.
e
Rs
)
ȳ
2
ni
ȧ
ȧ
2
Ǔ
ȴ
ȡ
ȧ
Ȣ
2
ǒ
Ǔ
e
)ǒIN
n
)
4kTR
S
2
ȳ
ȣ
Ǔ
R
ȧ
S
ȧ
Ȥ
ȧ
ȧ
ȧ
ȧ
ȴ
NOISE FIGURE
vs
SOURCE RESISTANCE
30
f = 10 kHz
TA = 25°C
25
20
15
Noise Figure – dB
10
5
0
10 100
Source Resistance – Ω
Figure 26. Noise Figure vs Source Resistance
1 k 100 k
10 k
16
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THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS401x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 27. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1.3 kΩ
1.3 kΩ
Input
_
THS401x
+
20 Ω
C
LOAD
Output
Figure 27. Driving a Capacitive Load
offset nulling
The THS401x has very low input offset voltage for a high-speed amplifier . However, if additional correction is
required, an offset nulling function has been provided on the THS4011. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply . This
is shown in Figure 28.
VCC+
0.1 µF
+
THS4011
_
10 kΩ
0.1 µF
VCC–
Figure 28. Offset Nulling Schematic
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290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
R
G
IB–
VOO+
+
V
I
R
S
I
IB+
R
1
) ǒ
F
Ǔ
"
I
Ǔ
IB
R
G
)
V
ǒ
IO
Figure 29. Output Offset Voltage Model
–
+
R
1
) ǒ
F
R
G
R
ǒ
S
V
O
Ǔ
"
I
Ǔ
IB–RF
optimizing unity gain response
Internal frequency compensation of the THS401x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 100 Ω should
be used as shown in Figure 30. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
THS401x
_
Output
18
100 Ω
Figure 30. Noninverting, Unity Gain Schematic
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290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer
(see Figure 31).
R
G
R
F
–
C1
R
F
R
G
+
ǒ
Ǔ
1)sR1C1
f
1
–3dB
Ǔ
V
I
R1
V
O
+ ǒ
1
V
I
)
+
V
O
1
2pR1C1
Figure 31. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
V
I
R2R1
C2
R
G
+
_
R
F
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
1
+
2pRC
R
F
1
2 –
(
)
Q
R
f
–3dB
G
=
Figure 32. 2-Pole Low-Pass Sallen-Key Filter
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THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS401x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS401x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
D
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerP AD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerP AD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
20
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
THS4011, THS4012
SLOS216B – JUNE 1999 – FEBRUARY 2000
Side View (a)
DIE
End View (b) Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Thermal
Pad
Figure 33. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 34. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 34. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter . Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS401xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
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21
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θJA, is about 58.4_C/W. For comparison, the non-PowerPAD version of
the THS401x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 35 and
is calculated by the following formula:
T
MAX–TA
Where:
ǒ
PD+
P
= Maximum power dissipation of THS401x IC (watts)
D
T
= Absolute maximum junction temperature (150°C)
MAX
T
= Free-ambient air temperature (°C)
A
θ
= θ
JA
JC
+ θ
q
θJC= Thermal coefficient from junction to case
θCA= Thermal coefficient from case to ambient air (°C/W)
Ǔ
JA
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
3
2.5
SOIC Package
High-K Test PCB
θJA = 98°C/W
2
1.5
1
Maximum Power Dissipation – W
NOTE A: Results are with no air flow and PCB size = 3”× 3”
SOIC Package
0.5
Low-K Test PCB
θJA = 167°C/W
0
–40 –20 0 20 40
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
TA – Free-Air Temperature – °C
TJ = 150°C
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
60 80 100
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerP AD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief,
PowerPAD Thermally Enhanced Package.
This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
22
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THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially muti-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. When using V
generally not a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is
severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how
the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But,
the device should always be soldered to a copper plane to fully use the heat dissipation properties of the
PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As
more trace and copper area is placed around the device, θ
decreases and the heat dissipation capability
JA
increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier
package (THS4012), the sum of the RMS output currents and voltages should be used to choose the proper
package.
= ±5 V, there is
CC
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
200
VCC = ± 5 V
Tj = 150°C
180
TA = 50°C
160
140
120
100
SO-8 Package
80
θJA = 167°C/W
Low-K Test PCB
60
40
– Maximum RMS Output Current – mA
O
I
20
||
0
012 3
| VO | – RMS Output Voltage – V
Maximum Output
Current Limit Line
Package With
θJA < = 120°C/W
Safe Operating
Area
45
Figure 36
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
TJ = 150°C
TA = 50°C
Maximum Output
DGN Package
θJA = 58.4°C/W
100
– Maximum RMS Output Current – mA
O
I
||
10
0369
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
| VO | – RMS Output Voltage – V
Current Limit Line
VCC = ± 15 V
SO-8 Package
θJA = 98°C/W
High-K Test PCB
Safe Operating
Area
12 15
Figure 37
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23
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
200
180
160
140
120
100
80
60
40
– Maximum RMS Output Current – mA
O
I
20
||
Package With
θJA ≤ 60°C/W
SO-8 Package
θJA = 98°C/W
High-K Test PCB
0
012 3
| VO | – RMS Output Voltage – V
Maximum Output
Current Limit Line
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Safe Operating Area
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
45
Figure 38
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
100
10
– Maximum RMS Output Current – mA
O
I
||
DGN Package
θJA = 58.4°C/W
Safe Operating Area
1
0369
| VO | – RMS Output Voltage – V
Maximum Output
Current Limit Line
SO-8 Package
θJA = 98°C/W
High-K Test PCB
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
12 15
Figure 39
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
evaluation board
An evaluation board is available for the THS401 1 (literature number SLOP128) and THS4012 (literature number
SLOP230). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the THS401 1 evaluation board is shown in Figure 40. The circuitry
has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For
more information, please refer to the
EVM User’s Guide
(literature number SLOU041) T o order the evaluation board contact your local TI sales office
or distributor.
THS401 1 EVM User’s Guide
VCC+
C2
0.1 µF
(literature number SLOU028) or the
+
C1
6.8 µF
THS4012
IN+
IN–
R3
49.9 Ω
R1
1 kΩ
NULL
+
THS4011
_
NULL
R5
1 kΩ
R4
49.9 Ω
C4
0.1 µF
VCC–
+
Figure 40. THS4011 Evaluation Board
R2
49.9 Ω
OUT
C3
6.8 µF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
14
1
0.069 (1,75) MAX
0.050 (1,27)
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
8
7
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
PINS **
DIM
A MAX
A MIN
0.008 (0,20) NOM
Gage Plane
0°–8°
8
0.197
(5,00)
0.189
(4,80)
14
0.344
(8,75)
0.337
(8,55)
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
4040047/D 10/96
16
0.394
(10,00)
0.386
(9,80)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,65
8
1
1,07 MAX
3,05
2,95
0,38
0,25
5
3,05
2,95
4
Seating Plane
0,15
0,05
0,25
4,98
4,78
M
0,10
Thermal Pad
(See Note D)
0,15 NOM
0°–6°
Gage Plane
0,25
0,69
0,41
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
4073271/A 04/98
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
20
22
23
24
25
19
21
12826 27
1314151618 17
0.020 (0,51)
0.010 (0,25)
12
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358
(9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
28
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
0.063 (1,60)
0.015 (0,38)
0.100 (2,54)
8
1
5
4
0.065 (1,65)
0.045 (1,14)
0.020 (0,51) MIN
0.280 (7,11)
0.245 (6,22)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0.310 (7,87)
0.290 (7,37)
Seating Plane
0°–15°
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4040107/C 08/96
29
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