Texas Instruments THS1206CDA, THS1206QDAR, THS1206QDA, THS1206IDAR, THS1206IDA Datasheet

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THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

High-Speed 6 MSPS ADC

4 Single-Ended or 2 Differential Inputs

Simultaneous Sampling of 4 Single-Ended Signals or 2 Differential Signals or Combination of Both

Differential Nonlinearity Error: ±1 LSB

Integral Nonlinearity Error: ±1.5 LSB

Signal-to-Noise and Distortion Ratio: 68 dB at fI = 2 MHz

Auto-Scan Mode for 2, 3, or 4 Inputs

3-V or 5-V Digital Interface Compatible

Low Power: 216 mW Max

5-V Analog Single Supply Operation

Internal Voltage References . . . 50 PPM/°C and ±5% Accuracy

Glueless DSP Interface

Parallel µC/DSP Interface

Integrated FIFO

Available in TSSOP Package

applications

Radar Applications

Communications

Control Applications

High-Speed DSP Front-End

Automotive Applications

description

The THS1206 is a CMOS, low-power, 12-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS1206 consists of four analog inputs, which are sampled simultaneously . These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.

An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In single conversion mode, a single and simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal (CONVST

). The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS1206. The internal clock oscillator is switched off in continuous conversion mode.

The THS1206C is characterized for operation from 0°C to 70°C, the THS1206I is characterized for operation from –40°C to 85°C, the THS1206Q is characterized to meet the rigorous requirements of the automotive environment from –40°C to 125°C, and the THS1206M is characterized for operation over the full military temperature range of –55°C to 125°C.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

D0 D1 D2 D3 D4 D5

BGND

D6 D7 D8

D9 D10/RA0 D11/RA1

CONV_CLK (CONVST

)

DATA_AV

AINP AINM BINP BINM REFIN REFOUT REFP REFM AGND AV

CS0 CS1 WR

(R/W) RD DV

DGND

DA PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICE

TSSOP

(DA)

0°C to 70°C THS1206CDA

–40°C to 85°C THS1206IDA –40°C to 125°C THS1206QDA –55°C to 125°C THS1206MDA

functional block diagram

Logic

and

Control

12 Bit

Pipeline

ADC

S/H

Single Ended and/or

Differential

MUX

–

REFP

REFM

1.5 V

3.5 V

1.225 V REF

FIFO

16 × 12

Buffers

2.5 V

Control

AGND DGND

REFOUT

DATA_AV

D0 D1

D2 D3 D4 D5

D6 D7 D8 D9 D10/RA0 D11/RA1

BGND

REFP

REFM

AINP

AINM

BINP

BINM

CONV_CLK (CONVST

) CS0 CS1

WR (R/W)

REFIN

THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AINP 32 I Analog input, single-ended or positive input of differential channel A AINM 31 I Analog input, single-ended or negative input of differential channel A BINP 30 I Analog input, single-ended or positive input of differential channel B BINM 29 I Analog input, single-ended or negative input of differential channel B AV

23 I Analog supply voltage AGND 24 I Analog ground BV

7 I Digital supply voltage for buffer BGND 8 I Digital ground for buffer CONV_CLK (CONVST) 15 I Digital input. This input is used to apply an external conversion clock in continuous conversion

mode. In single conversion mode, this input functions as the conversion start (CONVST

) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs.

CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level

information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. See Table 14.

DGND 17 I Digital ground. Ground reference for digital circuitry. DV

18 I Digital supply voltage D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB D10/RA0 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control

D11/RA1 14 I/O/Z Digital input, output (D1 1 = MSB). The data line D11 is also used as an address line (RA1) for

the control register . This is required for writing to control register 0 and control register 1. See Table 8.

REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin

be connected to the reference output REFOUT.

REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal

reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9.

REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal

reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9.

REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The

reference output requires a capacitor of 10 µF to AGND for filtering and stability .

†

19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a

digital input, active low as a data read select from the processor. See timing section.

WR (R/W)

†

20 I This input is programmable. It functions as a read-write input R/W and can also be configured

as a write-only input WR

, which is active low and used as data write select from the processor.

In this case, the RD

input is used as a read input from the processor. See timing section.

†

The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, DGND to DVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BGND to BVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to AV

–0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range AGND – 0.3 V to AVDD + 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage –0.3 + AGND to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range,T

THS1206C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS1206I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS1206Q –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS1206M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

≤ 25°C DERATING FACTOR T

= 70°C T

= 85°C T

= 125°C

PACKAGE

POWER RATING ABOVE TA = 25°C

‡

POWER RATING

DA 1453 mW 11.62 mW/°C 930 mW 756 mW 291 mW

‡

This is the inverse of the traditional junction-to-ambient thermal resistance (R

θJA

). Thermal resistances are not production tested and are for

informational purposes only.

recommended operating conditions

power supply

MIN NOM MAX UNIT

4.75 5 5.25

Supply voltage

3 3.3 5.25

analog and reference inputs

MIN NOM MAX UNIT

Analog input voltage in single-ended configuration V

REFM

REFP

V Common-mode input voltage VCM in differential configuration 1 2.5 4 V External reference voltage,V

REFP

(optional) 3.5 AVDD–1.2 V

External reference voltage, V

REFM

(optional) 1.4 1.5 V

Input voltage difference, REFP – REFM 2 V

THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (continued)

digital inputs

MIN NOM MAX UNIT

BVDD = 3.3 V 2 V

High-level input voltage, V

BVDD = 5.25 V 2.6 V

BVDD = 3.3 V 0.6 V

Low-level input voltage, V

BVDD = 5.25 V 0.6 V Input CONV_CLK frequency DVDD = 3 V to 5.25 V 0.1 6 MHz CONV_CLK pulse duration, clock high, t

w(CONV_CLKH)

DVDD = 3 V to 5.25 V 80 83 5000 ns CONV_CLK pulse duration, clock low, t

w(CONV_CLKL)

DVDD = 3 V to 5.25 V 80 83 5000 ns

THS1206CDA 0 70

THS1206IDA –40 85

Operating free-air temperature, T

THS1206QDA –40 125

°C

THS1206MDA –55 125

electrical characteristics over recommended operating conditions, V

REF

= internal (unless

otherwise noted)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Digital inputs

High-level input current DVDD = digital inputs –50 50 µA

Low-level input current Digital input = 0 V –50 50 µA

Input capacitance 5 pF

Digital outputs

BVDD–0.5

VOHHigh-level output voltage

= 3.3 V,

BVDD–0.5

VpI

= –

50 µA

BVDD = 5 V

0.4

VOLLow-level output voltage

0.4

High-impedance-state output current CS1 = DGND, CS0 = DVDD –10 10 µA

Output capacitance 5 pF

Load capacitance at databus D0 – D11 30 pF

THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, V

REF

= internal (unless

otherwise noted) (continued)

dc specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 Bits

Accuracy

C and I suffix ±1.5

Integral nonlinearit

INL

Q and M suffix ±1.8

LSB

Differential nonlinearity , DNL ±1 LSB

After calibration in single-ended mode –15

†

15†mV

Offset error

After calibration in differential mode –5

†

5†mV

Gain error 1% FSR

Analog input

Input capacitance 15 pF Input leakage current V

AIN

= V

REFM

to V

REFP

±10 µA

Internal voltage reference

C and I suffix 3.33 3.5 3.67

Accurac

REFP

Q and M suffix

3.3 3.5 3.7

C and I suffix 1.42 1.5 1.58

Accurac

REFM

Q and M suffix

1.3 1.5 1.7

T emperature coef ficient 50 PPM/°C Reference noise 100 µV

C and I suffix 2.475 2.5 2.525

Accurac

REFOUT

Q and M suffix 2.3 2.5 2.7

Power supply

DDA

Analog supply current AVDD =5 V, BVDD = DVDD = 3.3 V 36 40 mA

DDD

Digital supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 0.5 1 mA

DDB

Buffer supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 1.5 4 mA

AVDD = 5 V,

C and I suffix 7

DD_P

Su ly current in ower-down mode

BVDD = DVDD = 3.3 V

Q and M suffix 10

Power dissipation AVDD = 5 V, DVDD = BVDD = 3.3 V 186 216 mW Power dissipation in power down AVDD = 5 V, DVDD = BVDD = 3.3 V 30 mW

†

Not production tested for M and Q suffix devices.

THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, V

REF

= internal, fs = 6 MHz,

= 2 MHz at –1dBFS (unless otherwise noted) (continued)

ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential mode 63 68 dB

SINAD

Signal-to-noise ratio

distortion

Single-ended mode (see Note 1) 64 dB Differential mode 64 69 dB

SNR

Signal-to-noise ratio

Single-ended mode (see Note 1) 65 dB

C and I suffix –73 –69

Differential mode

Q and M suffix –73 –67

THD

Total harmonic distortion

C and I suffix –73 –69

Single-ended mode

Q and M suffix –73 –67

ENOB

Differential mode 10.3 11 Bits

(SNR)

Effective number of bits

Single-ended mode (see Note 1) 10.4 Bits

Differential mode 68 75 dB

SFDR

Spurious free dynamic range

Single-ended mode 68 75 dB

Analog Input

Full-power bandwidth with a source impedance of 150 Ω in differential configuration.

FS sinewave, –3 dB 96 MHz

Full-power bandwidth with a source impedance of 150 Ω in single-ended configuration.

FS sinewave, –3 dB 54 MHz

Small-signal bandwidth with a source impedance of 150 Ω in differential configuration.

100 mVpp sinewave, –3 dB 96 MHz

Small-signal bandwidth with a source impedance of 150 Ω in single-ended configuration.

100 mVpp sinewave, –3 dB 54 MHz

NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the

sampling clock.

THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing specifications, AV

= 5 V, BVDD = DVDD = 3.3 V, V

REF

= internal, CL < 30 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(DATA_AV)

Delay time 5 ns

d(o)

Delay time 5 ns

pipe

Latency 5

CONV

CLK

timing specification of the single conversion mode

†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Clock cycle of the internal clock oscillator 159 167 175 ns

Pulse width, CONVST 1.5×t

Aperture time 1 ns

1 analog input 2×t

2 analog inputs 3×t

t2Time between consecutive start of single conversion

3 analog inputs 4×t

4 analog inputs 5×t

1 analog input, TL = 1 6×t

Delay time, DATA_AV becomes active for the trigger

2 analog inputs, TL = 2 7×t

y, _ gg

level condition: TRIG0 = 0, TRIG1 = 0

3 analog inputs, TL = 3 8×t

4 analog inputs, TL = 4 9×t

1 analog input, TL = 4 3×t2 +6×t

Delay time, DATA_AV becomes active for the trigger

2 analog inputs, TL = 4 t2 +7×t

d(DATA_AV)

y, _ gg

level condition: TRIG0 = 1, TRIG1 = 0

3 analog inputs, TL = 6 t2 +8×t

4 analog inputs, TL = 8 t2 +9×t

1 analog input, TL = 8 7×t2 +6×t

Delay time, DATA_AV becomes active for the trigger

2 analog inputs, TL = 8 3×t2 +7×t

y, _ gg

level condition: TRIG0 = 0, TRIG1 = 1

3 analog inputs, TL = 9 2×t2 +8×t

4 analog inputs, TL = 12 2×t2 +9×t

1 analog input, TL = 14 13×t2 +6×t

d(DATA_AV)

Delay time, DATA_AV becomes active for the trigger

2 analog inputs, TL = 12 5×t2 +7×t

(

)

level condition: TRIG0 = 1, TRIG1 = 1

3 analog inputs, TL = 12 3×t2 +8×t

†

Timing parameters are ensured by design but are not tested.

THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

reference voltage

The THS1206 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V . An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

analog inputs

The THS1206 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed.

converter

The THS1206 uses a 12-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages, which achieves a high sample rate with low power consumption. The THS1206 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples.

conversion modes

The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal.

sampling rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.

Table 1. Maximum Conversion Rate in Continuous Conversion Mode

CHANNEL CONFIGURATION

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

1 single-ended channel 1 6 MSPS 2 single-ended channels 2 3 MSPS 3 single-ended channels 3 2 MSPS 4 single-ended channels 4 1.5 MSPS 1 differential channel 1 6 MSPS 2 differential channels 2 3 MSPS 1 single-ended and 1 differential channel 2 3 MSPS 2 single-ended and 1 differential channels 3 2 MSPS

The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:

6 MSPS

# channels

Table 2 shows the maximum conversion rate in the single conversion mode.

THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

sampling rate (continued)

Table 2. Maximum Conversion Rate in Single Conversion Mode

CHANNEL CONFIGURATION

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

1 single-ended channel 1 3 MSPS 2 single-ended channels 2 2 MSPS 3 single-ended channels 3 1.5 MSPS 4 single-ended channels 4 1.2 MSPS 1 differential channel 1 3 MSPS 2 differential channels 2 2 MSPS 1 single-ended and 1 differential channel 2 1.5 MSPS 2 single-ended and 1 differential channels 3 1.2 MSPS

single conversion mode

In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion mode is selected by setting bit 1 of control register 0 to 1.

A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started.

The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13.

Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can be selected to be sampled simultaneously (see Table 2).

CONVST

AIN

Sample N

d(A)

DATA_AV

DATA_AV,

Trigger Level = 1

Figure 1. Timing of Single Conversion Mode

The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog input channels. The time t

DATA_AV

, until DA TA_AV becomes active is given by: t

DATA_AV

= t

pipe

+ n × tc. This equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer to the timing specifications of single conversion mode.

THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

continuous conversion mode

The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.

Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum throughput rate is 6 MSPS in this mode. The timing of the DA T A_A V signal is shown here in the case of a trigger level set to 1 or 4.

Sample N Channel 1

Sample N+1

Channel 1

Sample N+2

Channel 1

Sample N+3

Channel 1

Sample N+4

Channel 1

Sample N+5

Channel 1

Sample N+6

Channel 1

Sample N+7

Channel 1

Sample N+8

Channel 1

Data N–5

Channel 1

Data N–4

Channel 1

Data N–3

Channel 1

Data N–2

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N+1

Channel 1

Data N+2

Channel 1

Data N+3 Channel 1

d(A)

w(CONV_CLKH)

w(CONV_CLKL)

d(O)

d(DATA_AV)

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 1

DATA_AV,

Trigger Level = 4

d(pipe)

50% 50%

Figure 2. Timing of Continuous Conversion Mode (1-channel operation)

Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is written into the FIFO. The timing of the DA TA_A V signal shown here is for a trigger level set to 2 or 4.

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 2

DATA_AV,

Trigger Level = 4

Data N–3

Channel 2

Data N–2

Channel 1

Data N–2

Channel 2

Data N–1

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N

Channel 2

Data N+1

Channel 1

Data N+1

Channel 2

d(DATA_AV)

w(CONV_CLKH)

w(CONV_CLKL)

d(A)

Sample N

Channel 1,2

Sample N+1

Channel 1,2

Sample N+2 Channel 1,2

Sample N+3 Channel 1,2

Sample N+4 Channel 1,2

d(O)

d(Pipe)

d(DATA_AV)

50% 50%

Figure 3. Timing of Continuous Conversion Mode (2-channel operation)

THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

continuous conversion mode (continued)

Figure 4 shows the timing of continuous conversion mode when three analog input channels are selected. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DA TA_AV signal shown here is for a trigger level set to 3.

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 3

d(DATA_AV)

Sample N

Channel 1,2,3

Sample N+1

Channel 1,2,3

Sample N+2

Channel 1,2,3

d(O)

Data N–2

Channel 2

Data N–2

Channel 3

Data N–1

Channel 2

Data N–1

Channel 2

Data N–1

Channel 3

Data N

Channel 1

Data N

Channel 2

Data N+1 Channel 3

d(A)

w(CONV_CLKH)

w(CONV_CLKL)

d(Pipe)

50% 50%

Figure 4. Timing of Continuous Conversion Mode (3-channel operation)

Figure 5 shows the timing of continuous conversion mode when four analog input channels are selected. The maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DA TA_AV signal shown here is for a trigger level of 4.

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 4

w(CONV_CLKH)

Sample N

Channel 1,2,3,4

Sample N+1

Channel 1,2,3,4

Sample N+2

Channel 1,2,3,4

d(Pipe)

w(CONV_CLKL)

d(O)

Data N–2

Channel 4

Data N–1

Channel 1

Data N–1 Channel 2

Data N–1 Channel 3

Data N–1

Channel 4

Data N

Channel 1

Data N

Channel 2

Data N

Channel 3

Data N

Channel 4

d(DATA_AV)

d(A)

50% 50%

Figure 5. Timing of Continuous Conversion Mode (4-channel operation)

THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

digital output data format

The digital output data format of the THS1206 can either be in binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages.

Table 3. Binary Output Format for Single-Ended Configuration

SINGLE-ENDED, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

FFFh

AIN = (V

REFP

+ V

REFM

)/2 800h

AIN = V

REFM

000h

Table 4. Two’s Complement Output Format for Single-Ended Configuration

SINGLE-ENDED, TWOS COMPLEMENT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

7FFh

AIN = (V

REFP

+ V

REFM

)/2 000h

AIN = V

REFM

800h

Table 5. Binary Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

REF

= V

REFP

– V

REFM

Vin = V

REF

FFFh Vin = 0 800h Vin = –V

REF

000h

Table 6. Two’s Complement Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

REF

= V

REFP

– V

REFM

Vin = V

REF

7FFh Vin = 0 000h Vin = –V

REF

800h

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