TEXAS INSTRUMENTS THS1060 Technical data
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THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
features
D
60 MSPS Maximum Sample Rate
D
10-Bit Resolution
D
No Missing Codes
D
On-Chip Sample and Hold
D
73 dB Spurious Free Dynamic Range at
fin = 15.5 MHz
D
5 V Analog and Digital Supply
D
3 V and 5 V CMOS Compatible Digital
Output
D
9.5 Bit ENOB at fIN = 31 MHz
D
60 dB SNR at fIN = 31 MHz
D
82 MHz Bandwidth
D
Internal or External Reference
D
Buffered 900 Ω Differential Analog Input
applications
D
Wireless Local Loop
D
Wireless Internet Access
D
Cable Modem Receivers
D
Medical Ultrasound
D
Magnetic Resonant Imaging
description
The THS1060 is a high speed low noise 10-bit CMOS pipelined analog-to-digital converter. A dif ferential sample
and hold minimizes even order harmonics and allows for a high degree of common mode rejection at the analog
input. A buffered analog input allows for operation with a constant analog input impedance, and prevents
transient voltage spikes from feeding backward to the analog input source. Full temperature DNL performance
allows for industrial application with the assurance of no missing codes. The THS1060 can operate with either
internal or external references. Internal reference usage selection is accomplished simply by externally
connecting reference output terminals to reference input terminals. Packaged in a small 48-pin quad flat-pack,
the THS1060 makes use of Texas Instruments PowerPAD technology. The die of the THS1060 is bonded
directly to a copper alloy plate which is exposed on the bottom of the package. When soldered to a ground land,
the PowerPAD provides superior heat dissipation and thermal performance ideal for industrial applications
in high temperature environments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
48 PHP PACKAGE
(TOP VIEW)
AV
AV
AV
V
REFOUT–
V
REFIN
V
REFIN
V
REFOUT
AV
AV
DD
DD
CM
V
47 46 45 44 4348 42
1
SS
2
DD
V
3
IN+
V
4
IN–
5
DD
6
–
7
+
8
+
9
V
10
BG
11
SS
12
DD
14 15
13
AV
AVSSAVSSAVDDAV
AV
17 18 19 20
16
SS
DRVSSAVSSDRV
40 39 3841
22 23 24
21
SS
DRVDDDRV
37
DD
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
functional block diagram
V
V
REFIN+
V
REFOUT+
V
REFOUT–
V
REFIN–
CLK+
CLK–
IN+
V
IN–
V
CM
Buffer
900 Ω
3.0 V
Reference
2.0 V
Timing
AVDDDV
S/H
AV
DD/2
SS
SS
CLK–
CLK+
AV
DV
T
–40°C to 85°C THS1060I
0°C to 70°C THS1060C
DRV
DD
DVDDDVSSDVSSDVDDDVSSDV
AVAILABLE OPTIONS
A
DD
Stage 1 Stage 10
DD
PACKAGE
48-TQFP
(PHP)
Stages 2 – 9
Σ
D/AA/D A/D
1
Digital Error Correction
DRV
SS
DD
DRV
A/D
Σ
D/A
1
1
SS
DV
SS
DRV
SS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AV
2
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
I/O
DESCRIPTION
ANALOG-TO-DIGITAL CONVERTER
Terminal Functions
TERMINAL
NAME NO.
AV
DD
AV
SS
CLK+ 15 I Clock input
CLK– 16 I Complementary clock input
D9–D0 25–34 O Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)
DRV
DD
DRV
SS
DV
DD
DV
SS
V
BG
V
CM
V
IN+
V
IN–
V
REFIN–
V
REFIN+
V
REFOUT+
V
REFOUT–
2, 5, 12
43, 45, 47
1, 11, 13,
41, 42, 44,
46
24, 37, 38 I Digital output driver supply
23, 39, 40 I Digital output driver ground return
17, 20, 22 I Positive digital supply
18, 19, 21 I Digital ground return
10 O Band gap reference. Bypass to ground with a 1 µF and a 0.01 µF chip capacitor.
48 O Common mode voltage output. Bypass to ground with a 0.1 µF and a 0.01 µF chip device capacitor.
3 I Analog signal input
4 I Complementary analog signal input
7 I External reference input low
8 I External reference input high
9 O Internal reference output. Compensate with a 1 µF and a 0.01 µF chip capacitor.
6 O Internal reference output. Compensate with a 1 µF and a 0.01 µF chip capacitor.
I Analog power supply
I Analog ground return for internal analog circuitry
THS1060
SLAS212 – MARCH 2000
detailed description
The THS1060 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 900 Ω resistor . The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor op-amp based
circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram.
The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic block which then
outputs the final 10 bits.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range: AVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AV
and DVSS –0.3 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SS
Voltage between DRVDD and DVDD –0.5 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AVDD and DVDD –0.5 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital data output –0.3 V to DVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK peak input current 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs) –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: THS1060C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS1060I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
PARAMETER MIN NOM MAX UNIT
Sample rate 1 60 MSPS
Analog supply voltage, AV
Digital supply voltage, DV
Digital output driver supply voltage, DRV
CLK + high level input voltage, V
CLK + low-level input voltage, V
CLK – high-level input voltage, V
CLK – low-level input voltage, V
CLK pulse-width high, t
CLK pulse-width low, t
Operating free-air temperature range, T
Operating free-air temperature range, T
DD
DD
IH
IL
IH
IL
p(H)
p(L)
DD
THS1060C 0 70 °C
A
THS1060I –40 85 °C
A
4.75 5 5.25 V
4.75 5 5.25 V
3 3.3 5.25 V
4 5 5.5 V
0 1 V
4 5 5.5 V
0 1 V
7.5 8.3 ns
7.5 8.3 ns
electrical characteristics, over recommended operating free-air temperature range,
AV
= DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 60 MHz, (unless otherwise noted)
DD
dc accuracy
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DNL Dif ferential nonlinearity (see Note 1) ±0.4 ±1 LSB
No missing codes (see Note 2) Assured
INL Integral nonlinearity (see Note 1) ±0.9 ±3 LSB
E
O
E
G
‡
All typical values are at TA = 25°C.
NOTES: 1. Tested without over ranging
4
Offset error 15 31 mV
Gain error –7 –10 %FSR
2. Tested with over ranging
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
‡
THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
electrical characteristics, over recommended operating free-air temperature range,
= DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 60 MHz, (unless otherwise noted)
AV
DD
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(AV
I(DV
I(DRV
P
D
†
All typical values are at TA = 25°C.
reference
V
REFOUT–
V
REFOUT+
V
REFIN–
V
REFIN+
V(VCM) Common mode output voltage AVDD/2 V
I(VCM) Common mode output current 10 µA
†
All typical values are at TA = 25°C.
Analog supply current V(VIN) = V(VCM) 120 150 mA
DD)
Digital supply current V(VIN) = V(VCM) 2 5 mA
DD)
Output driver supply current V(VIN) = V(VCM) 2 6 mA
DD)
Power dissipation V(VIN) = V(VCM) 0.6 W
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Negative reference output voltage 1.95 2 2.05 V
Positive reference output voltage 2.95 3 3.05 V
External reference supplied 2 V
External reference supplied 3 V
†
analog input
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RIDifferential input resistance 900 Ω
CIDifferential input capacitance 4 pF
VIAnalog input common mode range VCM ±0.05 V
VIDDifferential input voltage range 2
BW Analog input bandwidth (large signal) –3 dB 82 MHz
†
All typical values are at TA = 25°C.
V p-p
digital outputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
V
OL
C
L
†
All typical values are at TA = 25°C.
High-level output voltage IOH = –50 µA 0.8DRV
Low-level output voltage IOL = 50 µA 0.2DRV
Output load capacitance 15 pF
DD
DDVDD
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
THS1060
dBc
d
d
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
ac specifications, over recommended operating free-air temperature range, AVDD = DVDD = 5 V,
DRV
noted)
SNR Signal to noise ratio
SINAD Signal to noise and distortion
ENOB Effective number of bits fIN =15.5 MHz 8.5 9.6 bits
THD Total harmonic distortion fIN =15.5 MHz –72 –54
SFDR Spurious-free dynamic range fIN =15.5 MHz 57 73
2
3
Two tone SFDR
†
All typical values are at TA = 25°C.
= 3.3 V, internal references, CLK = 60 MHz, analog input at – 2 dBFS(unless otherwise
DD
†
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN = 2.2 MHz 60
n
Harmonic Distortion
r
Harmonic Distortion
fIN =15.5 MHz
fIN =31 MHz 60
fIN = 2.2 MHz 59
fIN =15.5 MHz
fIN =31 MHz 59
fIN = 2.2 MHz –80
fIN =15.5 MHz
fIN = 31 MHz –79
fIN = 2.2 MHz –68
fIN =15.5 MHz
fIN = 31 MHz –68
F1 = 14.9 MHz, F2 = 15.6 MHz,
Analog inputs at – 8 dBFS each
56 60
53 59.6
–77 –57
–79 –60
70 dBc
dBFS
dBFS
dBc
dBc
operating characteristics over recommended operating conditions, AVDD = DVDD = 5 V,
DRV
DD = 3.3 V
switching specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Aperture delay, t
Aperture jitter 1 ps RMS
Output delay t
Pipeline delay t
d(A)
d(O)
d(PIPE)
After falling edge of CLK+ 13 ns
120 ps
6.5
CLK
Cycle
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
definitions of specifications
analog bandwidth
The analog input frequency at which the spectral power of the fundamental frequency of a large input signal
is reduced by 3 dB.
aperture delay
The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is
sampled.
aperture uncertainity (jitter)
The sample-to-sample variation in aperture delay
differential nonlinearity
The average deviation of any output code from the ideal width of 1 LSB.
clock pulse width/duty cycle
Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve
rated performance; pulse width low is the minimum time clock pulse should be left in low state. At a given clock
rate, these specs define acceptable clock duty cycles.
offset error
The difference between the analog input voltage at which the analog-to-digital converter output changes from
negative full scale, to one LSB above negative full scale, and the ideal voltage at which this transition should
occur.
THS1060
gain error
The maximum error in LSBs between a digitized ideal full scale low frequency offset corrected triangle wave
analog input, from the ideal digitized full scale triangle wave, divided by the full scale range, in this case 1024.
harmonic distortion
The ratio of the power of the fundamental to a given harmonic component reported in dBc.
integral nonlinearity
The deviation of the transfer function from an end-point adjusted reference line measured in fractions of 1 LSB.
Also the integral of the DNL curve.
output delay
The delay between the 50% point of the falling edge of the clock and signal and the time when all output data
bits are within valid logic levels (not including pipeline delay).
signal-to-noise-and distortion (SINAD)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other spectral
components, excluding dc, referenced to full scale.
signal-to-noise ratio (SNR)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other power spectral
components, excluding dc and the first 9 harmonics, referenced to full scale.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits, using the following formula,
ENOB
(
SINAD*1.76
+
6.02
)
spurious-free dynamic range (SFDR)
The ratio of the signal power to the power of the worst spur, excluding dc. The worst spurious component may
or may not be a harmonic. The ratio is reported in dBc (that is, degrades as signal levels are lowered).
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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