Texas Instruments TCM129C18N, TCM29C19N, TCM29C18N, TCM29C19DW, TCM29C18DW Datasheet

TCM29C18, TCM29C19, TCM129C18, TCM129C19

ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

D

Reliable Silicon-Gate CMOS Technology

D

Low Power Consumption
– Operating Mode...80 mW
– Power-Down Mode...5 mW

D

µ-Law Coding

D

Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz

D

No External Components Needed for
Sample, Hold, and Autozero Functions

D

Precision Internal Voltage Reference

D

Single Chip Contains A/D, D/A, and
Associated Filters

description

The TCM29C18, TCM29C19, TCM129C18, and
TCM129C19 are low-cost single-chip PCM
codecs (pulse-code-modulated encoders and
decoders) and PCM line filters. These devices
incorporate both the A/D and D/A functions, an
antialiasing filter (A/D), and a smoothing filter
(D/A). They are ideal for use with the TMS320
DSP family members, particularly those featuring
a serial port such as the TMS32020, TMS32011,
and TMS320C25.

DW OR N PACKAGE

(TOP VIEW)

V

1

BB

PWRO+
PWRO–

DCLKR

PCM IN

FSR/TSRE

DGTL GND

Number of Pins:

16

Coding Law:

µ-Law

Variable Mode:

64 kHz to 2.048 MHz

Fixed Mode:

2.048 MHz (TCM29C18, TCM129C18),

1.536 MHz (TCM29C19, TCM129C19)
8-Bit Resolution

12-Bit Dynamic Range

2
3

PDN

4
5
6
7
8

FEATURES TABLE

V

16

GSX

15

ANLG IN

14

ANLG GND

13
12

TSX/DCLKX

11

PCM OUT

10

FSX/TSXE

9

CLK

CC

Primary applications include:

• Digital encryption systems

• Digital voice-band data storage systems

• Digital signal processing

These devices are designed to perform encoding of analog input signals (A/D conversion) and decoding of
digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a digital
signal processing system. Both devices also provide band-pass filtering of the analog signals prior to encoding,
and smoothing after decoding.

The TCM29C18 and TCM29C19 are characterized for operation over the temperature range of 0°C to 70°C.
The TCM129C18 and TCM129C19 are characterized for operation over the temperature range of
–40°C to 85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

functional block diagram

ANLG IN

GSX

PWRO+
PWRO–

Transmit Section

14

15

Receive Section

Gain

2
3

Reference

Set

+
–

Autozero

11

11

Filter

Filter

Σ

Sample
and Hold
and DAC

Reference

Buffer

Comparator

Analog-

to-Digital

Control

Logic

Sample
and Hold
and DAC

Successive

Approximation

Control Section

Digital-

to-Analog

Control

Logic

Output

Register

Control

Logic

Input

Register

PCM OUT

12

TSX/
DCLKX

10

FSX/TSXE

9

CLK

4

PDN

6

PCM IN

5

DCLKR

138116

ANLG

DGTL

V

V

CC

BB

GND

GND

7

FSR/TSRE

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TCM29C18, TCM29C19, TCM129C18, TCM129C19

ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

Terminal Functions

TERMINAL

NAME NO.

ANLG IN 14 I Inverting analog input to uncommitted transmit operational amplifier.
ANLG GND 13 Analog ground return for all voice circuits. ANLG GND is internally connected to DGTL GND.
CLK 9 I Master clock and data clock input for the fixed-data-rate mode. Master (filter) clock only for variable-data-rate

DCLKR 5 I Fixed-data-rate mode — variable-data-rate mode select. When DCLKR is connected to VBB, the device operates

DGTL GND 8 Digital ground for all internal logic circuits. DGTL GND is internally connected to ANLG GND.
FSR/TSRE 7 I Frame-synchronization clock input/time-slot enable for the receive channel. In the variable-data-rate mode, this

FSX/TSXE 10 I Frame-synchronization clock input/time-slot enable for transmit channel. FSX/TSXE operates independently of,

GSX 15 O Output terminal of internal uncommitted operational amplifier. Internally , this is the voice signal input to the transmit

PCM IN 6 I Receive PCM input. PCM data is clocked in on eight consecutive negative transitions of the receive data clock,

PCM OUT 11 O Transmit PCM output. PCM data is clocked out of pcm out on eight consecutive positive transition of the transmit

PDN 4 I Power-down select. On the TCM29C18 and the TCM129C18, the device is inactive with a TTL low-level input and

PWRO+ 2 O Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly

PWRO– 3 O Inverting output of power amplifier. PWRO– is functionally identical to PWRO+.
TSX/DCLKX 12 I/O Transmit channel time-slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain

V

BB

V

CC

1 Negative supply voltage. Input is –5 V ±5%.

16 Positive supply voltage. Input is 5 V ±5%.

mode. CLK is used for both the transmit and receive sections.

in the fixed-data-rate mode. When DCLKR is not connected to VBB, the device operates in the variable-data-rate
mode and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 2.048 MHz.

signal must remain high for the duration of the time slot. The receive channel enters the standby state when FSR
is TTL low for 30 ms.

but in an analogous manner to FSR/TSRE. The transmit channel enters the standby state when FSX is low for 300
ms.

filter.

which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing.

data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.

active with a TTL high-level input to the terminal. On the TCM29C19 and the TCM129C19, this terminal must be
connected to a TTL high level.

in either a differential or single-ended configuration.

output to be used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the
transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TCM29C18, TCM29C19, TCM129C18, TCM129C19

RLLoad resistance

CLLoad capacitance

pF

TAOperating free-air temperature

°C

PARAMETER

TEST CONDITIONS

UNIT

CC

y

CC

ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Output voltage range, V
Input voltage range, V

(see Note 1) –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Digital ground voltage range –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TCM29C18, TCM29C19 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . .

A

TCM129C18, TCM129C19 –40°C to 85°C. . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Voltage values for maximum ratings are with respect to VBB.

recommended operating conditions (see Note 2)

MIN NOM MAX UNIT

V
V

V
V
V

NOTES: 2. T o avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device

Supply voltage (see Note 3) 4.75 5 5.25 V

CC

Supply voltage –4.75 –5 –5.25 V

BB

DGTL GND voltage with respect to ANLG GND 0 V
High-level input voltage, all inputs except ANLG IN 2.2 V

IH

Low-level input voltage, all inputs except ANLG IN 0.8 V

IL

Peak-to-peak analog input voltage (see Note 4) 4.2 V

I(PP)

GSX 10 kΩ
PWRO+ and/or PWRO– 300 Ω

p

p

power-up sequence paragraphs later in this document should be followed.

3. V oltages at analog inputs and outputs and VCC and VBB terminals are with respect to ANLG GND. All other voltages are referenced
to DGTL GND unless otherwise noted.

4. Analog inputs signals that exceed 4.2 V peak to peak may contribute to clipping and preclude correct A/D conversion. The digital
code representing values higher than 4.2 V is 10000000. For values more negative than 4.2 V, the code is 0000000.

p

GSX 50
PWRO+ and/or PWRO– 100
TCM29C18 or TCM29C19 0 70
TCM129C18 or TCM129C19 –40 85

p

°

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

supply current, f

I

Supply current from V

CC

I

Supply current from V

BB

4

= 2.048 MHz, outputs not loaded

DCLK

Operating 10 14

CC

BB

Standby
Power down
Operating –10 –14
Standby
Power down

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TCM29Cxx TCM129Cxx

MIN MAX MIN MAX

FSX or FSR at VIL after 300 ms 1.2 1.5
PDN at VIL after 10 µs

FSX or FSR at VIL after 300 ms –1.2 –1.5
PDN at VIL after 10 µs

1 1.2

–1 –1.2

mA

mA

VOHHigh-level output voltage at PCM OUT

V

g

dB

in ut (see Note 8)

TCM29C18, TCM29C19, TCM129C18, TCM129C19

ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

ground terminals

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DC resistance between ANLG GND and DGTL GND 34 Ω

digital interface

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

p

V

Low-level output voltage at TSX

OL

I

High-level input current, any digital input VI = 2.2 V to V

IH

I

Low-level input current, any digital input VI = 0 to 0.8 V 12 µA

IL

C

Input capacitance 5 10 pF

i

C

Output capacitance 5 pF

o

†

All typical values are at VBB = –5 V , VCC = 5 V, and TA = 25°C.

transmit side (A/D) characteristics

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Input offset voltage at ANLG IN VI = –2.17 V to 2.17 V ±25 mV
Input offset current at ANLG IN VI = –2.17 V to 2.17 V 1 pA
Input bias current VI = –2.17 V to 2.17 V ±100 nA
Open-loop voltage amplification at GSX 5000
Unity-gain bandwidth at GSX 1 MHz
Input resistance at ANLG IN 10 MΩ

Gain-tracking error with sinusoidal input
(see Notes 5, 6, and 7)

Transmit gain tolerance VI = 1.06 V, f = 1.02 kHz 0.95 1.19 Vrms
Noise Ref max output level: 200 Hz to 3 kHz –70 dB
Supply-voltage rejection ratio,

VCC to V
Crosstalk attenuation, transmit to

receive (single ended)

Signal-to-distortion ratio, sinusoidal

Absolute delay time to PCM OUT

†

All typical values are at VBB = –5 V , VCC = 5 V, and TA = 25°C.

NOTES: 5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point

BB

p

of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.

6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave
through an ideal encoder.

7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO+ and PWRO– to 0 dBM. All
output levels are (sin x)/x corrected.

8. CCITT G.712 – Method 2

–3 ≥ dBm0 input level ≥ –40 dBm0, Ref level = –10 dBm0 ±0.5
–40 > dBm0 input level ≥ –50 dBm0, Ref level = –10 dBm0 ±25

f = 0 Hz to 30-kHz (measured at PCM OUT) idle channel,
Supply signal = 200 mV peak to peak

ANLG IN = 0 dBm,
PCM IN = lowest decode level,

0 dBm0 ≥ ANLG IN ≥ –30 dBm0 33
–30 dBm0 > ANLG IN ≥ –40 dBm0 27
–40 dBm0 > ANLG IN ≥ –45 dBm0 22
Fixed-data rate,

Input to ANLG IN = 1 kHz at 0 dB

IOH = –9.6 mA 2.4
IOH = –0.1 mA 3.5
IOL = 3.2 mA 0.5 V

CC

f = 1-kHz, unity gain,
Measured at PWRO+

f

= 2.048 MHz,

CLKX

–20 dB

62 dB

245 µs

12 µA

dB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TCM29C18, TCM29C19, TCM129C18, TCM129C19

g

dB

ygj ,

S

200 mV

N

20

dB

in ut (see Note 8)

ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

receive side (D/A) characteristics (see Note 9)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Output offset voltage PWRO+ and
PWRO– (single ended)

Output resistance at PWRO+ and
PWRO–

Gain-tracking error with sinusoidal
input (see Notes 5, 6, and 7)

Receive gain tolerance VI = 1.06 V, f = 1.02 kHz 1.34 1.69 Vrms
Noise Ref max output level: 200 Hz to 3 kHz –70 dB

Supply voltage rejection ratio,
VCC to VBB (single-ended)

Crosstalk attenuation, receive to
transmit (single ended)

Signal-to-distortion ratio, sinusoidal

p

Absolute delay time to PWRO+ Fixed data rate, f

†

All typical values are at VBB = –5 V , VCC = 5 V, and TA = 25°C.

NOTES: 5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point

of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.

6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave
through an ideal encoder.

7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO+ and PWRO– to 0 dBM. All
output levels are (sin x)/x corrected.

8. CCITT G.712 – Method 2

9. The receive side (D/A) characteristics are referenced to a 600-Ω termination.

Relative to ANLG GND ±200 mV

1 2 Ω

–3 dBm0 ≥ input level ≥ –40 dBm0, Ref level = –10 dBm0 ±0.5
–40 dBm0 > input level ≥ –50 dBm0, Ref level = –10 dBm0 ±25

f = 0 Hz to 30-kHz,

pp

upply signal =

Frequency at PWRO+
PCM IN = 0 dB,

Frequency = 1 kHz at PCM OUT
0 dBm0 ≥ ANLG IN ≥ –30 dBm0 33
–30 dBm0 > ANLG IN ≥ –40 dBm0 27
–40 dBm0 > ANLG IN ≥ –45 dBm0 22

p

peak to peak,

p

Idle channel,

arrow band,

= 2.048 MHz 190 µs

CLKX

–

60 dB

dB

timing requirements

clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)

MIN NOM MAX UNIT

t

c(CLK)

tr, t

f

t

w(CLK)

t

w(DCLK)

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)

t

d(FSX)

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)

t

d(FSR)

Clock period for CLK (2.048-MHz systems) 488 ns
Rise and fall times for CLK 5 30 ns
Pulse duration for CLK 220 ns
Pulse duration, DCLK (f
Clock duty cycle, [t

Frame-sync delay time 100 t

Frame-sync delay time 100 t

w(CLK)/tc(CLK)

= 64 kHz to 2.048 MHz) 220 ns

DCLK

] for CLK 45% 50% 55%

MIN MAX UNIT

c(CLK)

MIN MAX UNIT

c(CLK)

–100 ns

–100 ns

6

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