SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
1B
1A
S0
1DE
S1
2A
2B
GND
D PACKAGE
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
0
1
V
CC
V
CC
1Y
1Z
2DE
2Z
2Y
GND
D
Meets or Exceeds the Requirements of
ANSI TIA/EIA–644–1995 Standard
D
Designed for Signaling Rates Up to
400 Mbit/s
D
ESD Protection Exceeds 12 kV on Bus Pins
D
Operates from a Single 3.3-V Supply
D
Low-Voltage Differential Signaling with
Output Voltages of 350 mVinto:
– 100-Ω Load (SN65LVDS22)
– 50-Ω Load (SN65LVDM22)
D
Propagation Delay Time; 4 ns Typ
D
Power Dissipation at 400 Mbit/s of 150 mW
D
Bus Pins are High Impedance When
Disabled or With V
D
LVTTL Levels are 5 V Tolerant
D
Open-Circuit Fail Safe Receiver
Less Than 1.5 V
CC
description
The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use
low-voltage differential signaling (LVDS) to
achieve signaling rates as high as 400 Mbps. The
receiver outputs can be switched to either or both
drivers through the multiplexer control signals S0
and S1. This allows the flexibility to perform
logic diagram (positive logic)
2
1
4
12
3
5
+
_
1A
1B
1DE
2DE
S0
S1
splitter or signal routing functions with a single
device.
The TIA/EIA-644 standard compliant electrical
interface provides a minimum differential output
2A
2B
6
+
7
_
0
1
voltage magnitude of 247 mV into a 100-Ω load
and receipt of 100 mV signals with up to 1 V of
MUX Truth Table
ground potential difference between a transmitter
and receiver. The SN65LVDM22 doubles the
output drive current to achieve L VDS levels with a
50 Ω load.
The intended application of these devices and
signaling technique is for both point–to–point
baseband (single termination) and multipoint
INPUT OUTPUT
S1
S0
1Y/1Z
0
0
1A/1B
0
1
2A/2B
1
0
1A/1B
1
1
2A/2B
2Y/2Z
1A/1B
2A/2B
2A/2B
1A/1B
FUNCTION
Splitter
Splitter
Router
Router
(double termination) data transmissions over
controlled impedance media. The transmission
media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data
transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment,
and other application specific characteristics).
14
13
10
1Y
1Z
2Y
11
2Z
The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40 C to 85 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
equivalent input and output schematic diagrams
V
CC
V
CC
S0, S1
Input
A Input B Input
50 Ω
7 V
300 kΩ
V
CC
300 kΩ 300 kΩ
1DE, 2DE
Input
10 kΩ
50 Ω
7 V
300 kΩ
V
CC
5 Ω
Y or Z
Output
7 V7 V
7 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Voltage range (DE, S0, S1) –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
(A or B) –0.5 V to Vcc+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Electrostatic discharge: A, B, Y, Z and GND (see Note 2) Class 3, A:12 kV, B:600 V. . . . . . . . . . . . . . . . . . . .
All pins Class 3, A:5 kV, B:500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING T ABLE
PACKAGE
D16 950 mW 7.6 mW/°C 494 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
‡
POWER RATING
TA = 85°C
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Magnitude of differential input voltage, VID 0.1 0.6 V
Common-mode input voltage, VIC (see Figure 1)
Operating free-air temperature, T
CC
IH
IL
A
S0, S1, 1DE, 2DE 2 V
S0, S1, 1DE, 2DE 0.8 V
3 3.3 3.6 V
Ť
Ť
Ť
Ť
V
ID
2
–40 85 °C
V
ID
2.4–
2
VCC–0.8 V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN65LVDS22, SN65LVDM22
IIInput current (A or B inputs)
A
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
COMMON-MODE INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
2.5
vs
MAX at VCC > 3.15 V
2
1.5
1
– Common-Mode Input Voltage – VV
0.5
IC
0
0 0.1 0.2 0.3
MAX at VCC = 3 V
Min
0.4 0.5 0.6
VID – Differential Input Voltage – V
Figure 1. Common-Mode Input Voltage vs Differential Input Voltage
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
ITH+
V
ITH–
I
I(OFF)
Positive-going differential input voltage threshold 100 mV
Negative-going differential input voltage threshold –100 mV
p
Power-off input current (A or B inputs) VCC = 0 V 20 µA
p
VI = 0 V –2 –20
VI = 2.4 V –1.2
µ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
∆V
Change in differential out ut voltage magnitude
5050mV
)
R
L
Ω( LVDM22)
ICCSupply current
mA
IIHHigh-level input current
V
5
A
IILLow-level input current
V
V
A
,
(
)
V
OY
V
OZ
V,
( LVDS22)
IOSShort-circuit output current
,
(
)
mA
V
OY
V
OZ
V,
( LVDM22)
IOZHigh-impedance output current
A
See Figure 4
See Figure 5
Channel-to-channel ske
receiver to driver
‡
ns
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
receiver/driver electrical characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
OD
OD
V
OC(SS)
∆V
OC(SS)
V
OC(PP)
I
O(OFF)
C
IN
†
All typical values are at 25°C and with a 3.3 V supply.
Differential output voltage magnitude 247 340 454 mV
Change in differential output voltage magnitude
between logic states
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
Peak-to-peak common-mode output voltage 150 mV
pp
p
p
p
p
Power-off output current VCC = 0 V, VO = 3.6 V 0.015 ±1 µA
Input capacitance 3 pF
p
DE
S0, S1
DE
S0, S1
RL = 100 Ω (’LVDS22),
50
R
= 50 Ω(’LVDM22
No Load 8 12
RL = 100 Ω (‘LVDS22) 13 20
RL = 50 Ω (‘LVDM22) 21 27
Disabled 3 6
=
IH
= 0.8
IL
V
or V
= 0 V
or
or V
or
0
= 0 V
0
CC
VOD = 0 V,
V
VOD = 0 V,
VOD = 600 mV 0.015 ±1
VO = 0 V or V
See Figure 2
See Figure 3
’LVDS22
’LVDM22
–
1.125 1.375 V
–50 3 50 mV
–10
µ
20
–10
µ
10
–10
–10
–10
–10
0.015 ±1
µ
differential receiver to driver switching characteristics over recommended operating conditions
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
t
PLH
t
PHL
t
sk(p)
t
r
t
r
t
f
t
f
t
PHZ
t
PLZ
t
PZH
t
PZL
t
_R1_Dx
PHL
t
PLH_R1_Dx
t
PHL_R2_Dx
t
PLH_R2_Dx
†
All typical values are at 25°C and with a 3.3 V supply.
‡
These parametric values are measured over supply voltage and temperature ranges recommended for the device.
Differential propagation delay , low-to-high 4 6 ns
Differential propagation delay , high-to-low 4 6 ns
Pulse skew (|t
Transition, low-to-high SN65LVDS22
Transition, low-to-high SN65LVDM22
Transition, high-to-low SN65LVDS22 1 1.5 ns
Transition, high-to-low SN65LVDM22 0.8 1.3 ns
Propagation delay time, high-level-to-high-impedance output 4 10 ns
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output 6 10 ns
PHL
– t
|) 0.5 ns
PLH
w,
CL = 10 pF,
0.8 1.3 ns
0.2
0.2
0.2
0.2
1 1.5 ns
5 10 ns
5 10 ns
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5
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
DE
A
Pulse
Generator
V
I(B)
V
I(A)
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
NOTES: B. RL = 100 Ω or 50 Ω ±1%
pulse width = 10 ± 0.2 ns.
C. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
B
1.4 V
1 V
Input
(see Note A)
V
OD
0
Y
V
Z
OD
t
f
RL (see Note B)
CL = 10 pF
(2 Places)
(see Note C)
t
r
100%
80%
20%
0%
Figure 2. Test Circuit and Voltage Definitions for the Differential Output Signal
Pulse
Generator
DE
A
B
Input
(see Note A)
RL (see Note B)
Y
Z
(2 Places)
CL = 10 pF
(2 Places)
(see Note C)
V
I(B)
V
I(A)
V
V
OC
V
CC
OC(PP)
(see Note D)
1.4 V
1 V
V
OC(SS)
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
NOTES: B. RL = 100 Ω or 50 Ω ±1%
pulse width = 10 ± 0.2 ns.
C. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
D. The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
DE
Y
RL (see Note A)
Pulse
Generator
A
RD
V
IB
V
IA
V
OZ
V
OY
VOY – V
NOTES: A. RL = 100 Ω or 50 Ω ±1%
B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
OZ
B
t
PLH
0-V Differential
0-V Differential
t
r
Z
10 pF
1.2-V CM
t
PHL
1.2-V CM
10 pF
80%
0-V Differential
20%
t
f
1.4 V
1 V
1.4 V
1 V
Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
1 V or 1.4 V
1.2 V
DE
t
PZH
VOY or V
VOY or V
NOTES: A. RL = 100 Ω or 50 Ω ±1%
OZ
t
PZL
OZ
B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns.
DE
A
RD
B
t
PHZ
t
PLZ
RL/2
(see Note A)
1.2 V
RL/2
(see Note A)
2 V
1.4 V
0.8 V
≈1.4 V
1.25 V
1.2 V
1.2 V
1.15 V
≈1 V
Figure 5. Enable and Disable Timing Circuit
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
TYPICAL CHARACTERISTICS
3.5
3
2.5
2
1.5
1
– High-Level Ouptut Voltage – V
OH
.5
V
0
–4
SN65LVDS22
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 3.3 V
TA = 25°C
–2 –1
IOH – High-Level Output Current – mA
Figure 6
0–3
4
3
2
– Low-Level Output Voltage – V
1
OL
V
0
SN65LVDS22
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VCC = 3.3 V
TA = 25°C
40
IOL – Low-Level Output Current – mA
Figure 7
62
3.5
3
2.5
2
1.5
1
– High-Level Output Voltage – V
OH
.5
V
0
–8
SN65LVDM22
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 3.3 V
TA = 25°C
–4 –2
IOH – High-Level Output Current – mA
Figure 8
SN65LVDM22
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
VCC = 3.3 V
TA = 25°C
3
2
1
– Low-Level Output Voltage – V
OL
V
0–6
0
IOL – Low-Level Output Current – mA
6102
80
124
Figure 9
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9
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.
1000
100
10
1
Transmission Distance – m
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k 10M 100M
5% Jitter
1M
30% Jitter
Data Rate – Hz
Figure 10. Data Transmission Distance Versus Rate
10
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SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair . The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the L VDS receiver
will pull each line of the signal pair to near V
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
300 kΩ 300 kΩ
through 300-kΩ resistors as shown in Figure 1 1. The fail-safe
CC
V
CC
A
Rt = 100 Ω (Typ)
B
VIT ≈ 2.3 V
Y
Figure 11. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not af fect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pull-up currents from the receiver and the fail-safe feature.
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11
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
DIM
8
7
PINS **
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
8
14
0.008 (0,20) NOM
0°–8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
12
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
4040047/D 10/96
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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