Texas Instruments SN65LVDS116DGG, SN65LVDS116DGGR Datasheet

SN65LVDS116

16-PORT LVDS REPEATER

SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

One Receiver and Sixteen Line Drivers
Meet or Exceed the Requirements of ANSI
EIA/TIA-644 Standard

D

Designed for Signaling Rates Up to
622 Mbps

D

Enabling Logic Allows Separate Control of
Each Bank of Four Channels or 2-Bit
Selection of Any One of the Four Banks

D

Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100 Ω Load

D

Electrically Compatible With L VDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
T ermination Networks

D

Propagation Delay Times <4.7 ns

D

Output Skew is < 300 ps and Part-to-Part
Skew <1.5 ns

D

Total Power Dissipation Typically 470 mW
With All Ports Enabled and at 200 MHz

D

Driver Outputs or Receiver Input is High
Impedance when Disabled or With
V

CC

<1.5 V

D

Bus-Pin ESD Protection Exceeds 12 kV

D

Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch

description

The SN65L VDS116 is one differential line reciever
connected to sixteen differential line drivers that
implement the electrical characteristics of
low-voltage differential signaling (LVDS). LVDS,
as specified in EIA/TIA-644, is a data signaling
technique that offers the low-power, low-noise
coupling, and switching speeds to transmit data at speeds up to 622 Mbps and relatively long distances. (Note:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,
the noise coupling to the environment, and other system characteristics.)

The intended application of this device and signaling technique is for point-to-point or multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed
circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along
with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated
from the input. This is particularly advantageous in system clock distribution.

The SN65LVDS116 is characterised for operation from –40°C to 85°C.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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GND

V

CC

V

CC

GND

ENA
ENA

NC
NC

NC
ENB
ENB

NC

NC

NC

GND

V

CC

V

CC

GND

A
B

NC
ENC
ENC

S0
S1

SM
END
END

GND

V

CC

V

CC

GND

A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z

DGG PACKAGE

(TOP VIEW)

SN65LVDS116
16-PORT LVDS REPEATER

SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

A4Z

A4Y

A3Z

A3Y

A2Z

A2Y

A1Z

A1Y

S0

A
B

B2Z

B2Y

B1Z

B1Y

B4Z

B4Y

B3Z

B3Y

C2Z

C2Y

C1Z

C1Y

C4Z

C3Z

C4Y

C3Y

D2Z

D2Y

D1Z

D1Y

D4Z

D4Y

D3Z

D3Y

SM

S1

ENA
ENA

ENB
ENB

ENC
ENC

END
END

SN65LVDS116

16-PORT LVDS REPEATER

SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUT

OUTPUT

VID = VA - V

B

SM EN EN S1 S0 AY AZ BY BZ CY CZ DY DZ

X H L X X X Z Z Z Z Z Z Z Z

VID ≥100 mV H H L X X H L H L H L H L

–100 mV < VID < 100 mV H H L X X ? ? ? ? ? ? ? ?

VID ≤ –100 mV H H L X X L H L H L H L H

X H X H X X Z Z Z Z Z Z Z Z

VID ≥ 100 mV L X X L L H L Z Z Z Z Z Z

–100 mV < VID < 100 mV L X X L L ? ? Z Z Z Z Z Z

VID ≤ –100 mV L X X L L L H Z Z Z Z Z Z

VID ≥ 100 mV L X X L H Z Z H L Z Z Z Z

–100 mV < VID < 100 mV L X X L H Z Z ? ? Z Z Z Z

VID ≤ –100 mV L X X L H Z Z L H Z Z Z Z

VID ≥ 100 mV L X X H L Z Z Z Z H L Z Z

–100 mV < VID < 100 mV L X X H L Z Z Z Z ? ? Z Z

VID ≤ –100 mV L X X H L Z Z Z Z L H Z Z

VID ≥ 100 mV L X X H H Z Z Z Z Z Z H L

–100 mV < VID < 100 mV L X X H H Z Z Z Z Z Z ? ?

VID ≤ –100 mV L X X H H Z Z Z Z Z Z L H

H = high level, L = low level, Z = high impedance, ? = indeterminate

equivalent input and output schematic diagrams

300 kΩ300 kΩ

V

CC

7 V 7 V

A Input B Input

7 V

300 kΩ

50 Ω

V

CC

Enable

Inputs

V

CC

5 Ω

7 V

Y or Z
Output

10 kΩ

300 kΩ

(EN

and SM Only)

(EN, S0, and S1 Only)

SN65LVDS116
16-PORT LVDS REPEATER

SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, Enable inputs –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A, B, Y or Z –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge, Y, Z, and GND (see Note 2) Class 3, A:12 kV, B: 500 V. . . . . . . . . . . . . . . . . . . . . . . . .

All pins Class 3, A: 4 kV, B: 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 85°C

POWER RATING

DGG 2094 mW 16.7 mW/°C 1089 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
with no air flow.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

3 3.3 3.6 V

High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

0.8 V

Magnitude of differential input voltage, VID 0.1 3.6 V

Common–mode input voltage, V

IC

Ť

V

ID

Ť

2

2.4 –

Ť

V

ID

Ť

2

V

VCC – 0.8 V

Operating free-air temperature, T

A

–40 85 °C

SN65LVDS116

16-PORT LVDS REPEATER

SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

ITH+

Positive-going differential input voltage threshold

100

V

ITH–

Negative-going differential input voltage threshold

See Figure 1 and Table 1

–100

mV

VOD Differential output voltage magnitude

247 340 454

∆VOD

Change in differential output voltage magnitude
between logic states

R

L

=

100Ω

,

V

ID

=

±100 mV

,

See Figure 1 and Figure 2

–50 50

mV

V

OC(SS)

Steady-state common-mode output voltage 1.125 1.375 V

∆V

OC(SS)

Change in steady-state common-mode output
voltage between logic states

See Figure 3

–50 50

mV

V

OC(PP)

Peak-to-peak common-mode output voltage 50 150

pp

Enabled, RL = 100Ω 84 115

ICCSupply current

Disabled 3.2 6

mA

p

p

VI = 0 V –2 –20

IIInput current (A or B inputs)

‡

VI = 2.4 V –1.2

µ

A

I

I(OFF)

Power-off Input current (A or B inputs) VCC= 1.5 V , VI= 2.4 V 20 µA

p

ENx, S0, S1

20

IIHHigh-level input current

ENx, SM

V

IH

= 2

V

–20

µ

A

p

ENx, S0, S1

10

IILLow-level input current

ENx, SM

V

IL

=

0.8 V

–10

µ

A

p

VOY or VOZ = 0 V ±24

IOSShort-circuit output current

VOD = 0 V ±12

mA

I

OZ

High-impedance output current VO = 0 V or V

CC

±1 µA

I

O(OFF)

Power-off output current VCC = 1.5 V, VO = 3.6 V ±1 µA

C

IN

Input capacitance (A or B inputs) VI = 0.4 sin (4E6πt) + 0.5 V 5

p

C

O

Output capacitance (Y or Z outputs) VI = 0.4 sin (4E6πt) + 0.5 V 9.4

pF

†

All typical values are at 25°C and with a 3.3 V supply.

‡

The non-algebraic convention, where the more positive (least negative) limit is designated minimum, is used in this data sheet for the input current
(II) only.

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

Propagation delay time, low-to-high-level output 2.2 3.1 4.7

t

PHL

Propagation delay time, high-to-low-level output 2.2 3.1 4.7

ns

t

r

Differential output signal rise time

=

0.3 0.8 1.2

t

f

Differential output signal fall time

R

L

=

100 Ω

,

CL = 10 pF,

0.3 0.8 1.2

ns

t

sk(p)

Pulse skew (|t

PHL

- t

PLH

|)

‡

See Figure 4

140 500

p

t

sk(o)

Output skew, channel-to-channel

§

100 300

ps

t

sk(pp)

Part-to-part skew

¶

1.5 ns

t

PZH

Propagation delay time, high-impedance-to-high-level output 5.7 15

t

PZL

Propagation delay time, high-impedance-to-low-level output

7.7 15

ns

t

PHZ

Propagation delay time, high-level-to-high-impedance output

See Figure 5

3.2 15

t

PLZ

Propagation delay time, low-level-to-high-impedance output 3.2 15 ns

†

All typical values are at 25°C and with a 3.3 V supply.

‡

t

sk(p)

is the magnitude of the time difference between the t

PLH

and t

PHL

of any output of a single device.

§

t

sk(o)

is the magnitude of the time difference between the t

PLH

or t

PHL

measured at any two outputs.

¶

t

sk(pp)

is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.