TEXAS INSTRUMENTS PCI1420 Technical data

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PCI1420

PC Card Controllers

Data Manual

Literature Number: SCPS047

April 1999

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify , before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.

TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
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Copyright  1999, Texas Instruments Incorporated

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Related Documents 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Feature/Protocol Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Power Supply Sequencing 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 I/O Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Clamping Voltages 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Peripheral Component Interconnect (PCI) Interface 3–2. . . . . . . . . . . . . .

3.4.1 PCI Bus Lock (LOCK

3.4.2 Loading Subsystem Identification 3–3. . . . . . . . . . . . . . . . . . . . .

3.5 PC Card Applications 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 PC Card Insertion/Removal and Recognition 3–3. . . . . . . . . . .

3.5.2 P

3.5.3 Zoomed Video Support 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.4 Ultra Zoomed Video 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.5 Internal Ring Oscillator 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.6 Integrated Pullup Resistors 3–7. . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.7 SPKROUT and CAUDPWM Usage 3–7. . . . . . . . . . . . . . . . . . .

3.5.8 LED Socket Activity Indicators 3–8. . . . . . . . . . . . . . . . . . . . . . . .

3.5.9 PC Card-16 Distributed DMA Support 3–8. . . . . . . . . . . . . . . . .

3.5.10 PC Card-16 PC/PCI DMA 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.11 CardBus Socket Registers 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Serial Bus Interface 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 Serial Bus Interface Implementation 3–11. . . . . . . . . . . . . . . . . . .

3.6.2 Serial Bus Interface Protocol 3–11. . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3 Serial Bus EEPROM Application 3–13. . . . . . . . . . . . . . . . . . . . . .

3.6.4 Serial Bus Power Switch Application 3–14. . . . . . . . . . . . . . . . . .

3.6.5 Accessing Serial Bus Devices Through Software 3–15. . . . . . . .

3.7 Programmable Interrupt Subsystem 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 PC Card Functional and Card Status Change Interrupts 3–15.

3.7.2 Interrupt Masks and Flags 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3 Using Parallel IRQ Interrupts 3–18. . . . . . . . . . . . . . . . . . . . . . . . .

3.7.4 Using Parallel PCI Interrupts 3–18. . . . . . . . . . . . . . . . . . . . . . . . .

2

C Power-Switch Interface (TPS2206/2216) 3–4. . . . . . . . . .

) 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

3.7.5 Using Serialized IRQSER Interrupts 3–19. . . . . . . . . . . . . . . . . . .

3.7.6 SMI Support in the PCI1420 3–19. . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Power Management Overview 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 Clock Run Protocol 3–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.2 CardBus PC Card Power Management 3–20. . . . . . . . . . . . . . . .

3.8.3 16-Bit PC Card Power Management 3–20. . . . . . . . . . . . . . . . . . .

3.8.4 Suspend Mode 3–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.5 Requirements for Suspend Mode 3–21. . . . . . . . . . . . . . . . . . . . .

3.8.6 Ring Indicate 3–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.7 PCI Power Management 3–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.8 CardBus Device Class Power Management 3–23. . . . . . . . . . . .

3.8.9 ACPI Support 3–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.10 Master List of PME

Context Bits and

Global Reset Only Bits 3–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 PC Card Controller Programming Model 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 PCI Configuration Registers (Functions 0 and 1) 4–1. . . . . . . . . . . . . . . . .

4.2 Vendor ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Device ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Revision ID Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 PCI Class Code Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Cache Line Size Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Latency Timer Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 Header Type Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 BIST Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 CardBus Socket Registers/ExCA Base-Address Register 4–7. . . . . . . . .

4.13 Capability Pointer Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Secondary Status Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 PCI Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 CardBus Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Subordinate Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18 CardBus Latency Timer Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 Memory Base Registers 0, 1 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.20 Memory Limit Registers 0, 1 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.21 I/O Base Registers 0, 1 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 I/O Limit Registers 0, 1 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 Interrupt Line Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.24 Interrupt Pin Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.25 Bridge Control Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.26 Subsystem Vendor ID Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.27 Subsystem ID Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.28 PC Card 16-bit I/F Legacy-Mode Base Address Register 4–15. . . . . . . . .

4.29 System Control Register 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

4.30 Multifunction Routing Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.31 Retry Status Register 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.32 Card Control Register 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.33 Device Control Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.34 Diagnostic Register 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.35 Socket DMA Register 0 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.36 Socket DMA Register 1 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.37 Capability ID Register 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.38 Next-Item Pointer Register 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.39 Power Management Capabilities Register 4–28. . . . . . . . . . . . . . . . . . . . . .

4.40 Power Management Control/Status Register 4–29. . . . . . . . . . . . . . . . . . . .

4.41 Power Management Control/Status Register Bridge

Support Extensions 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.42 Power Management Data Register 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.43 General-Purpose Event Status Register 4–31. . . . . . . . . . . . . . . . . . . . . . . .

4.44 General-Purpose Event Enable Register 4–32. . . . . . . . . . . . . . . . . . . . . . .

4.45 General-Purpose Input Register 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.46 General-Purpose Output Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.47 Serial Bus Data Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.48 Serial Bus Index Register 4–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.49 Serial Bus Slave Address Register 4–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.50 Serial Bus Control and Status Register 4–36. . . . . . . . . . . . . . . . . . . . . . . . .

5 ExCA Compatibility Registers (Functions 0 and 1) 5–1. . . . . . . . . . . . . . . . . .

5.1 ExCA Identification and Revision Register (Index 00h) 5–5. . . . . . . . . . .

5.2 ExCA Interface Status Register (Index 01h) 5–6. . . . . . . . . . . . . . . . . . . . .

5.3 ExCA Power Control Register (Index 02h) 5–7. . . . . . . . . . . . . . . . . . . . . .

5.4 ExCA Interrupt and General-Control Register (Index 03h) 5–8. . . . . . . . .

5.5 ExCA Card Status-Change Register (Index 04h) 5–9. . . . . . . . . . . . . . . . .

5.6 ExCA Card Status-Change-Interrupt Configuration

Register (Index 05h) 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 ExCA Address Window Enable Register (Index 06h) 5–11. . . . . . . . . . . . .

5.8 ExCA I/O Window Control Register (Index 07h) 5–12. . . . . . . . . . . . . . . . .

5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte

Registers (Index 08h, 0Ch) 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte

Registers (Index 09h, 0Dh) 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte

Registers (Index 0Ah, 0Eh) 5–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte

Registers (Index 0Bh, 0Fh) 5–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte

Registers (Index 10h, 18h, 20h, 28h, 30h) 5–15. . . . . . . . . . . . . . . . . . . . . .

5.14 ExCA Memory Windows 0–4 Start-Address High-Byte

Registers (Index 11h, 19h, 21h, 29h, 31h) 5–16. . . . . . . . . . . . . . . . . . . . . .

5.15 ExCA Memory Windows 0–4 End-Address Low-Byte

Registers (Index 12h, 1Ah, 22h, 2Ah, 32h) 5–17. . . . . . . . . . . . . . . . . . . . . .

v

5.16 ExCA Memory Windows 0–4 End-Address High-Byte

Registers (Index 13h, 1Bh, 23h, 2Bh, 33h) 5–18. . . . . . . . . . . . . . . . . . . . .

5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte

Registers (Index 14h, 1Ch, 24h, 2Ch, 34h) 5–19. . . . . . . . . . . . . . . . . . . . .

5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte

Registers (Index 15h, 1Dh, 25h, 2Dh, 35h) 5–20. . . . . . . . . . . . . . . . . . . . .

5.19 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte

Registers (Index 36h, 38h) 5–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.20 ExCA I/O Windows 0 and 1 Offset-Address High-Byte

Registers (Index 37h, 39h) 5–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.21 ExCA Card Detect and General Control Register (Index 16h) 5–22. . . . . .

5.22 ExCA Global Control Register (Index 1Eh) 5–23. . . . . . . . . . . . . . . . . . . . . .

5.23 ExCA Memory Windows 0–4 Page Register 5–24. . . . . . . . . . . . . . . . . . . .

6 CardBus Socket Registers (Functions 0 and 1) 6–1. . . . . . . . . . . . . . . . . . . . . .

6.1 Socket Event Register 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Socket Mask Register 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Socket Present State Register 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Socket Force Event Register 6–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Socket Control Register 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 Socket Power Management Register 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Distributed DMA (DDMA) Registers 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 DMA Current Address/Base Address Register 7–1. . . . . . . . . . . . . . . . . . .

7.2 DMA Page Register 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 DMA Current Count/Base Count Register 7–2. . . . . . . . . . . . . . . . . . . . . . .

7.4 DMA Command Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 DMA Status Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 DMA Request Register 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 DMA Mode Register 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8 DMA Master Clear Register 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9 DMA Multichannel/Mask Register 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Electrical Characteristics 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Absolute Maximum Ratings Over Operating

Temperature Ranges 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Recommended Operating Conditions 8–2. . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Electrical Characteristics Over Recommended

Operating Conditions 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 PCI Clock/Reset Timing Requirements Over Recommended
Ranges Of Supply Voltage And Operating Free-air Temperature 8–3. . .

8.5 PCI Timing Requirements Over Recommended Ranges

of Supply Voltage and Operating Free-air Temperature 8–4. . . . . . . . . . .

9 Mechanical Information 9–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Illustrations

Figure Title Page

2–1 PCI-to-CardBus Pin Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 PCI-to-PC Card (16-Bit) Diagram 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 PCI1420 Simplified Block Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 3-State Bidirectional Buffer 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 TPS2206 Terminal Assignments 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 TPS2206 Typical Application 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Zoomed Video Implementation Using PCI1420 3–5. . . . . . . . . . . . . . . . . . . . . . .

3–6 Zoomed Video Switching Application 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Sample Application of SPKROUT and CAUDPWM 3–8. . . . . . . . . . . . . . . . . . . .

3–8 Two Sample LED Circuits 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Serial EEPROM Application 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 Serial Bus Start/Stop Conditions and Bit Transfers 3–12. . . . . . . . . . . . . . . . . . .

3–11 Serial Bus Protocol Acknowledge 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 Serial Bus Protocol – Byte Write 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–13 Serial Bus Protocol – Byte Read 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–14 EEPROM Interface Doubleword Data Collection 3–13. . . . . . . . . . . . . . . . . . . . .

3–15 EEPROM Data Format 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–16 Send Byte Protocol 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–17 IRQ Implementation 3–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–18 Suspend Functional Implementation 3–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–19 Signal Diagram of Suspend Function 3–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–20 RI_OUT

3–21 Block Diagram of a Status/Enable Cell 3–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 ExCA Register Access Through I/O 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 ExCA Register Access Through Memory 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Accessing CardBus Socket Registers Through PCI Memory 6–1. . . . . . . . . . . .

Functional Diagram 3–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

List of Tables

Table Title Page

2–1 CardBus PC Card Signal Names by GHK/PDV Pin Number 2–3. . . . . . . . . . . .

2–2 CardBus PC Card Signal Names Sorted Alphabetically 2–4. . . . . . . . . . . . . . . .

2–3 16-Bit PC Card Signal Names by GHK/PDV Pin Number 2–5. . . . . . . . . . . . . . .

2–4 16-Bit PC Card Signal Names Sorted Alphabetically 2–7. . . . . . . . . . . . . . . . . . .

2–5 Power Supply 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 PC Card Power Switch 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 PCI System 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 PCI Address and Data 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 PCI Interface Control 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Multifunction and Miscellaneous Pins 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 16-Bit PC Card Address and Data (Slots A and B) 2–13. . . . . . . . . . . . . . . . . . . .

2–12 16-Bit PC Card Interface Control (Slots A and B) 2–14. . . . . . . . . . . . . . . . . . . . .

2–13 CardBus PC Card Interface System (Slots A and B) 2–16. . . . . . . . . . . . . . . . . .

2–14 CardBus PC Card Address and Data (Slots A and B) 2–17. . . . . . . . . . . . . . . . .

2–15 CardBus PC Card Interface Control (Slots A and B) 2–18. . . . . . . . . . . . . . . . . .

3–1 PC Card Card-Detect and Voltage-Sense Connections 3–4. . . . . . . . . . . . . . . .

3–2 PC Card Card-Detect and Voltage-Sense Connections 3–6. . . . . . . . . . . . . . . .

3–3 Distributed DMA Registers 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 PC/PCI Channel Assignments 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 I/O Addresses Used for PC/PCI DMA 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 CardBus Socket Registers 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Registers and Bits Loadable Through Serial EEPROM 3–13. . . . . . . . . . . . . . . . .

3–8 PCI1420 Registers Used to Program Serial Bus Devices 3–15. . . . . . . . . . . . . . .

3–9 Interrupt Mask and Flag Registers 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 PC Card Interrupt Events and Description 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 Interrupt Pin Register Cross Reference 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 SMI Control 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–13 Power Management Registers 3–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 PCI Configuration Registers (Functions 0 and 1) 4–1. . . . . . . . . . . . . . . . . . . . . .

4–2 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Secondary Status Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Interrupt Pin Register Cross Reference 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Bridge Control Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 System Control Register 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Multifunction Routing Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 Retry Status Register 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

4–10 Card Control Register 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 Device Control Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–12 Diagnostic Register 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–13 Socket DMA Register 0 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–14 Socket DMA Register 1 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–15 Power Management Capabilities Register 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . .

4–16 Power Management Control/Status Register 4–29. . . . . . . . . . . . . . . . . . . . . . . .

4–17 Power Management Control/Status Register Bridge

Support Extensions 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–18 General-Purpose Event Status Register 4–31. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–19 General-Purpose Event Enable Register 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–20 General-Purpose Input Register 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–21 General-Purpose Output Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–22 Serial Bus Data Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–23 Serial Bus Index Register 4–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–24 Serial Bus Slave Address Register 4–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–25 Serial Bus Control and Status Register 4–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 ExCA Registers and Offsets 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 ExCA Identification and Revision Register (Index 00h) 5–5. . . . . . . . . . . . . . . . .

5–3 ExCA Interface Status Register (Index 01h) 5–6. . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 ExCA Power Control Register 82365SL Support (Index 02h) 5–7. . . . . . . . . . .

5–5 ExCA Power Control Register 82365SL-DF Support (Index 02h) 5–7. . . . . . . .

5–6 ExCA Interrupt and General-Control Register (Index 03h) 5–8. . . . . . . . . . . . . .

5–7 ExCA Card Status-Change Register (Index 04h) 5–9. . . . . . . . . . . . . . . . . . . . . .

5–8 ExCA Card Status-Change-Interrupt Configuration Register

(Index 05h) 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 ExCA Address Window Enable Register (Index 06h) 5–11. . . . . . . . . . . . . . . . . .

5–10 ExCA I/O Window Control Register (Index 07h) 5–12. . . . . . . . . . . . . . . . . . . . . .

5–11 ExCA Memory Windows 0–4 Start-Address High-Byte Registers

(Index 11h, 19h, 21h, 29h, 31h) 5–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 ExCA Memory Windows 0–4 End-Address High-Byte Registers

(Index 13h, 1Bh, 23h, 2Bh, 33h) 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers

(Index 15h, 1Dh, 25h, 2Dh, 35h) 5–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 ExCA Card Detect and General Control Register (Index 16h) 5–22. . . . . . . . . .

5–15 ExCA Global Control Register (Index 1Eh) 5–23. . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 CardBus Socket Registers 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Socket Event Register 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Socket Mask Register 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 Socket Present State Register 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 Socket Force Event Register 6–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–6 Socket Control Register 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–7 Socket Power Management Register 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

7–1 Distributed DMA Registers 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 DMA Command Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 DMA Status Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 DMA Mode Register 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 DMA Multichannel/Mask Register 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x

1 Introduction

1.1 Description

The TI PCI1420, the industry’s first 208-pin controller to meet the

for PCI to CardBus Bridges

sockets compliant with the
bridging between PCI and PC Cards in both notebook and desktop computers. The
the 16-bit PC Card specification defined in
capable of full 32-bit data transfers at 33 MHz. The PCI1420 supports any combination of 16-bit and CardBus PC
Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1420 is compliant with the
device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus
PC Card bridging transactions. The PCI1420 is also compliant with the latest

Specification

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1420 is
register compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1420 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI1420 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1420, such as socket activity light-emitting diode (LED)
outputs, are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management
system to further reduce power consumption.

.

, is a high-performance PCI-to-CardBus controller that supports two independent card

1997 PC Card Standard

. The PCI1420 provides features that make it the best choice for

PCI Local Bus Specification

PCI Local Bus Specification

PCI Bus Power Management Interface Specification

1997 PC Card Standard

and defines the new 32-bit PC Card, CardBus,

, and its PCI interface can act as either a PCI master

retains

PCI Bus Power Management Interface

1.2 Features

The PCI1420 supports the following features:

• Fully compatible with the Intel 430TX (Mobile Triton II) chipset

• A 208-Pin Low-Profile QFP (PDV) or MicroStar Ball Grid Array (GHK) package

• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

• Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards

• Two PC Card or CardBus slots with hot insertion and removal

• Uses serial interface to TI TPS2206/2216 dual-slot PC Card power switch

• Burst transfers to maximize data throughput with CardBus Cards

• Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI

interrupts, and serial ISA IRQ and PCI interrupts

• Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

• Pipelined architecture allows greater than 130M bps throughput from CardBus-to-PCI and from

PCI-to-CardBus

1–1

• Up to five general-purpose I/Os

• Programmable output select for CLKRUN

• Multifunction PCI device with separate configuration space for each socket

• Five PCI memory windows and two I/O windows available for each R2 socket

• Two I/O windows and two memory windows available to each CardBus socket

• Exchangeable Card Architecture (ExCA) compatible registers are mapped in memory and I/O space

• Intel 82365SL-DF and 82365SL register compatible

• Distributed DMA (DDMA) and PC/PCI DMA

• 16-Bit DMA on both PC Card sockets

• Ring indicate, SUSPEND

, PCI CLKRUN, and CardBus CCLKRUN

• Socket activity LED pins

• PCI Bus Lock (LOCK

)

• Advanced Submicron, Low-Power CMOS Technology

• Internal Ring Oscillator

1.3 Related Documents

•

Advanced Configuration and Power Interface (ACPI) Specification

•

PCI Bus Power Management Interface Specification

•

PCI Bus Power Management Interface Specification for PCI to CardBus Bridges

•

PCI to PCMCIA CardBus Bridge Register Description

•

PCI Local Bus Specification

•

PCI Mobile Design Guide

•

PCI14xx Implemenation Guide for D3 Wake-Up

•

1997 PC Card Standard

•

PC 99

•

Serialized IRQ Support for PCI Systems

(Revision 2.2)

(Revision 1.0)

(Revision 6)

(Revision 1.0)

(Revision 1.1)

(Revision 0.6)

(Yenta) (Revision 2.1)

1.4 Ordering Information

ORDERING NUMBER NAME VOLTAGE PACKAGE

PCI1420 PC Card Controller 3.3 V, 5-V T olerant I/Os 208-pin LQFP

209-ball PBGA

1–2

2 Terminal Descriptions

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

C/BE3

RI_OUT/PME

V

CC

AD25

PRST

GND

GNT

REQ
AD31
AD30
AD11
AD29
AD28

GRST

AD27
AD26

V

CCP

AD24

PCLK

GND

IDSEL

AD23
AD22
AD21
AD20

V

CC
AD19
AD18
AD17
AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP
PERR
SERR

V

CC

PAR

C/BE1

AD15
AD14
AD13

GND

AD12

SUSPEND

GND

MFUNC0

DATA

MFUNC1

152

154

153

156

155

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

LATCH

CLOCK

150

151

CCI

SPKROUT

A_CAD31

V

148

147

149

A_CAD30

A_RSVD

A_CAD29

144

146

145

CC

A_CAD28

V

142

143

A_CCD2

A_CAD27

A_CCLKRUN

140

139

141

A_CAUDIO

A_CSTSCHG

A_CINT

A_CSERR

136

135

138

137

A_CAD26

A_CVS1

A_CAD25

132

134

133

PCI1420 CorePCI

A_CC/BE3

A_CAD24

GND

130

129

131

A_CAD23

A_CAD22

A_CREQ

126

128

127

Card A

A_CAD21

A_CRST

124

125

A_CAD20

A_CAD19

A_CVS2

122

121

123

Card B

CCA

A_CAD18

V

119

120

A_CC/BE2

A_CAD17

118

117

CC

A_CFRAME

A_CTRDY

A_CIRDY

114

113

116

115

A_CCLKVA_CDEVSEL

112

A_CGNT

111

110

A_CSTOP

A_CBLOCK

A_CPERR

108

107

109

A_RSVD

A_CPAR

105
104

103
102
101
100

51 106

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53

A_CC/BE1
A_CAD16
A_CAD14
A_CAD15
A_CAD12
A_CAD13
A_CAD11
A_CAD10
GND
A_CAD9
A_CC/BE0
A_CAD8
A_CAD7
A_RSVD
A_CAD5
A_CAD6
A_CAD3
A_CAD4
V

CC

A_CAD1
A_CAD2
A_CAD0
A_CCD1
B_CAD31
B_RSVD
B_CAD30
B_CAD29
B_CAD28
B_CAD27
GND
B_CCD2
B_CCLKRUN
B_CSTSCHG
B_CAUDIO
B_CSERR
B_CINT
B_CVS1
B_CAD26
B_CAD25
B_CAD24
V

CC

B_CC/BE3
B_CAD23
B_CREQ
B_CAD22
B_CAD21
B_CRST
B_CAD20
B_CVS2
B_CAD19
B_CAD18
B_CAD17

CCP

V

AD10

AD9

AD8

AD7

C/BE0

CC

AD4

AD6

AD5

AD3

AD1

AD0

V

AD2

GND

B_CAD0

B_CAD2

B_CCD1

B_CAD1

B_CAD4

B_CAD3

GND

B_CAD6

B_CAD5

B_CAD7

B_RSVD

B_CAD8

B_CAD9

B_CAD10

B_CC/BE0

CC

V

B_CAD11

B_CAD13

B_CAD14

B_CAD12

B_CAD15

CCB

V

B_CAD16

B_CC/BE1

B_CPAR

B_RSVD

B_CBLOCK

GND

B_CSTOP

B_CPERR

B_CCLK

B_CGNT

B_CDEVSEL

B_CIRDY

B_CTRDY

B_CFRAME

B_CC/BE2

Figure 2–1. PCI-to-CardBus Pin Diagram

2–1

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

C/BE3

RI_OUT/PME

V

CC

AD25

PRST

GND

GNT

REQ
AD31
AD30
AD11
AD29
AD28
GRST
AD27
AD26

V

CCP
AD24
PCLK

GND

IDSEL

AD23
AD22
AD21
AD20

V

CC
AD19
AD18
AD17

AD16

C/BE2

FRAME

GND
IRDY

TRDY

DEVSEL

STOP

PERR
SERR

V

CC

PAR

C/BE1

AD15
AD14
AD13

GND

AD12

A_D10

A_D2

146

147

A_D9

145

A_D1

144

CC

V

143

A_D8

A_D0

142

141

A_CD2

A_WP(IOIS16)

140

139

A_BVD1(STSCHG/RI)

A_READY(IREQ)

A_WAIT

A_A0

A_VS1

A_A2

136

135

134

133

A_A1

132

131

A_BVD2(SPKR)

138

137

PCI1420 CorePCI

A_REG

GND

130

129

Card A

A_A3

128

A_INPACK

127

A_A4

126

A_A5

A_RESET

124

125

A_A6

A_A25

A_VS2

122

121

123

Card B

CCA

V

120

A_A7

119

A_A12

A_A24

118

117

A_A23

A_A15

116

115

CC

A_A22

114

113

A_A16VA_A21

112

CCI

SPKROUT

GND

MFUNC0

DATA

LATCH

CLOCK

152

151

150

149

V

148

SUSPEND

MFUNC1

154

153

156

155

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

111

A_A20

A_WE

110

109

A_A19

A_A14

108

107

A_A18

A_A13

105
104

A_A8

103

A_A17

102

A_A9

101

A_IOWR

100

A_A11

99

A_IORD

98

A_OE

97

A_CE2

96

GND

95

A_A10

94

A_CE1

93

A_D15

92

A_D7

91

A_D14

90

A_D6

89

A_D13

88

A_D5
A_D12

87

V

86
85

A_D4

84

A_D11
A_D3

83
82

A_CD1

81

B_D10

80

B_D2

79

B_D9

78

B_D1

77

B_D8

76

B_D0

75

GND

74

B_CD2

73

B_WP(IOIS16)

72

B_BVD1(STSCHG/RI)

71

B_BVD2(SPKR)

70

B_WAIT

69

B_READY(IREQ)

68

B_VS1

67

B_A0

66

B_A1
B_A2

65
64

V

63

B_REG

62

B_A3

61

B_INPACK

60

B_A4

59

B_A5

58

B_RESET

57

B_A6

56

B_VS2

55

B_A25

54

B_A7

53

B_A24

51 106

CC

CC

2–2

V

CCP

AD10

AD9

AD8

AD7

C/BE0

CC

AD6

AD5

AD3

AD1

AD2

GND

AD0

B_D3

B_CD1

GND

B_D4

B_D5

B_D6

B_D11

B_D12

B_D13

B_D7

B_D14

AD4

V

B_D15

B_CE1

B_A10

B_CE2

V

CC

B_OE

B_IORD

B_A11

B_IOWR

B_A9

CCB

V

B_A17

B_A8

B_A13

B_A18

B_A14

B_A19

GND

B_WE

B_A20

B_A21

B_A16

B_A15

B_A22

B_A23

B_A12

Figure 2–2. PCI-to-PC Card (16-Bit) Diagram

Table 2–1 and Table 2–2 show the terminal assignments for the CardBus PC Card; Table 2–3 and Table 2–4 show

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

the terminal assignments for the 16-bit PC Card. Table 2–1 and Table 2–3 show the CardBus PC Card and the 16-bit
PC Card terminals sorted alphanumerically by the associated GHK package terminal number. Table 2–2 and
Table 2–4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name
and its associated terminal numbers. Pin E5 is a no connection identification ball.

Table 2–1. CardBus PC Card Signal Names by GHK/PDV Pin Number

PIN NO.

GHK PDV

A4 208 AD12 E3 2 AD10 G19 143 V
A5 203 C/BE1 E6 206 AD13 H1 18 B_CAD2 L19 123 A_CAD20
A6 199 PERR E7 201 V
A7 195 IRDY E8 194 GND H3 16 B_CCD1 M2 35 B_CAD15
A8 190 AD17 E9 189 AD18 H5 15 AD0 M3 36 B_CAD14

A9 185 AD21 E10 183 AD23 H6 11 AD3 M5 38 V
A10 180 PCLK E11 178 V
A11 175 GRST E12 171 AD30 H15 142 A_CAD28 M14 115 A_CIRDY
A12 174 AD28 E13 165 AD25 H17 140 A_CCD2 M15 119 A_CAD18
A13 170 AD31 E14 159 MFUNC4 H18 139 A_CCLKRUN M17 120 V
A14 166 PRST E17 155 MFUNC1 H19 138 A_CSTSCHG M18 121 A_CAD19
A15 162 C/BE3 E18 153 GND J1 19 B_CAD1 M19 122 A_CVS2
A16 157 MFUNC2 E19 151 CLOCK J2 20 B_CAD4 N1 39 B_CC/BE1

B5 205 AD14 F1 10 AD4 J3 21 B_CAD3 N2 40 B_RSVD

B6 200 SERR F2 8 AD6 J5 22 GND N3 41 B_CPAR

B7 196 TRDY F3 7 V

B8 191 AD16 F5 3 AD9 J14 136 A_CSERR N6 42 B_CBLOCK

B9 186 AD20 F6 204 AD15 J15 137 A_CAUDIO N14 108 A_CPERR
B10 181 GND F7 198 STOP J17 135 A_CINT N15 113 V
B11 176 AD27 F8 193 FRAME J18 134 A_CVS1 N17 116 A_CFRAME
B12 173 AD29 F9 188 AD19 J19 133 A_CAD26 N18 117 A_CC/BE2
B13 169 REQ F10 184 AD22 K1 24 B_CAD5 N19 118 A_CAD17
B14 164 V
B15 161 MFUNC6/CLKRUN F12 167 GND K3 26 B_CAD7 P2 44 GND

C5 207 GND F13 160 MFUNC5 K5 27 B_CAD8 P3 46 B_CGNT

C6 202 PAR F14 152 DATA K6 28 B_CC/BE0 P5 50 B_CIRDY

C7 197 DEVSEL F15 154 MFUNC0 K14 132 A_CAD25 P6 48 B_CCLK

C8 192 C/BE2 F17 150 LATCH K15 131 A_CAD24 P7 56 B_CVS2

C9 187 V
C10 182 IDSEL F19 147 A_CAD31 K18 129 GND P9 75 GND
C11 177 AD26 G1 14 AD1 K19 128 A_CAD23 P10 80 B_RSVD
C12 172 AD11 G2 13 GND L1 29 B_CAD9 P11 84 A_CAD2
C13 168 GNT G3 12 AD2 L2 30 B_CAD10 P12 89 A_CAD6
C14 163 RI_OUT/PME G5 9 AD5 L3 31 V
C15 158 MFUNC3 G6 4 AD8 L5 33 B_CAD13 P14 100 A_CAD12

D1 1 V
D19 156 SUSPEND G15 149 SPKROUT L14 127 A_CREQ P17 111 A_CDEVSEL

E1 6 AD7 G17 145 A_CAD30 L15 126 A_CAD22 P18 112 A_CCLK

E2 5 C/BE0 G18 144 A_CAD29 L17 125 A_CAD21 P19 114 A_CTRDY

CC

CC

CCP

PIN NO.

GHK PDV

CC

CCP

CC

F11 179 AD24 K2 25 B_RSVD P1 43 B_CPERR

F18 148 V

G14 146 A_RSVD L6 32 B_CAD11 P15 107 A_CBLOCK

CCI

PIN NO.

GHK PDV

CC

H2 17 B_CAD0 M1 34 B_CAD12

H14 141 A_CAD27 M6 37 B_CAD16

J6 23 B_CAD6 N5 45 B_CSTOP

K17 130 A_CC/BE3 P8 63 B_CC/BE3

CC

PIN NO.

GHK PDV

L18 124 A_CRST

CCB

CCA

CC

P13 94 A_CC/BE0

2–3

Table 2–1. CardBus PC Card Signal Names by GHK/PDV Pin Number (Continued)

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PIN NO.

GHK PDV

R1 47 B_CDEVSEL R18 109 A_CSTOP U14 98 A_CAD11 W4 53 B_CAD17
R2 49 B_CTRDY R19 110 A_CGNT U15 103 A_CAD16 W5 58 B_CRST
R3 51 B_CFRAME T1 52 B_CC/BE2 V5 57 B_CAD20 W6 62 B_CAD23
R6 55 B_CAD19 T19 105 A_RSVD V6 60 B_CAD22 W7 66 B_CAD25
R7 61 B_CREQ U5 54 B_CAD18 V7 65 B_CAD24 W8 70 B_CSERR
R8 67 B_CAD26 U6 59 B_CAD21 V8 69 B_CINT W9 71 B_CAUDIO

R9 74 B_CCD2 U7 64 V
R10 79 B_CAD30 U8 68 B_CVS1 V10 77 B_CAD28 W11 81 B_CAD31
R11 85 A_CAD1 U9 73 B_CCLKRUN V11 82 A_CCD1 W12 86 V
R12 90 A_CAD5 U10 78 B_CAD29 V12 87 A_CAD4 W13 91 A_RSVD
R13 97 A_CAD10 U11 83 A_CAD0 V13 92 A_CAD7 W14 95 A_CAD9
R14 102 A_CAD14 U12 88 A_CAD3 V14 96 GND W15 99 A_CAD13
R17 106 A_CPAR U13 93 A_CAD8 V15 101 A_CAD15 W16 104 A_CC/BE1

PIN NO.

GHK PDV

CC

PIN NO.

GHK PDV

V9 72 B_CSTSCHG W10 76 B_CAD27

PIN NO.

GHK PDV

CC

Table 2–2. CardBus PC Card Signal Names Sorted Alphabetically

PIN NO.

GHK PDV

A_CAD0 U11 83 A_CAD27 H14 141 A_CTRDY P19 114 AD21 A9 185
A_CAD1 R11 85 A_CAD28 H15 142 A_CVS1 J18 134 AD22 F10 184
A_CAD2 P11 84 A_CAD29 G18 144 A_CVS2 M19 122 AD23 E10 183
A_CAD3 U12 88 A_CAD30 G17 145 A_RSVD G14 146 AD24 F11 179
A_CAD4 V12 87 A_CAD31 F19 147 A_RSVD T19 105 AD25 E13 165
A_CAD5 R12 90 A_CAUDIO J15 137 A_RSVD W13 91 AD26 C11 177
A_CAD6 P12 89 A_CBLOCK P15 107 AD0 H5 15 AD27 B11 176
A_CAD7 V13 92 A_CC/BE0 P13 94 AD1 G1 14 AD28 A12 174
A_CAD8 U13 93 A_CC/BE1 W16 104 AD2 G3 12 AD29 B12 173
A_CAD9 W14 95 A_CC/BE2 N18 117 AD3 H6 11 AD30 E12 171
A_CAD10 R13 97 A_CC/BE3 K17 130 AD4 F1 10 AD31 A13 170
A_CAD11 U14 98 A_CCD1 V11 82 AD5 G5 9 B_CAD0 H2 17
A_CAD12 P14 100 A_CCD2 H17 140 AD6 F2 8 B_CAD1 J1 19
A_CAD13 W15 99 A_CCLK P18 112 AD7 E1 6 B_CAD2 H1 18
A_CAD14 R14 102 A_CCLKRUN H18 139 AD8 G6 4 B_CAD3 J3 21
A_CAD15 V15 101 A_CDEVSEL P17 111 AD9 F5 3 B_CAD4 J2 20
A_CAD16 U15 103 A_CFRAME N17 116 AD10 E3 2 B_CAD5 K1 24
A_CAD17 N19 118 A_CGNT R19 110 AD11 C12 172 B_CAD6 J6 23
A_CAD18 M15 119 A_CINT J17 135 AD12 A4 208 B_CAD7 K3 26
A_CAD19 M18 121 A_CIRDY M14 115 AD13 E6 206 B_CAD8 K5 27
A_CAD20 L19 123 A_CPAR R17 106 AD14 B5 205 B_CAD9 L1 29
A_CAD21 L17 125 A_CPERR N14 108 AD15 F6 204 B_CAD10 L2 30
A_CAD22 L15 126 A_CREQ L14 127 AD16 B8 191 B_CAD11 L6 32
A_CAD23 K19 128 A_CRST L18 124 AD17 A8 190 B_CAD12 M1 34
A_CAD24 K15 131 A_CSERR J14 136 AD18 E9 189 B_CAD13 L5 33
A_CAD25 K14 132 A_CSTOP R18 109 AD19 F9 188 B_CAD14 M3 36
A_CAD26 J19 133 A_CSTSCHG H19 138 AD20 B9 186 B_CAD15 M2 35

PIN NO.

GHK PDV

PIN NO.

GHK PDV

PIN NO.

GHK PDV

2–4

Table 2–2. CardBus PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PIN NO.

GHK PDV

B_CAD16 M6 37 B_CCLKRUN U9 73 DEVSEL C7 197 PAR C6 202
B_CAD17 W4 53 B_CDEVSEL R1 47 FRAME F8 193 PCLK A10 180
B_CAD18 U5 54 B_CFRAME R3 51 GND B10 181 PERR A6 199
B_CAD19 R6 55 B_CGNT P3 46 GND C5 207 PRST A14 166
B_CAD20 V5 57 B_CINT V8 69 GND E8 194 REQ B13 169
B_CAD21 U6 59 B_CIRDY P5 50 GND E18 153 RI_OUT/PME C14 163
B_CAD22 V6 60 B_CPAR N3 41 GND F12 167 SERR B6 200
B_CAD23 W6 62 B_CPERR P1 43 GND G2 13 SPKROUT G15 149
B_CAD24 V7 65 B_CREQ R7 61 GND J5 22 STOP F7 198
B_CAD25 W7 66 B_CRST W5 58 GND K18 129 SUSPEND D19 156
B_CAD26 R8 67 B_CSERR W8 70 GND P2 44 TRDY B7 196
B_CAD27 W10 76 B_CSTOP N5 45 GND P9 75 V
B_CAD28 V10 77 B_CSTSCHG V9 72 GND V14 96 V
B_CAD29 U10 78 B_CTRDY R2 49 GNT C13 168 V
B_CAD30 R10 79 B_CVS1 U8 68 GRST A11 175 V
B_CAD31 W11 81 B_CVS2 P7 56 IDSEL C10 182 V
B_CAUDIO W9 71 B_RSVD K2 25 IRDY A7 195 V
B_CBLOCK N6 42 B_RSVD N2 40 LATCH F17 150 V
B_CC/BE0 K6 28 B_RSVD P10 80 MFUNC0 F15 154 V
B_CC/BE1 N1 39 C/BE0 E2 5 MFUNC1 E17 155 V
B_CC/BE2 T1 52 C/BE1 A5 203 MFUNC2 A16 157 V
B_CC/BE3 P8 63 C/BE2 C8 192 MFUNC3 C15 158 V
B_CCD1 H3 16 C/BE3 A15 162 MFUNC4 E14 159 V
B_CCD2 R9 74 CLOCK E19 151 MFUNC5 F13 160 V
B_CCLK P6 48 DATA F14 152 MFUNC6/CLKRUN B15 161 V

PIN NO.

GHK PDV

PIN NO.

GHK PDV

CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCB
CCI
CCP
CCP

PIN NO.

GHK PDV

B14 164

C9 187
E7 201
F3 7

G19 143

L3 31

N15 113

U7 64
W12 86
M17 120

M5 38

F18 148

D1 1

E11 178

PIN NO.

GHK PDV

A4 208 AD12
A5 203 C/BE1
A6 199 PERR
A7 195 IRDY
A8 190 AD17

A9 185 AD21
A10 180 PCLK
A11 175 GRST
A12 174 AD28
A13 170 AD31
A14 166 PRST
A15 162 C/BE3
A16 157 MFUNC2

B5 205 AD14

B6 200 SERR

Table 2–3. 16-Bit PC Card Signal Names by GHK/PDV Pin Number

PIN NO.

GHK PDV

B7 196 TRDY C11 177 AD26 E11 178 V
B8 191 AD16 C12 172 AD11 E12 171 AD30

B9 186 AD20 C13 168 GNT E13 165 AD25
B10 181 GND C14 163 RI_OUT/PME E14 159 MFUNC4
B11 176 AD27 C15 158 MFUNC3 E17 155 MFUNC1
B12 173 AD29 D1 1 V
B13 169 REQ D19 156 SUSPEND E19 151 CLOCK
B14 164 V
B15 161 MFUNC6 E2 5 C/BE0 F2 8 AD6

C5 207 GND E3 2 AD10 F3 7 V
C6 202 PAR E6 206 AD13 F5 3 AD9
C7 197 DEVSEL E7 201 V
C8 192 C/BE2 E8 194 GND F7 198 STOP
C9 187 V

C10 182 IDSEL E10 183 AD23 F9 188 AD19

CC

CC

PIN NO.

GHK PDV

CCP

E1 6 AD7 F1 10 AD4

CC

E9 189 AD18 F8 193 FRAME

PIN NO.

GHK PDV

E18 153 GND

F6 204 AD15

CCP

CC

2–5

Table 2–3. 16-Bit PC Card Signal Names by GHK/PDV Pin Number (Continued)

SIGNAL NAME

SIGNAL NAME

PIN NO.

GHK PDV

F10 184 AD22
F11 179 AD24
F12 167 GND
F13 160 MFUNC5
F14 152 DATA
F15 154 MFUNC0
F17 150 LATCH
F18 148 V
F19 147 A_D10

G1 14 AD1
G2 13 GND
G3 12 AD2
G5 9 AD5

G6 4 AD8
G14 146 A_D2
G15 149 SPKROUT
G17 145 A_D9
G18 144 A_D1
G19 143 V

H1 18 B_D11

H2 17 B_D3

H3 16 B_CD1

H5 15 AD0

H6 11 AD3

H14 141 A_D0
H15 142 A_D8
H17 140 A_CD2
H18 139 A_WP(IOIS16)
H19 138 A_BVD1(STSCHG/R1)

J1 19 B_D4
J2 20 B_D12
J3 21 B_D5
J5 22 GND

J6 23 B_D13
J14 136 A_WAIT
J15 137 A_BVD2(SPKR)
J17 135 A_READY(IREQ)

CCI

CC

PIN NO.

GHK PDV

J18 134 A_VS1 N14 108 A_A14 T1 52 B_A12
J19 133 A_A0 N15 113 V

K1 24 B_D6 N17 116 A_A23 U5 54 B_A7
K2 25 B_D14 N18 117 A_A12 U6 59 B_A5
K3 26 B_D7 N19 118 A_A24 U7 64 V
K5 27 B_D15 P1 43 B_A14 U8 68 B_VS1

K6 28 B_CE1 P2 44 GND U9 73 B_WP(IOIS16)
K14 132 A_A1 P3 46 B_WE U10 78 B_D1
K15 131 A_A2 P5 50 B_A15 U11 83 A_D3
K17 130 A_REG P6 48 B_A16 U12 88 A_D5
K18 129 GND P7 56 B_VS2 U13 93 A_D15
K19 128 A_A3 P8 63 B_REG U14 98 A_OE

L1 29 B_A10 P9 75 GND U15 103 A_A17

L2 30 B_CE2 P10 80 B_D2 V5 57 B_A6

L3 31 V

L5 33 B_IORD P12 89 A_D13 V7 65 B_A2

L6 32 B_OE P13 94 A_CE1 V8 69 B_READY(IREQ)

L14 127 A_INPACK P14 100 A_A11 V9 72 B_BVD1(STSCHG/R1)
L15 126 A_A4 P15 107 A_A19 V10 77 B_D8
L17 125 A_A5 P17 111 A_A21 V11 82 A_CD1
L18 124 A_RESET P18 112 A_A16 V12 87 A_D12
L19 123 A_A6 P19 114 A_A22 V13 92 A_D7

M1 34 B_A11 R1 47 B_A21 V14 96 GND
M2 35 B_IOWR R2 49 B_A22 V15 101 A_IOWR
M3 36 B_A9 R3 51 B_A23 W4 53 B_A24
M5 38 V

M6 37 B_A17 R7 61 B_INPACK W6 62 B_A3
M14 115 A_A15 R8 67 B_A0 W7 66 B_A1
M15 119 A_A7 R9 74 B_CD2 W8 70 B_WAIT
M17 120 V
M18 121 A_A25 R11 85 A_D4 W10 76 B_D0
M19 122 A_VS2 R12 90 A_D6 W11 81 B_D10

N1 39 B_A8 R13 97 A_CE2 W12 86 V

N2 40 B_A18 R14 102 A_A9 W13 91 A_D14

N3 41 B_A13 R17 106 A_A13 W14 95 A_A10

N5 45 B_A20 R18 109 A_A20 W15 99 A_IORD

N6 42 B_A19 R19 110 A_WE W16 104 A_A8

SIGNAL

NAME

CC

CCB

CCA

PIN NO.

GHK PDV

P11 84 A_D11 V6 60 B_A4

R6 55 B_A25 W5 58 B_RESET

R10 79 B_D9 W9 71 B_BVD2(SPKR)

SIGNAL

NAME

CC

PIN NO.

GHK PDV

T19 105 A_A18

CC

CC

2–6

Table 2–4. 16-Bit PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PIN NO.

GHK PDV

A_A0 J19 133 A_D11 P11 84 AD26 C11 177 B_D5 J3 21
A_A1 K14 132 A_D12 V12 87 AD27 B1 1 176 B_D6 K1 24
A_A2 K15 131 A_D13 P12 89 AD28 A12 174 B_D7 K3 26
A_A3 K19 128 A_D14 W13 91 AD29 B12 173 B_D8 V10 77
A_A4 L15 126 A_D15 U13 93 AD30 E12 171 B_D9 R10 79
A_A5 L17 125 A_INPACK L14 127 AD31 A13 170 B_D10 W11 81
A_A6 L19 123 A_IORD W15 99 B_A0 R8 67 B_D11 H1 18
A_A7 M15 119 A_IOWR V15 101 B_A1 W7 66 B_D12 J2 20
A_A8 W16 104 A_OE U14 98 B_A2 V7 65 B_D13 J6 23
A_A9 R14 102 A_READY(IREQ) J17 135 B_A3 W6 62 B_D14 K2 25
A_A10 W14 95 A_REG K17 130 B_A4 V6 60 B_D15 K5 27
A_A11 P14 100 A_RESET L18 124 B_A5 U6 59 B_INPACK R7 61
A_A12 N18 117 A_VS1 J18 134 B_A6 V5 57 B_IORD L5 33
A_A13 R17 106 A_VS2 M19 122 B_A7 U5 54 B_IOWR M2 35
A_A14 N14 108 A_WAIT J14 136 B_A8 N1 39 B_OE L6 32
A_A15 M14 115 A_WE R19 110 B_A9 M3 36 B_READY(IREQ) V8 69
A_A16 P18 112 A_WP(IOIS16) H18 139 B_A10 L1 29 B_REG P8 63
A_A17 U15 103 AD0 H5 15 B_A11 M1 34 B_RESET W5 58
A_A18 T19 105 AD1 G1 14 B_A12 T1 52 B_VS1 U8 68
A_A19 P15 107 AD2 G3 12 B_A13 N3 41 B_VS2 P7 56
A_A20 R18 109 AD3 H6 11 B_A14 P1 43 B_WAIT W8 70
A_A21 P17 111 AD4 F1 10 B_A15 P5 50 B_WE P3 46
A_A22 P19 114 AD5 G5 9 B_A16 P6 48 B_WP(IOIS16) U9 73
A_A23 N17 116 AD6 F2 8 B_A17 M6 37 C/BE0 E2 5
A_A24 N19 118 AD7 E1 6 B_A18 N2 40 C/BE1 A5 203
A_A25 M18 121 AD8 G6 4 B_A19 N6 42 C/BE2 C8 192
A_BVD1(STSCHG/R1) H19 138 AD9 F5 3 B_A20 N5 45 C/BE3 A15 162
A_BVD2(SPKR) J15 137 AD10 E3 2 B_A21 R1 47 CLOCK E19 151
A_CD1 V11 82 AD11 C12 172 B_A22 R2 49 DATA F14 152
A_CD2 H17 140 AD12 A4 208 B_A23 R3 51 DEVSEL C7 197
A_CE1 P13 94 AD13 E6 206 B_A24 W4 53 FRAME F8 193
A_CE2 R13 97 AD14 B5 205 B_A25 R6 55 GND B10 181
A_D0 H14 141 AD15 F6 204 B_BVD1(STSCHG/R1) V9 72 GND C5 207
A_D1 G18 144 AD16 B8 191 B_BVD2(SPKR) W9 71 GND E8 194
A_D2 G14 146 AD17 A8 190 B_CD1 H3 16 GND E18 153
A_D3 U11 83 AD18 E9 189 B_CD2 R9 74 GND F12 167
A_D4 R11 85 AD19 F9 188 B_CE1 K6 28 GND G2 13
A_D5 U12 88 AD20 B9 186 B_CE2 L2 30 GND J5 22
A_D6 R12 90 AD21 A9 185 B_D0 W10 76 GND K18 129
A_D7 V13 92 AD22 F10 184 B_D1 U10 78 GND P2 44
A_D8 H15 142 AD23 E10 183 B_D2 P10 80 GND P9 75
A_D9 G17 145 AD24 F11 179 B_D3 H2 17 GND V14 96
A_D10 F19 147 AD25 E13 165 B_D4 J1 19 GNT C13 168

PIN NO.

GHK PDV

PIN NO.

GHK PDV

PIN NO.

GHK PDV

2–7

Table 2–4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

NAME

NAME

PIN NO.

GHK PDV

GRST A11 175 MFUNC5 F13 160 SPKROUT G15 149 V
IDSEL C10 182 MFUNC6 B15 161 STOP F7 198 V
IRDY A7 195 PAR C6 202 SUSPEND D19 156 V
LATCH F17 150 PCLK A10 180 TRDY B7 196 V
MFUNC0 F15 154 PERR A6 199 V
MFUNC1 E17 155 PRST A14 166 V
MFUNC2 A16 157 REQ B13 169 V
MFUNC3 C15 158 RI_OUT/PME C14 163 V
MFUNC4 E14 159 SERR B6 200 V

PIN NO.

GHK PDV

CC
CC
CC
CC
CC

PIN NO.

GHK PDV

B14 164 V

C9 187 V
E7 201 V

F3 7 V

G19 143 V

CC
CC
CC
CC
CCA
CCB
CCI
CCP
CCP

PIN NO.

GHK PDV

L3 31

N15 113

U7 64
W12 86
M17 120

M5 38

F18 148

D1 1

E11 178

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.

Table 2–5. Power Supply

TERMINAL

DESCRIPTION

GND

V

V

CCA

V

CCB

V

CCI

V

CCP

CC

NO.

PDV GHK

13, 22, 44, 75,

96, 129, 153,

167, 181, 194,

207

7, 31, 64, 86,

113, 143, 164,

187, 201

B10, C5, E8,

E18, F12, G2,

J5, K18, P2,

P9, V14

B14, C9, E7,
F3, G19, L3,

N15, U7, W12

Device ground terminals

Power supply terminal for core logic (3.3 V)

120 M17 Clamp voltage for PC Card A interface. Matches Card A signaling environment, 5 V or 3.3 V.

38 M5 Clamp voltage for PC Card B interface. Matches Card B signaling environment, 5 V or 3.3 V.

148 F18 Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V or 3.3 V

1, 178 D1, E11 Clamp voltage for PCI signaling, 5 V or 3.3 V

TERMINAL

NO.

I/O DESCRIPTION

PDV GHK

CLOCK 151 E19 I/O

DATA 152 F14 O

LATCH 150 F17 O

Table 2–6. PC Card Power Switch

Power switch clock. Information on the DAT A line is sampled at the rising edge of CLOCK. CLOCK defaults
to an input, but can be changed to a PCI1420 output by using bit 27 (P2CCLK) in the system control register
(see Section 4.29). The TPS2206 defines the maximum frequency of this signal to be 2 MHz.
If a system design defines this terminal as an output, then this terminal requires an external pulldown
resistor. The frequency of the PCI1420 output CLOCK is derived from dividing the PCI CLK by 36.

Power switch data. DATA is used to serially communicate socket power control information to the power
switch.

Power switch latch. LATCH is asserted by the PCI1420 to indicate to the power switch that the data on the
DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4
terminals provide the serial EEPROM SDA and SCL interface.

2–8

TERMINAL

NAME

NO.

PDV GHK

GRST 175 A11 I

PCLK 180 A10 I

PRST

166 A14 I

Table 2–7. PCI System

I/O DESCRIPTION

Global reset. When the global reset is asserted, the GRST signal causes the PCI1420 to place all output
buffers in a high-impedance state and reset all internal registers. When GRST
completely in its default state. For systems that require wake-up from D3, GRST
only during initial boot. PRST
transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST

When the SUSPEND
preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the
rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1420 to place all output buffers in a
high-impedance state and reset internal registers. When PRST
nonfunctional. After PRST

When the SUSPEND
preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

should be asserted following initial boot so that PME context is retained when

mode is enabled, the device is protected from the GRST , and the internal registers are

is asserted, the device is completely

is deasserted, the PCI1420 is in a default state.

mode is enabled, the device is protected from the PRST , and the internal registers are

is asserted, the device is

will normally be asserted

should be tied to PRST .

2–9

TERMINAL

NAME

NO.

PDV GHK

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3
C/BE2
C/BE1
C/BE0

PAR 202 C6 I/O

170
171
173
174
176
177
165
179
183
184
185
186
188
189
190
191
204
205
206
208
172

2
3
4
6
8

9
10
11
12
14
15

162
192
203

5

A13
E12
B12
A12

B11
C11
E13

F11
E10

F10

A9
B9
F9
E9
A8
B8
F6
B5
E6
A4

C12

E3
F5
G6
E1
F2
G5
F1
H6
G3
G1
H5

A15

C8
A5
E2

Table 2–8. PCI Address and Data

I/O DESCRIPTION

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other

I/O

destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary bus PCI cycle, C/BE3
phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. C/BE0
C/BE2

applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PCI bus parity. In all PCI bus read and write cycles, the PCI1420 calculates even parity across the
AD31–AD0 and C/BE3
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the
initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

–C/BE0 buses. As an initiator during PCI cycles, the PCI1420 outputs this parity

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8),

–C/BE0 define the bus command. During the data

).

2–10

TERMINAL

NAME

NO.

PDV GHK

DEVSEL

FRAME

GNT

IDSEL 182 C10 I

IRDY

PERR

REQ

SERR

STOP

TRDY

197 C7 I/O

193 F8 I/O

168 C13 I

195 A7 I/O

199 A6 I/O
169 B13 O PCI bus request. REQ is asserted by the PCI1420 to request access to the PCI bus as an initiator.

200 B6 O

198 F7 I/O

196 B7 I/O

Table 2–9. PCI Interface Control

I/O DESCRIPTION

PCI device select. The PCI1420 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator
on the bus, the PCI1420 monitors DEVSEL
occurs, then the PCI1420 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1420 access to the PCI bus after the
current data transaction has completed. GNT
bus parking algorithm.

Initialization device select. IDSEL selects the PCI1420 during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY
Until IRDY

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match
PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1420 when enabled through bit 8 of the
command register (see Section 4.4) indicating a system error has occurred. The PCI1420 need not be the
target of the PCI cycle to assert this signal. When SERR
pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP
support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK when both IRDY
Until both IRDY

and TRDY are both sampled asserted, wait states are inserted.

is enabled through bit 6 of the command register (see Section 4.4).

is used for target disconnects and is commonly asserted by target devices that do not

and TRDY are asserted, wait states are inserted.

until a target responds. If no target responds before timeout

may or may not follow a PCI bus request, depending on the PCI

and TRDY are asserted.

is enabled in the command register, this signal also

and TRDY are asserted.

is

2–11

TERMINAL

NAME

NO.

PDV GHK

MFUNC0 154 F15 I/O

MFUNC1 155 E17 I/O

MFUNC2 157 A16 I/O

MFUNC3 158 C15 I/O

MFUNC4 159 E14 I/O

MFUNC5 160 F13 I/O

MFUNC6 161 B15 I/O

RI_OUT/PME 163 C14 O

SPKROUT

SUSPEND 156 D19 I

149 G15 O

Table 2–10. Multifunction and Miscellaneous Pins

I/O DESCRIPTION

Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INT A, GPI0, GPO0, socket
activity LED output, ZV switching outputs, CardBus audio PWM, GPE
Section 4.30,

Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket
activity LED output, ZV switching outputs, CardBus audio PWM, GPE
Section 4.30,

Serial data (SDA). When LATCH is detected low after a PCI reset, the MFUNC1 terminal provides the
SDA signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification
and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1,

Implementation

Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket
activity LED output, ZV switching outputs, CardBus audio PWM, GPE
Section 4.30,

Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal
IRQSER. See Section 4.30,

Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED
output, ZV switching outputs, CardBus audio PWM, GPE

Multifunction Routing Register

Serial clock (SCL). When LATCH is detected low after a PCI reset, the MFUNC4 terminal provides the
SCL signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification
and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1,

Implementation

Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4, socket activity
LED output, ZV switching outputs, CardBus audio PWM, GPE

Multifunction Routing Register

Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See
Section 4.30,

Ring indicate out and power management event output. T erminal provides an output for ring-indicate or
PME

signals.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through
the PCI1420 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card
SPKR

Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST signal is
asserted. See Section 3.8.4,

Multifunction Routing Register

Multifunction Routing Register

, for details on other serial bus applications.

Multifunction Routing Register

, for details on other serial bus applications.

Multifunction Routing Register

//CAUDIO inputs.

, for configuration details.

, for configuration details.

, for configuration details.

Multifunction Routing Register

, for configuration details.

, for configuration details.

, for configuration details.

Suspend Mode

, for details.

, RI_OUT , or a parallel IRQ. See Section 4.30,

, for configuration details.

, or a parallel IRQ. See Section 4.30,

, or a parallel IRQ. See

, or a parallel IRQ. See

Serial Bus Interface

, RI_OUT, or a parallel IRQ. See

Serial Bus Interface

2–12

Table 2–11. 16-Bit PC Card Address and Data (Slots A and B)

I/O

DESCRIPTION

TERMINAL

NUMBER

NAME

PDV

A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

D15
D14
D13
D12

D11

D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 121 and M18 are A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R6 are B_A25.

121
118
116
114
111
109
107
105
103
112
115
108
106
117
100

95
102
104
119
123
125
126
128
131
132
133

93

91

89

87

84
147
145
142

92

90

88

85

83
146
144
141

SLOT A

†

GHK

M18

N19
N17
P19
P17
R18
P15
T19
U15
P18

M14

N14
R17
N18
P14

W14

R14
W16
M15

L19

L17

L15

K19

K15

K14

J19

U13
W13

P12

V12

P11

F19

G17
H15
V13
R12
U12
R11
U11
G14
G18
H14

PDV

55
53
51
49
47
45
42
40
37
48
50
43
41
52
34
29
36
39
54
57
59
60
62
65
66
67

27
25
23
20
18
81
79
77
26
24
21
19
17
80
78
76

SLOT B

‡

GHK

R6

W4

R3
R2
R1
N5
N6
N2

M6

P6
P5
P1
N3
T1

M1

L1

M3

N1
U5
V5
U6
V6

W6

V7

W7

R8
K5

K2

J6
J2

H1
W11
R10

V10

K3

K1

J3
J1

H2

P10

U10

W10

O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.

2–13

Table 2–12. 16-Bit PC Card Interface Control (Slots A and B)

I/O

DESCRIPTION

TERMINAL

NUMBER

NAME

PDV GHK PDV GHK

BVD1

(STSCHG

BVD2

(SPKR

CD1
CD2

CE1
CE2

INPACK 127 L14 61 R7 I

IORD

IOWR

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 are A_INPACK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 are B_INPACK

138 H19 72 V9 I

/RI)

137 J15 71 W9 I

)

82

140

9497P13

99 W15 33 L5 O

101 V15 35 M2 O

SLOT A

†

V11

H171674

R132830

SLOT B

‡

H3
R9

K6
L2

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that
include batteries. BVD1 is used with BVD2 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and should be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See Section 5.6,

Configuration Register
Status-Change Register

status bits for this signal.
Status change. STSCHG is used to alert the system to a change in the READY,

write protect, or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI

Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that
include batteries. BVD2 is used with BVD1 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and should be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See Section 5.6,

Configuration Register
Status-Change Register

status bits for this signal.
Speaker. SPKR is an optional binary audio signal available only when the card and

socket have been configured for the 16-bit I/O interface. The audio signals from
cards A and B are combined by the PCI1420 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA
operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to
indicate a request for a DMA operation.

Card detect 1 and Card detect 2. CD1 and CD2 are internally connected to ground
on the PC Card. When a PC Card is inserted into a socket, CD1

I

low. For signal status, see
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1

O

odd-numbered address bytes.
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an

I/O read cycle at the current address.
DMA request. INPACK can be used as the DMA request signal during DMA

operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then
the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1420 to enable 16-bit I/O PC Card data output
during host I/O read cycles.

DMA write. IORD is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The PCI1420 asserts IORD
transfers from the PC Card to host memory.

I/O write. IOWR is driven low by the PCI1420 to strobe write data into 16-bit I/O PC
Cards during host I/O write cycles.

DMA read. IOWR is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The PCI1420 asserts IOWR
from host memory to the PC Card.

, for enable bits. See Section 5.5,
, and Section 5.2,

is used by 16-bit modem cards to indicate a ring detection.

, for enable bits. See Section 5.5,
, and Section 5.2,

Section 5.2,

enables even-numbered address bytes, and CE2 enables

ExCA Card Status-Change-Interrupt

ExCA Interface Status Register

ExCA Card Status-Change-Interrupt

ExCA Interface Status Register

ExCA Interface Status Register

ExCA Card

, for the

ExCA Card

, for the

and CD2 are pulled

.

during DMA

during transfers

.

2–14

Table 2–12. 16-Bit PC Card Interface Control (Slots A and B) (Continued)

I/O

DESCRIPTION

TERMINAL

NUMBER

NAME

PDV GHK PDV GHK

OE 98 U14 32 L6 O

READY

(IREQ

REG

RESET 124 L18 58 W5 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE 110 R19 46 P3 O

WP

(IOIS16

VS1
VS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19 are A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3 are B_WE

135 J17 69 V8 I

)

130 K17 63 P8 O

136 J14 70 W8 I

139 H18 73 U9 I

)

134
122

†

SLOT A

J18

M196856U8P7

SLOT B

‡

Output enable. OE is driven low by the PCI1420 to enable 16-bit memory PC Card data
output during host memory read cycles.

DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit
PC Card that supports DMA. The PCI1420 asserts OE
operation.

Ready. The ready function is provided by READY when the 16-bit PC Card and the host
socket are configured for the memory-only interface. READY is driven low by the 16-bit
memory PC Cards to indicate that the memory card circuits are busy processing a previous
write command. READY is driven high when the 16-bit memory PC Card is ready to accept
a new data transfer command.

Interrupt request. IREQ
device on the 16-bit I /O PC Card requires service by the host software. IREQ
(deasserted) when no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG
is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space
(IORD

or IOWR active). Attribute memory is a separately accessed section of card memory
and is generally used to record card capacity and other configuration and attribute
information.

DMA acknowledge. REG
to a 16-bit PC Card that supports DMA. The PCI1420 asserts REG
operation. REG
strobes to transfer data.

Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory
or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE
is also used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE
supports DMA. The PCI1420 asserts WE

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the
write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the
16-bit port (IOIS16

I/O is 16 bits. IOIS16
when the address on the bus corresponds to an address to which the 16-bit PC Card
responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for
a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each

I/O

other, determine the operating voltage of the PC Card.

is asserted by a 16-bit I/O PC Card to indicate to the host that a

is used as a DMA acknowledge (DACK) during DMA operations

is used in conjunction with the DMA read (IOWR) or DMA write (IORD)

is used as TC during DMA operations to a 16-bit PC Card that

to indicate TC for a DMA read operation.

) function.

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card

to indicate TC for a DMA write

is high

to indicate a DMA

.

2–15

Table 2–13. CardBus PC Card Interface System (Slots A and B)

I/O

DESCRIPTION

TERMINAL

NUMBER

NAME

PDV GHK PDV GHK

CCLK 112 P18 48 P6 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 are A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 are B_CCLK.

139 H18 73 U9 O

124 L18 58 W5 I/O

SLOT A

†

SLOT B

‡

CardBus clock. CCLK provides synchronous timing for all transactions on the
CardBus interface. All signals except CRST
CCD2

, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all
timing parameters are defined with the rising edge of this signal. CCLK operates at
the PCI bus clock frequency, but it can be stopped in the low state or slowed down
for power savings.

CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase
in the CCLK frequency, and by the PCI1420 to indicate that the CCLK frequency is
going to be decreased.

CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and
signals to a known state. When CRST
placed in a high-impedance state, and the PCI1420 drives these signals to a valid
logic level. Assertion can be asynchronous to CCLK, but deassertion must be
synchronous to CCLK.

, CCLKRUN, CINT , CSTSCHG, CAUDIO,

is asserted, all CardBus PC Card signals are

2–16

Table 2–14. CardBus PC Card Address and Data (Slots A and B)

I/O

DESCRIPTION

TERMINAL

NUMBER

NAME

PDV GHK PDV GHK

CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12

CAD11

CAD10

CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0

CC/BE3
CC/BE2
CC/BE1
CC/BE0

CPAR 106 R17 41 N3 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 are A_CPAR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 are B_CPAR.

147
145
144
142
141
133
132
131
128
126
125
123
121
119
118
103
101
102

99

100

98
97
95
93
92
89
90
87
88
84
85
83

130
117
104

94

SLOT A

†

F19
G17
G18
H15
H14

J19
K14
K15
K19

L15

L17

L19
M18
M15
N19
U15
V15
R14

W15

P14
U14
R13

W14

U13
V13
P12
R12
V12
U12
P11
R11
U11

K17
N18

W16

P13

81
79
78
77
76
67
66
65
62
60
59
57
55
54
53
37
35
36
33
34
32
30
29
27
26
23
24
20
21
18
19
17

63
52
39
28

SLOT B

‡

W11
R10
U10
V10

W10

R8
W7
V7
W6
V6
U6
V5
R6
U5
W4
M6
M2
M3

L5

M1

L6
L2

L1
K5
K3

J6
K1

J2

J3
H1

J1
H2

P8

T1
N1
K6

CardBus address and data. These signals make up the multiplexed CardBus address
and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31–CAD0 contain data. CAD31 is the most significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of a CardBus cycle,
CC/BE3

–CC/BE0 define the bus command. During the data phase, this 4-bit bus is used

as byte enables. The byte enables determine which byte paths of the full 32-bit data bus

I/O

carry meaningful data. CC/BE0
byte 1 (CAD15–CAD8), CC/BE2
to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1420 calculates even parity
across the CAD and CC/BE
outputs CP AR with a one-CCLK delay. As a target during CardBus cycles, the calculated
parity is compared to the initiator’s parity indicator; a compare error results in a parity
error assertion.

applies to byte 0 (CAD7–CAD0), CC/BE1 applies to
applies to byte 2 (CAD23–CAD8), and CC/BE3 applies

buses. As an initiator during CardBus cycles, the PCI1420

2–17

Table 2–15. CardBus PC Card Interface Control (Slots A and B)

I/O

DESCRIPTION

I

ith CVS1

CVS2 to identif

I/O

i

ith CCD1

CCD2 to identif

TERMINAL

NUMBER

NAME

PDV GHK PDV GHK

CAUDIO 137 J15 71 W9 I

CBLOCK

CCD1
CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 134 J18 68 U8
CVS2 122 M19 56 P7

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 137 and J15 are A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 71 and W9 are B_CAUDIO.

107 P15 42 N6 I/O

82 V11 16 H3

140 H17 74 R9

111 P17 47 R1 I/O

116 N17 51 R3 I/O

110 R19 46 P3 I

135 J17 69 V8 I

115 M14 50 P5 I/O

108 N14 43 P1 I/O

127 L14 61 R7 I

136 J14 70 W8 I

109 R18 45 N5 I/O

138 H19 72 V9 I

114 P19 49 R2 I/O

SLOT A

†

SLOT B

‡

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system
speaker. The PCI1420 supports the binary audio mode and outputs a binary signal
from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

w
operating voltage and card type.

CardBus device select. The PCI1420 asserts CDEVSEL to claim a CardBus cycle as
the target device. As a CardBus initiator on the bus, the PCI1420 monitors CDEVSEL
until a target responds. If no target responds before timeout occurs, then the PCI1420
terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle.
CFRAME
transfers continue while this signal is asserted. When CFRAME
CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI1420 to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt
servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete
the current data phase of the transaction. A data phase is completed on a rising edge
of CCLK when both CIRDY
both sampled asserted, wait states are inserted.

CardBus parity error. CPERR reports parity errors during CardBus transactions,
except during special cycles. It is driven low by a target two clocks following that data
when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires
use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors
that could lead to catastrophic results. CSERR
CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The
PCI1420 can report CSERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop
the current CardBus transaction. CSTOP
commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG alerts the system to a change in the card’s
status, and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’ s ability to complete the
current data phase of the transaction. A data phase is completed on a rising edge of
CCLK, when both CIRDY
inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

n conjunction w

to determine the operating voltage and card type.

and

is asserted to indicate that a bus transaction is beginning, and data

y card insertion and interrogate cards to determine the

and CTRDY are asserted. Until CIRDY and CTRDY are

is driven by the card synchronous to

to the system by assertion of SERR on the PCI interface.

is used for target disconnects, and is

and CTRDY are asserted; until this time, wait states are

and

y card insertion and interrogate cards

is deasserted, the

2–18