TEXAS INSTRUMENTS PCI1251A Technical data
查询PCI1251A GFN/GJG供应商
D
(PCI) Power Management 1.0 Compliant
D
ACPI 1.0 Compliant
D
Packaged in GFN 256-Pin BGA or GJG
MicroStar BGA
D
PCI Local Bus Specification Revision 2.2
Compliant
D
1997 PC Card Standard Compliant
D
PC 99 Compliant
D
3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments
D
Mix-and-Match 5-V/3.3-V PC Card16 Cards
and 3.3-V CardBus Cards
D
Supports Two PC Card or CardBus Slots
With Hot Insertion and Removal
D
Uses Serial Interface to TI TPS2206 Dual
Power Switch
D
Supports Burst Transfers to Maximize Data
Throughput on the PCI Bus and the
CardBus Bus
D
Supports Serialized Interrupt request (IRQ)
With PCI Interrupts
D
8-Way Legacy IRQ Multiplexing
D
System Interrupts Can Be Programmed as
PCI Style or Industry Standard Architecture
(ISA-IRQ) Style
D
ISA-IRQ Interrupts Can Be Serialized Onto
a Single IRQ Serial (IRQSER) Pin
D
EEPROM Interface for Loading Subsystem
ID and Subsystem Vendor ID
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
D
Pipelined Architecture Allows Greater Than
130M-Bytes-Per-Second Throughput From
CardBus to PCI and From PCI to CardBus
D
Supports Zoom Video With Internal
Buffering
D
Four General Purpose I/Os
D
Multifunction PCI Device With Separate
Configuration Space for Each Socket
D
Five PCI Memory Windows and Two I/O
Windows Available for Each PC Card16
Socket
D
Two I/O Windows and Two Memory
Windows Available to Each CardBus
Socket
D
Exchangeable Card Architecture (ExCA)
Compatible Registers Are Mappable in
Memory and I/O Space
D
Supports Distributed DMA (DDMA) and
PC/PCI DMA
D
Intel 82365SL-DF Register Compatible
D
Supports 16-Bit DMA on Both PC Card
Sockets
D
Supports Ring Indicate, SUSPEND, PCI
CLKRUN,
D
Advanced Submicron, Low-Power CMOS
T echnology
D
Provides VGA/Palette Memory and I/O and
Subtractive Decoding Options
D
LED Activity Pins
D
Supports PCI Bus Lock (LOCK)
and CardBus CCLKRUN
Table of Contents
Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Name/Terminal Number Sort Tables 4. . . . . . . . . . . . . . . . .
Terminal Functions 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Sequencing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamping Rail Voltages 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interface 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Applications 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Interrupt Subsystem 32. . . . . . . . . . . . . . . . . . . . . .
Power Management Overview 36. . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Controller Programming Model 39. . . . . . . . . . . . . . . . . .
PCI Configuration Registers (Functions 0 and 1) 39. . . . . . . . . . .
ExCA Compatibility Registers (Functions 0 and 1) 75. . . . . . . . .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA).
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
CardBus Socket Registers (Functions 0 and 1) 98. . . . . . . . . . . . . . .
Distributed DMA (DDMA) Registers 106. . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 112. . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock/Reset Timing Requirements 114. . . . . . . . . . . . . . . . . . . . .
PCI Timing Requirements 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information 115. . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Parameter Measurement Information 116. . . . . . . . . . . . . . .
PC Card Cycle Timing 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Requirements, (Memory Cycles) 118. . . . . . . . . . . . . . . . . . . .
Timing Requirements, (I/O Cycles) 118. . . . . . . . . . . . . . . . . . . . . . . . .
Switching Characteristics (Miscellaneous) 119. . . . . . . . . . . . . . . . . .
PC Card Parameter Mesasurement Information 120. . . . . . . . . . . . . .
Mechanical Data 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
description
The TI PCI1251A is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two
independent PC Card sockets compliant with the 1997 PC Card Standard. The PCI1251A provides a rich
feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop
computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA
Release 2.2, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The
PCI1251A supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or
3.3 V, as required.
The PCI1251A is compliant with the latest
the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI master device or a PCI slave
device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or
CardBus PC Card bridging transactions.
Multiple system-interrupt signaling options are provided and they include:
D
Parallel PCI interrupts
D
Parallel ISA interrupts
D
Serialized ISA interrupts
D
Serialized ISA and PCI interrupts
Additionally, general-purpose inputs and outputs are provided for the board designer to implement sideband
functions.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The
PCI1251A is register compatible with the Intel 82365SL-DF ExCA controller . The PCI1251A internal data path
logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.
Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained
bursting. The PCI1251A can also be programmed to accept fast posted writes to improve system-bus utilization.
The PCI1251A provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC board
manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading
specifications. Many other features, such as socket activity light-emitting diode (LED) outputs, are designed into
the PCI1251A. These features are discussed in detail throughout the design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low
system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable
the host power management system to further reduce power consumption.
PCI Bus Power Management Specification
. It is also compliant with
Unused PCI1251A inputs must be pulled up using a 43 kW resistor.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
system block diagram
A simplified system block diagram using the PCI1251A is provided below. The zoomed video (ZV) capability
can be used to route the ZV data directly to the VGA controller.
The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface
includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV)
is enabled (in 16-bit PC Card mode), 23 of the 68 signals are redefined to support the ZV protocol.
The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
The ring indicate terminal is included in the interrupt interface because its function is to perform system wake
up on incoming PC Card modem rings. Other miscellaneous system interface terminals available on the
PCI1251A include:
D
Programmable general purpose multifunction terminals
D
SUSPEND, RI_OUT/PME (power management control signal)
D
SPKROUT
PCI Bus
Activity LED’s
CLKRUN
TPS2206
Power
Switch
PC Card
Socket A
PC Card
Socket B
NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video
mode, 23 pins are used for routing the zoomed video signals to the VGA controller.
3
23 for ZV
(See Note)
23 for ZV
68
68
PCI1251A
Enable
ZV
IRQSER
†
DMA
PME
Zoom Video
South Bridge
19 Video
4 Audio
†
Interrupt Routing Options:
1) Serialized, including PCI and ISA
2) Serialized ISA and parallel PCI
3) Parallel PCI and parallel ISA
4) Parallel PCI interrupts only
Embedded
Controller
VGA
Controller
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
signal names and terminal assignments
Signal names and their terminal assignments are shown in Tables 1 through 4 sorted alpha-numerically by the
assigned terminal.
Table 1. GFN Terminals Sorted Alpha-Numerically for CardBus and 16-Bit Signals
GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
C3
C4
C5
C6
C7
C8
GND
ZV_UV3
ZV_Y7
V
CCZ
ZV_Y1
ZV_HREF
B_RSVD//B_D2
B_CAD28//B_D8
B_CSTSCHG//B_BVD1(STSCHG
B_CINT
//B_READY(IREQ)
B_CVS1//B_VS1
B_CAD24//B_A2
B_CAD22//B_A4
B_CAD20//B_A6
B_CAD18//B_A7
B_CIRDY
B_CCLK//B_A16
B_CDEVSEL
B_CPAR//B_A13
B_RSVD//B_A18
ZV_UV5
ZV_UV4
ZV_UV1
ZV_Y6
ZV_Y4
ZV_Y0
B_CAD31//B_D10
B_CAD29//B_D1
B_CCLKRUN
B_CSERR
B_CAD25//B_A1
B_CC/BE3
B_CAD21//B_A5
B_CVS2//B_VS2
B_CAD17//B_A24
V
B_CPERR
B_CBLOCK
B_CC/BE1
B_CAD14//B_A9
ZV_RSVD1
ZV_SCLK
ZV_UV6
ZV_UV2
ZV_Y5
ZV_Y3
ZV_VSYNC
B_CAD30//B_D9
//B_A15
//B_A21
//B_WP(IOIS16)
//B_WAIT
//B_REG
CCB
//B_A14
//B_A19
//B_A8
/RI)
C9
B_CCD2//B_CD2
C10
V
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
E2
E3
E4
E17
E18
E19
E20
F4
F17
F18
F19
F20
G1
G2
G3
CCB
B_CAD26//B_A0
B_CAD23//B_A3
B_CRST
B_CAD19//B_A25
B_CFRAME
B_CTRDY
B_CSTOP
B_CAD16//B_A17
B_CAD15//B_IOWR
B_CAD11//B_OE
V
ZV_UV7
ZV_MCLK
GND
ZV_UV0
V
ZV_Y2
GND
B_CAD27//B_D0
B_CAUDIO//B_BVD2(SPKR
V
B_CREQ
GND
B_CC/BE2
V
B_CGNT
GND
B_CAD12//B_A11
B_CAD10//B_CE2
B_CC/BE0//B_CE1
ZV_PCLK
ZV_SDATA
ZV_LRCLK
ZV_RSVD0
B_CAD13//B_IORD
B_CAD9//B_A10
B_CAD8//B_D15
B_RSVD//B_D14
V
V
V
B_CAD5//B_D6
B_CAD3//B_D5
A_CAD2//A_D1 1
A_CAD0//A_D3
A_CCD1
//B_RESET
CCZ
CC
CC
CC
CC
CC
CCB
//A_CD1
//B_A23
//B_A22
//B_A20
//B_INPACK
//B_A12
//B_WE
G17
B_CAD7//B_D7
G18
B_CAD6//B_D13
G19
B_CAD4//B_D12
G20
B_CAD1//B_D4
H1
A_CAD3//A_D5
H2
A_CAD4//A_D12
H3
A_CAD1//A_D4
H4
GND
H17
GND
H18
B_CAD2//B_D1 1
H19
B_CAD0//B_D3
H20
B_CCD1
J1
A_CAD7//A_D7
J2
A_RSVD//A_D14
J3
A_CAD5//A_D6
J4
A_CAD6//A_D13
J17
PCLK
J18
CLKRUN
J19
PRST
J20
GNT
K1
A_CC/BE0//A_CE1
K2
)
V
K3
A_CAD8//A_D15
K4
V
K17
REQ
K18
AD31
K19
AD30
K20
V
L1
A_CAD9//A_A10
L2
A_CAD10//A_CE2
L3
A_CAD11//A_OE
L4
A_CAD13//A_IORD
L17
V
L18
AD28
L19
AD27
L20
AD29
M1
A_CAD12//A_A11
M2
A_CAD15//A_IOWR
M3
A_CAD14//A_A9
M4
A_CAD16//A_A17
M17
C/BE3
M18
AD24
M19
AD25
M20
AD26
N1
A_CC/BE1
N2
A_RSVD//A_A18
N3
A_CPAR//A_A13
//B_CD1
CCA
CC
CCP
CC
//A_A8
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
signal names and terminal assignments (continued)
Table 1. GFN Terminals Sorted Alpha-Numerically for CardBus and 16-Bit Signals (Continued)
GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME
N4
N17
N18
N19
N20
P1
P2
P3
P4
P17
P18
P19
P20
R1
R2
R3
R4
R17
R18
R19
R20
T1
T2
T3
T4
T17
T18
T19
T20
U1
U2
U3
U4
U5
U6
U7
U8
GND
GND
AD22
AD23
IDSEL
A_CBLOCK
A_CPERR
A_CGNT
A_CTRDY//A_A22
AD17
V
CCP
AD20
AD21
A_CSTOP
A_CDEVSEL
V
CCA
V
CC
V
CC
AD16
AD18
AD19
A_CCLK//A_A16
A_CIRDY
A_CC/BE2
A_CAD19//A_A25
STOP
IRDY
FRAME
C/BE2
A_CFRAME//A_23
A_CAD17//A_A24
A_CVS2//A_VS2
GND
A_CAD26//A_A0
V
CC
A_CCLKRUN
GND
//A_A19
//A_A14
//A_WE
//A_A20
//A_A21
//A_A15
//A_A12
//A_WP(IOIS16)
U9
IRQMUX1
U10
V
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W1
W2
W3
W4
W5
CC
PCGNT
/IRQMUX6
CLOCK
GND
AD6
V
CC
AD11
GND
PERR
SERR
TRDY
A_CAD18//A_A7
A_CAD20//A_A6
A_CAD21//A_A5
A_CAD25//A_A1
A_CSERR
A_CSTSCHG//A_BVD1(STSCHG/RI)
A_CAD28//A_D8
A_RSVD//A_D2
IRQMUX2
V
CCI
GPIO0/LEDA1
DATA
GPIO3/INTA
AD3
V
CCP
AD8
AD12
AD15
GPIO2/LOCK
DEVSEL
A_CRST//A_RESET
A_CAD22//A_A4
A_CAD23//A_A3
A_CAD24//A_A2
V
CCA
//A_WAIT
W6
A_CCD2//A_CD2
W7
A_CAD29//A_D1
W8
A_CAD31//A_D10
W9
IRQMUX3
W10
IRQMUX5
W11
GPIO1/LEDA2
W12
LATCH
W13
IRQSER/INTB
W14
AD1
W15
AD4
W16
AD7
W17
AD9
W18
AD13
W19
C/BE1
W20
V
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
CCP
A_CREQ
A_CC/BE3//A_REG
A_CVS1//A_VS1
A_CINT//A_READY(IREQ)
A_CAUDIO//A_BVD2(SPKR
A_CAD27//A_D0
A_CAD30//A_D9
IRQMUX0
IRQMUX4
SPKROUT
SUSPEND
PCREQ/IRQMUX7
RI_OUT
/PME
AD0
AD2
AD5
C/BE0
AD10
AD14
PAR
//A_INPACK
)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
signal names and terminal assignments (continued)
Table 2. GJG Terminals Sorted Alpha-Numerically for CardBus and 16-bit Signals
NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
C2
C18
C19
D1
D2
D4
D5
D6
D7
D8
D9
D10
D11
ZV_UV6
ZV_UV4
ZV_UV2
ZV_Y6
ZV_Y3
ZV_VSYNC
V
CC
B_CCLKRUN
B_CSERR
B_CAD24//B_A2
B_CAD21//B_A5
B_CAD20//B_A6
B_CAD17//B_A24
V
CCB
B_CGNT
B_CPERR//B_A14
B_CBLOCK
ZV_SCLK
ZV_UV5
ZV_UV3
ZV_UV1
ZV_Y7
ZV_Y4
ZV_Y0
B_CAD30//B_D9
B_CCD2
V
CCB
B_CAD25//B_A1
B_CAD22//B_A4
B_CVS2//B_VS2
GND
B_CIRDY
B_CDEVSEL
B_CSTOP
B_CPAR//B_A13
B_RSVD//B_A18
ZV_UV7
ZV_MCLK
B_CC/BE1
B_CAD14//B_A9
ZV_RSVD0
ZV_RSVD1
GND
ZV_UV0
V
CCZ
GND
B_RSVD//B_D2
B_CAD27//B_D0
B_CAUDIO//B_BVD2(SPKR
B_CC/BE3
//B_WP(IOIS16)
//B_WAIT
//B_WE
//B_A19
//B_CD2
//B_A15
//B_A21
//B_A20
//B_A8
//B_REG
D12
B_CREQ//B_INPACK
D13
B_CRST//B_RESET
D14
B_CC/BE2
D15
B_CCLK//B_A16
D16
B_CAD16//B_A17
D18
B_CAD15//B_IOWR
D19
B_CAD12//B_A11
E1
ZV_SDATA
E2
ZV_PCLK
E4
V
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E18
E19
F1
F2
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F18
F19
G1
G2
G4
G5
G6
G7
G13
)
G14
G15
CCZ
ZV_LRCLK
ZV_Y5
ZV_Y1
B_CAD31//B_D10
B_CAD28//B_D8
B_CSTSCHG//B_BVD1(STSCHG/RI
B_CAD26//B_A0
B_CAD23//B_A3
B_CAD19//B_A25
B_CFRAME
B_CTRDY
B_CAD13//B_IORD
B_CAD11//B_OE
B_CAD10//B_CE2
A_CCD1//A_CD1
A_CAD0//A_D3
NC
GND
V
CC
ZV_Y2
B_CAD29//B_D1
GND
B_CINT
B_CVS1//B_VS1
V
CC
B_CAD18//B_A7
VCC
B_CAD9//B_A10
B_CC/BE0
B_CAD8//B_D15
V
CCB
A_CAD4//A_D12
V
CC
A_CAD3//A_D5
A_CAD1//A_D4
A_CAD2//A_D1 1
ZV_HREF
B_CAD3//B_D5
B_CAD7//B_D7
B_RSVD//B_D14
//B_A12
//B_A23
//B_A22
//B_READY(IREQ)
//B_CE1
G16
GND
G18
B_CAD5//B_D6
G19
B_CAD6//B_D13
H1
A_CAD5//A_D6
H2
A_RSVD//A_D14
H4
A_CAD7//A_D7
H5
GND
H6
A_CAD6//A_D13
H14
B_CCD1
H15
B_CAD4//B_D12
H16
B_CAD1//B_D4
H18
B_CAD2//B_D1 1
H19
B_CAD0//B_D3
J1
A_CAD8//A_D15
J2
A_CC/BE0
J4
V
J5
A_CAD9//A_A10
J6
V
J14
GNT
J15
PCLK
J16
CLKRUN
J18
PRST
J19
GND
K1
A_CAD11//A_OE
K2
A_CAD13//A_IORD
K4
A_CAD12//A_A11
K5
GND
K6
A_CAD10//A_CE2
K14
V
K15
REQ
K16
AD31
K18
AD30
K19
V
L1
A_CAD14//A_A9
L2
A_CAD16//A_A17
L4
A_CC/BE1
L5
A_RSVD//A_A18
L6
A_CAD15//A_IOWR
L14
AD29
L15
AD28
L16
AD25
L18
AD27
L19
AD26
M1
A_CPAR//A_A13
M2
A_CBLOCK
M4
A_CPERR
M5
A_CSTOP
M6
V
M14
AD22
M15
AD24
//B_CD1
//A_CE1
CCA
CC
CCP
CC
//A_A8
//A_A19
//A_A14
//A_A20
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
signal names and terminal assignments (continued)
Table 2. GFN Terminals Sorted Alpha-Numerically for CardBus and 16-bit Signals. (Continued)
NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME
M16
M18
M19
N1
N2
N4
N5
N6
N7
N13
N14
N15
N16
N18
N19
P1
P2
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P18
P19
R1
R2
R4
R5
CBE3
IDSEL
AD23
A_CDEVSEL
GND
A_CCLK//A_A16
A_CTRDY
V
CCA
A_CGNT
AD1
GND
AD19
AD21
V
CCP
AD20
A_CIRDY
A_CFRAME
A_CC/BE2
V
CC
A_CAD17//A_A24
A_CAD27//A_D0
V
CC
V
CCI
SPKROUT
PCREQ/IRQMUX7
RI_OUT
AD5
AD8
C/BE2
AD16
AD18
AD17
A_CAD18//A_A7
A_CAD19//A_A25
A_CVS2//A_VS2
A_CSERR//A_WAIT
//A_A21
//A_A22
//A_WE
//A_A15
//A_23
//A_A12
/PME
R6
A_CSTSCHG//A_BVD1(STSCHG/RI)
R7
A_CAD28//A_D8
R8
IRQMUX2
R9
IRQMUX5
R10
PCGNT
/IRQMUX6
R11
CLOCK
R12
AD0
R13
GND
R14
C/BE0
R15
V
R16
R18
R19
T1
T2
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T18
T19
U1
U2
U18
U19
V1
V2
CC
TRDY
FRAME
IRDY
A_CAD20//A_A6
A_CRST
A_CAD21//A_A5
A_CINT
A_CCLKRUN
A_RSVD//A_D2
IRQMUX1
IRQMUX3
GPIO0/LEDA1
DATA
GPI03/INTA
AD4
AD7
AD11
AD15
DEVSEL
STOP
GND
A_CAD22//A_A4
PERR
SERR
A_CREQ//A_INPACK
A_CAD23//A_A3
//A_RESET
//A_READY(IREQ)
//A_WP(IOIS16)
V3
A_CAD25//A_A1
V4
A_CVS1//A_VS1
V5
A_CAUDIO//A_BVD2(SPKR)
V6
GND
V7
A_CAD29//A_D1
V8
IRQMUX0
V9
GND
V10
GPI01/LEDA2
V11
LATCH
V12
V
V13
V14
V15
V16
V17
V18
V19
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
CC
AD3
V
CCP
AD10
AD13
C/BE1
V
CCP
GPI02/LOCK
A_CC/BE3//A_REG
A_CAD24//A_A2
A_CAD26//A_A0
V
CCA
A_CCD2
A_CAD30//A_D9
A_CAD31//A_D10
IRQMUX4
SUSPEND
GND
IRQSER/INTB
AD2
AD6
AD9
AD12
AD14
PAR
//A_CD2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
signal names and terminal assignments (continued)
Table 3. CardBus Signal Names Sorted Alpha-Numerically for GFN and GJG Pins
SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG
A_CAD0
A_CAD1
A_CAD2
A_CAD3
A_CAD4
A_CAD5
A_CAD6
A_CAD7
A_CAD8
A_CAD9
A_CAD10
A_CAD11
A_CAD12
A_CAD13
A_CAD14
A_CAD15
A_CAD16
A_CAD17
A_CAD18
A_CAD19
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A_CAD28
A_CAD29
A_CAD30
A_CAD31
A_CAUDIO
A_CBLOCK
A_CC/BE0
A_CC/BE1
A_CC/BE2
A_CC/BE3
A_CCD1
A_CCD2
G2
H3
G1
H1
H2
J3
J4
J1
K3
L1
L2
L3
M1
L4
M3
M2
M4
U2
V1
T4
V2
V3
W2
W3
W4
V4
U5
Y6
V7
W7
Y7
W8
Y5
P1
K1
N1
T3
Y2
G3
W6
F2
G5
G6
G4
G1
H1
H6
H4
J1
J5
K6
K1
K4
K2
L1
L6
L2
P6
R1
R2
T1
T4
U2
V2
W3
V3
W4
P7
R7
V7
W7
W8
V5
M2
J2
L4
P4
W2
F1
W6
A_CCLK
A_CCLKRUN
A_CDEVSEL
A_FRAME
A_CGNT
A_CINT
A_CIRDY
A_CPAR
A_CPERR
A_CREQ
A_CRST
A_CSERR
A_CSTOP
A_CSTSCHG
A_CTRDY
A_CVS1
A_CVS2
A_RSVD
A_RSVD
A_RSVD
B_CAD00
B_CAD01
B_CAD02
B_CAD03
B_CAD04
B_CAD05
B_CAD06
B_CAD07
B_CAD08
B_CAD09
B_CAD10
B_CAD11
B_CAD12
B_CAD13
B_CAD14
B_CAD15
B_CAD16
B_CAD17
B_CAD18
B_CAD19
T1
U7
R2
U1
P3
Y4
T2
N3
P2
Y1
W1
V5
R1
V6
P4
Y3
U3
J2
N2
V8
H19
G20
H18
F20
G19
F19
G18
G17
E19
E18
D19
C20
D18
E17
B20
C19
C18
B15
A15
C14
N4
T6
N1
P2
N7
T5
P1
M1
M4
V1
T2
R5
M5
R6
N5
V4
R4
H2
L5
T7
H19
H16
H18
G13
H15
G18
G19
G14
F18
F15
E19
E18
D19
E16
C19
D18
D16
A14
F13
E13
B_CAD20
B_CAD21
B_CAD22
B_CAD23
B_CAD24
B_CAD25
B_CAD26
B_CAD27
B_CAD28
B_CAD29
B_CAD30
B_CAD31
B_CAUDIO
B_CBLOCK
B_CCBE0
B_CCBE1
B_CCBE2
B_CCBE3
B_CCD1
B_CCD2
B_CCLK
B_CCLKRUN
B_CDEVSEL
B_CFRAME
B_CGNT
B_CINT
B_CIRDY
B_CPAR
B_CPERR
B_CREQ
B_CRST
B_CSERR
B_CSTOP
B_CSTSCHG
B_CTRDY
B_CVS1
B_CVS2
B_RSVD
B_RSVD
B_RSVD
A14
B13
A13
C12
A12
B11
C11
D9
A8
B8
C8
B7
D10
B18
D20
B19
D14
B12
H20
C9
A17
B9
A18
C15
D16
A10
A16
A19
B17
D12
C13
B10
C17
A9
C16
A11
B14
A20
A7
E20
A13
A12
B12
E12
A11
B11
E11
D9
E9
F8
B8
E8
D10
A18
F16
C18
D14
D11
H14
B9
D15
A9
B16
E14
A16
F10
B15
B18
A17
D12
D13
A10
B17
E10
E15
F11
B13
B19
D8
G15
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
signal names and terminal assignments (continued)
Table 4. 16 Bit Signal Names Sorted Alpha-Numerically for GFN and GJG Pins
SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG
A_A00
A_A01
A_A02
A_A03
A_A04
A_A05
A_A06
A_A07
A_A08
A_A09
A_A10
A_A11
A_A12
A_A13
A_A14
A_A15
A_A16
A_A17
A_A18
A_A19
A_A20
A_A21
A_A22
A_A23
A_A24
A_A25
A_BVD1
A_BVD2
A_CD1
A_CD2
A_CE1
A_CE2
A_D00
A_D01
A_D02
A_D03
A_D04
A_D05
A_D06
A_D07
U5
V4
W4
W3
W2
V3
V2
V1
N1
M3
L1
M1
T3
N3
P2
T2
T1
M4
N2
P1
R1
R2
P4
U1
U2
T4
V6
Y5
G3
W6
K1
L2
Y6
W7
V8
G2
H3
H1
J3
J1
W4
V3
W3
V2
U2
T4
T1
R1
L4
L1
J5
K4
P4
M1
M4
P1
N4
L2
L5
M2
M5
N1
N5
P2
P6
R2
R6
V5
F1
W6
J2
K6
P7
V7
T7
F2
G5
G4
H1
H4
A_D08
A_D09
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A_INPACK
A_IORD
A_IOWR
A_OE
A_RDY
A_REG
A_RESET
A_VS1
A_VS2
A_WAIT
A_WE
A_WP
B_A00
B_A01
B_A02
B_A03
B_A04
B_A05
B_A06
B_A07
B_A08
B_A09
B_A10
B_A11
B_A12
B_A13
B_A14
B_A15
B_A16
B_A17
B_A18
B_A19
V7
Y7
W8
G1
H2
J4
J2
K3
Y1
L4
M2
L3
Y4
Y2
W1
Y3
U3
V5
P3
U7
C11
B11
A12
C12
A13
B13
A14
A15
B19
B20
E18
D18
D14
A19
B17
A16
A17
C18
A20
B18
R7
W7
W8
G6
G1
H6
H2
J1
V1
K2
L6
K1
T5
W2
T2
V4
R4
R5
N7
T6
E11
B11
A11
E12
B12
A12
A13
F13
C18
C19
F15
D19
D14
B18
A17
B15
D15
D16
B19
A18
B_A20
B_A21
B_A22
B_A23
B_A24
B_A25
B_BVD1
B_BVD2
B_CD1
B_CD2
B_CE1
B_CE2
B_D00
B_D01
B_D02
B_D03
B_D04
B_D05
B_D06
B_D07
B_D08
B_D09
B_D10
B_D11
B_D12
B_D13
B_D14
B_D15
B_INPACK
B_IORD
B_IOWR
B_OE
B_RDY
B_REG
B_RESET
B_VS1
B_VS2
B_WAIT
B_WE
B_WP
C17
A18
C16
C15
B15
C14
A9
D10
H20
C9
D20
D19
D9
B8
A7
H19
G20
F20
F19
G17
A8
C8
B7
H18
G19
G18
E20
E19
D12
E17
C19
C20
A10
B12
C13
A11
B14
B10
D16
B9
B17
B16
E15
E14
A14
E13
E10
D10
H14
B9
F16
E19
D9
F8
D8
H19
H16
G13
G18
G14
E9
B8
E8
H18
H15
G19
G15
F18
D12
E16
D18
E18
F10
D11
D13
F11
B13
A10
A16
A9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
PCI1251A GFN/GJG
FUNCTION
FUNCTION
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Terminal Functions
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 5. Power Supply
TERMINAL
NAME GFN NO. GJG NO.
B14, D4, D7, F5, F9, G16, H5,
J19, K5, N2, N14, R13, U1, V6,
V9, W11
A8, F6, F12, F14, G2, J6, K19,
M6, P5, P8, R15, V12
Device ground terminals
Power supply terminal for core logic (3.3 V)
Clamp voltage for PC Card A interface. Indicates Card A
signaling environment.
Clamp voltage for PC Card B interface. Indicates Card B
signaling environment.
Clamp voltage for interrupt subsystem interface and
miscellaneous I/O. Indicates signaling level of the following
inputs and shared outputs: IRQSER, PCGNT
SUSPEND
INTA
, SPKROUT, GPIO1:0, IRQMUX7–IRQMUX0,
, INTB, CLOCK, DATA, LATCH, and RI_OUT.
, PCREQ,
GND
V
V
CCA
V
CCB
V
CCI
V
CCP
V
CCZ
A1, D4, D8, D13, D17, H4, H17,
N4, N17, U4, U8, U13, U17
D6, D11, D15, F4, F17, K4, L17,
CC
R4, R17, U6, U10, U15
K2, R3, W5 J4, N6, W5
B16, C10, F18, A15, B10, F19
V10 P9
K20, P18, V15, W20 K14, N18, V14, V18 Clamp voltage for PCI signaling (3.3 V or 5 V)
A4, D1 D6, E4 Clamp voltage for zoom video interface (3.3 V or 5 V)
TERMINAL
NAME GFN NO. GJG NO.
CLOCK U12 R11 I/O
DATA V12 T11 O
LATCH W12 V11 O
I/O
TYPE
Table 6. PC Card power switch
3-line power switch clock. Information on the DA TA line is sampled at the rising edge
of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1251A output by
using the P2CCLK bit in the system control register. The TPS2206 defines the
maximum frequency of this signal to be 2 MHz. If a system design defines this terminal
as an output, CLOCK requires an external pulldown resistor. The frequency of the
PCI1251A output CLOCK is derived by dividing the PCI CLK by 36.
3-line power switch data. DA TA is used to serially communicate socket power-control
information to the power switch.
3-line power switch latch. LATCH is asserted by the PCI1251A to indicate to the PC
Card power switch that the data on the DATA line is valid.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
Terminal Functions (Continued)
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Table 7. PCI system
TERMINAL
NAME GFN NO. GJG NO.
CLKRUN
PCLK J17 J15 I
PRST
J18 J16 I/O
J19 J18 I
I/O
TYPE
PCI clock run. CLKRUN is used by the central resource to request permission to stop the
PCI clock or to slow it down, and the PCI1251A responds accordingly. If CLKRUN
implemented, this pin should be tied low. CLKRUN
(KEEPCLK) in the system control register.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals
are sampled at the rising edge of PCLK.
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1251A to place all
output buffers in a high-impedance state and reset all internal registers. When PRST
asserted, the device is completely nonfunctional. After PRST
is in its default state. When the SUSPEND
the PRST
high-impedance state, but the contents of the registers are preserved.
, and the internal registers are preserved. All outputs are placed in a
mode is enabled, the device is protected from
is enabled by default by bit 1
is deasserted, the PCI1251A
is not
is
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
PCI1251A GFN/GJG
FUNCTION
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Terminal Functions (Continued)
Table 8. PCI Address and Data
TERMINAL
NAME GFN NO. GJG NO.
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3
C/BE2
C/BE1
C/BE0
PAR Y20 W18 I/O
K18
K19
L20
L18
L19
M20
M19
M18
N19
N18
P20
P19
R20
R19
P17
R18
V18
Y19
W18
V17
U16
Y18
W17
V16
W16
U14
Y16
W15
V14
Y15
W14
Y14
M17
T20
W19
Y17
K16
K18
L14
L15
L18
L19
L16
M15
M19
M14
N16
N19
N15
P18
P19
P16
T16
W17
V16
W16
T15
V15
W15
P14
T14
W14
P13
T13
V13
W13
N13
R12
M16
P15
V17
R14
TYPE
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit
I/O
address or other destination information. During the data phase, AD31–AD0 contain data.
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, C/BE3
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which
I/O
byte paths of the full 32-bit data bus carry meaningful data. C/BE0
C/BE1
applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies
to byte 3 (AD31–AD24).
PCI bus parity. In all PCI bus read and write cycles, the PCI1251A calculates even parity across
the AD31–AD0 and C/BE3
this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is
compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error
(PERR
).
–C/BE0 buses. As an initiator during PCI cycles, the PCI1251A outputs
–C/BE0 define the bus command.
applies to byte 0 (AD7–AD0),
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
Terminal Functions (Continued)
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Table 9. PCI Interface Control
TERMINAL
NAME GFN NO. GJG NO.
DEVSEL
FRAME
GNT
GPIO2/LOCK
IDSEL N20 M18 I
IRDY
PERR
REQ
SERR
STOP
TRDY
V20 T18 I/O
T19 R18 I/O
J20 J14 I
V19 V19 I/O
T18 R19 I/O
U18 U18 I/O
K17 K15 O
U19 U19 O
T17 T19 I/O
U20 R16 I/O
I/O
TYPE
PCI device select. The PCI1251A asserts DEVSEL to claim a PCI cycle as the target device.
As a PCI initiator on the bus, the PCI1251A monitors DEVSEL
target responds before timeout occurs, the PCI1251A terminates the cycle with an initiator
abort.
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is
asserted. When FRAME
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1251A access to the
PCI bus after the current data transaction has completed. GNT
bus request, depending on the PCI bus parking algorithm.
PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI
LOCK
and used to gain exclusive access downstream. Since this functionality is not typically
used, a general-purpose I/O may be accessed through this terminal. GPIO2/LOCK
to a general-purpose input and can be configured through the GPIO2 control register.
Initialization device select. IDSEL selects the PCI1251A during configuration space
accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of PCLK where both
IRDY
and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states
are inserted.
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity
does not match PAR when PERR is enabled through bit 6 of the command register.
PCI bus request. REQ is asserted by the PCI1251A to request access to the PCI bus as an
initiator.
PCI system error. SERR is an output that is pulsed from the PCI1251A when enabled
through the command register, indicating a system error has occurred. The PCI1251A need
not be the target of the PCI cycle to assert this signal. When SERR
control register, this signal also pulses, indicating that an address parity error has occurred
on a CardBus interface.
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the
current PCI bus transaction. STOP
by target devices that do not support burst data transfers.
PCI target ready. TRDY indicates the primary bus target’s ability to complete the current
data phase of the transaction. A data phase is completed on a rising edge of PCLK when
both IRDY
inserted.
and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are
is deasserted, the PCI bus transaction is in the final data phase.
is used for target disconnects and is commonly asserted
until a target responds. If no
may or may not follow a PCI
defaults
is enabled in the bridge
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
PCI1251A GFN/GJG
FUNCTION
FUNCTION
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Terminal Functions (Continued)
Table 10. System Interrupt
TERMINAL
NAME GFN NO. GJG NO.
GPIO3/INTA
IRQSER/INTB W13 W12 I/O
IRQMUX7
IRQMUX6
IRQMUX5
IRQMUX4
IRQMUX3
IRQMUX2
IRQMUX1
IRQMUX0
RI_OUT/PME Y13 P12 O
NAME GFN NO. GJG NO.
PCGNT/
IRQMUX6
PCREQ/
IRQMUX7
V13 T12 I/O
Y12
U11
W10
Y9
W9
V9
U9
Y8
TERMINAL
U11 R10 I/O
Y12 P11 O
P11
R10
R9
W9
T9
R8
T8
V8
I/O
TYPE
O
I/O
TYPE
Parallel PCI interrupt. INT A can be optionally mapped to GPI03 when parallel PCI interrupts
are used.
See
interrupt subsystem
to a general-purpose input.
Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme.
Serialized PCI interrupts can also be sent in the IRQSER stream. See
on page 32 for details on interrupt signaling. This terminal can be used to signal PCI INTB
when one of the parallel interrupt modes is selected in the device control register.
Interrupt request/secondary functions multiplexed. The primary function of these terminals
is to provide the ISA-type IRQ signaling supported by the PCI1251A. These interrupt
multiplexer outputs can be mapped to any of 15 IRQs. The device control register must be
programmed for the ISA IRQ interrupt mode and the IRQMUX routing register must have
the IRQ routing programmed before these terminals are enabled.
All of these terminals have secondary functions, such as PCI INTB
request/grant, ring indicate output, and zoom video status, that can be selected with the
appropriate programming of this register. When the secondary functions are enabled, the
respective terminals are not available for IRQ routing.
See the IRQMUX routing register for programming options.
Ring Indicate Out and Power Management Event Output. Terminal provides an output for
ring-indicate or PME
on page 32 for details on interrupt signaling. GPIO3/INTA defaults
interrupt subsystem
, PC/PCI DMA
signals.
T able 11. PC/PCI DMA
PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system
supporting the PC/PCI DMA scheme.
Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6
interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs.
IRQMUX6 takes precedence over PCGNT
PC/PCI DMA.
This terminal is also used for the serial EEPROM interface.
PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system
supporting the PC/PCI DMA scheme.
Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7
interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs.
IRQMUX7 takes precedence over PCREQ
PC/PCI DMA.
This terminal is also used for the serial EEPROM interface.
, and should not be enabled in a system using
, and should not be enabled in a system using
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
Terminal Functions (Continued)
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Table 12. Zoom Video
TERMINAL
NAME
ZV_HREF
ZV_VSYNC
ZV_Y7
ZV_Y6
ZV_Y5
ZV_Y4
ZV_Y3
ZV_Y2
ZV_Y1
ZV_Y0
ZV_UV7
ZV_UV6
ZV_UV5
ZV_UV4
ZV_UV3
ZV_UV2
ZV_UV1
ZV_UV0
ZV_SCLK C2 B1 A7 O Audio SCLK PCM
ZV_MCLK D3 C2 A6 O Audio MCLK PCM
ZV_PCLK E1 E2 IOIS16 O Pixel clock to the zoom video port
ZV_LRCLK E3 E5 INPACK O Audio LRCLK PCM
ZV_SDATA E2 E1 SPKR O Audio SDATA PCM
NC F1 F4 O Reserved. No connection.
ZV_RSVD
ZV_RSVD
GFN
GJG NO.
NO.
A6 G7 A10 O
C7 A7 A11 O
A3
B4
C5
B5
C6
D7
A5
B6
D2
C3
B1
B2
A2
C4
B3
D5
C1
E4
B5
A5
E6
B6
A6
F7
E7
B7
C1
A2
B2
A3
B3
A4
B4
D5
D2
D1
I/O AND MEMORY
INTERFACE
SIGNAL
A20
A14
A19
A13
A18
A8
A17
A9
A25
A12
A24
A15
A23
A16
A22
A21
A5
A4
TYPE
Horizontal sync to the zoom video port
Vertical sync to the zoom video port
O Video data to the zoom video port in YV:4:2:2 format
O Video data to the zoom video port in YV:4:2:2 format
Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0
O
are put into the high-impedance state by host adapter.
FUNCTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
PCI1251A GFN/GJG
I/O
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Terminal Functions (Continued)
TERMINAL
NAME GFN NO.
GPIO0/LEDA1 V11 T10 I/O
GPIO1/LEDA2 W11 V10 I/O
SPKROUT
SUSPEND
Y10 P10 O
Y11 W10 I
GJG
NO.
TYPE
Table 13. Miscellaneous
FUNCTION
GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it
provides an output indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be
configured as a general-purpose input and output, GPIO0. The zoom video enable signal
(ZV_STAT) can also be routed to this signal through the GPIO0 control register.
GPIO0/LEDA1 defaults to a general-purpose input.
GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it
provides an output indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be
configured as a general-purpose input and output, GPIO1. A CSC interrupt can be
generated on a GPDATA change, and this input can be used for power switch overcurrent
(OC) sensing. See
to a general-purpose input.
Speaker output. SPKROUT is the output to the host system that can carry SPKR or
CAUDIO through the PCI1251A from the PC Card interface. SPKROUT is driven as the
exclusive-OR combination of card SPKR
Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is
asserted. See
GPIO1 control register
SUSPEND mode
for programming details. GPIO1/LEDA2 defaults
//CAUDIO inputs.
for details.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
Terminal Functions (Continued)
Table 14. 16-bit PC Card Address and Data (slots A and B)
TERMINAL
GFN NO. GJG NO.
NAME
D15
D14
D13
D12
D10
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal T4 is A_A25.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal C14 is B_A25.
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SLOT
†
A
T4
U2
U1
P4
R2
R1
P1
N2
M4
T1
T2
P2
N3
T3
M1
L1
M3
N1
V1
V2
V3
W2
W3
W4
V4
U5
K3
J2
J4
H2
G1
W8
Y7
V7
J1
J3
H1
H3
G2
V8
W7
Y6
SLOT
‡
B
C14
B15
C15
C16
A18
C17
B18
A20
C18
A17
A16
B17
A19
D14
D18
E18
B20
B19
A15
A14
B13
A13
C12
A12
B11
C11
E19
E20
G18
G19
H18
B7
C8
A8
G17
F19
F20
G20
H19
A7
B8
D9
SLOT
†
A
R2
P6
P2
N5
N1
M5
M2
L5
L2
N4
P1
M4
M1
P4
K4
J5
L1
L4
R1
T1
T4
U2
V2
W3
V3
W4
J1
H2
H6
G1
G6
W8
W7
R7
H4
H1
G4
G5
F2
T7
V7
P7
SLOT
B
E13
A14
E14
E15
B16
B17
A18
B19
D16
D15
B15
A17
B18
D14
D19
F15
C19
C18
F13
A13
A12
B12
E12
A11
B11
E11
F18
G15
G19
H15
H18
E8
B8
E9
G14
G18
G13
H16
H19
D8
F8
D9
I/O
TYPE
‡
O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.
I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
PCI1251A GFN/GJG
FUNCTION
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Terminal Functions (Continued)
Table 15. 16-bit PC Card Interface Control (slots A and B)
TERMINAL
GFN NO. GJG NO.
NAME
BVD1
(STSCHG
BVD2
(SPKR
CD1
CD2
CE1
CE2
INPACK Y1 D12 V1 D12 I
IORD
IOWR
SLOT
/RI)
)
SLOT
†
A
V6 A9 R6 E10 I
Y5 D10 V5 D10 I
G3W6H20C9F1W6H14
K1L2D20
L4 E17 K2 E16 O
M2 C19 L6 D18 O
SLOT
‡
B
A
D19J2K6
SLOT
†
F16
E19
B
B9
I/O
TYPE
‡
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that
include batteries. BVD1 is used with BVD2 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the
battery is good. When BVD2 is low and BVD1 is high, the battery is weak and
should be replaced. When BVD1 is low, the battery is no longer serviceable and
the data in the memory PC Card is lost. See ExCA card status-change interrupt
configuration
register
this signal.
Status change. STSCHG
write protect, or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that
include batteries. BVD2 is used with BVD1 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and should be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See ExCA card status-change interrupt configuration
register
page 83
this signal.
Speaker. SPKR is an optional binary audio signal available only when the card
and socket have been configured for the 16-bit I/O interface. The audio signals
from cards A and B are combined by the PCI1251A and are output on SPKROUT .
DMA request. BVD2 can be used as the DMA request signal during DMA
operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2
to indicate a request for a DMA operation.
PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected
to ground on the PC Card. When a PC Card is inserted into a socket, CD1
I
CD2
.
80
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered
address bytes. CE1
O
odd-numbered address bytes.
Input acknowledge. INP ACK is asserted by the PC Card when it can respond to
an I/O read cycle at the current address.
DMA request. INPACK can be used as the DMA request signal during DMA
operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC
Card asserts this signal to indicate a request for a DMA operation.
I/O read. IORD is asserted by the PCI1251A to enable 16-bit I/O PC Card data
output during host I/O read cycles.
DMA write. IORD is used as the DMA write strobe during DMA operations from
a 16-bit PC Card that supports DMA. The PCI1251A asserts IORD
transfers from the PC Card to host memory.
I/O write. IOWR is driven low by the PCI1251A to strobe write data into 16-bit I/O
PC Cards during host I/O write cycles.
DMA read. IOWR
a 16-bit PC Card that supports DMA. The PCI1251A asserts IOWR
transfers from host memory to the PC Card.
register on page 84 for enable bits. See ExCA card status-change
and the ExCA interface status register on page 80 for the status bits for
is used to alert the system to a change in the READY,
on page 84 for enable bits. See ExCA card status-change register on
and the ExCA interface status register on page 80 for the status bits for
are pulled low. For signal status, see ExCA interface status register on page
enables even-numbered address bytes, and CE2 enables
is used as the DMA write strobe during DMA operations from
and
during DMA
during
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
PCI1251A GFN/GJG
PC CARD CONTROLLER
Terminal Functions (Continued)
Table 15. 16-bit PC Card Interface Control (slots A and B) (continued)
TERMINAL
GFN NO. GJG NO.
NAME
OE L3 C20 K1 E18 O
READY
(IREQ
REG
RESET W1 C13 T2 D13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
WAIT
WE P3 D16 N7 A16 O
WP
(IOIS16
VS1
VS2
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal P3 is A_WE.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal D16 is B_WE
SLOT
SLOT
†
A
)
Y4 A10 T5 F10 I
Y2 B12 W2 D11 O
V5 B10 R5 A10 I
U7 B9 T6 A9 I
)
Y3U3A11
SLOT
‡
B
B14V4R4
SLOT
†
A
F11
B13
I/O
TYPE
‡
B
Output enable. OE is driven low by the PCI1251A to enable 16-bit memory PC
Card data output during host memory read cycles.
DMA terminal count. OE
to a 16-bit PC Card that supports DMA. The PCI1251A asserts OE
for a DMA write operation.
Ready. The ready function is provided by READY when the 16-bit PC Card and
the host socket are configured for the memory-only interface. READY is driven
low by the 16-bit memory PC Cards to indicate that the memory card circuits are
busy processing a previous write command. READY is driven high when the
16-bit memory PC Card is ready to accept a new data transfer command.
Interrupt request. IREQ
that a device on the 16-bit I /O PC Card requires service by the host software.
IREQ
is high (deasserted) when no interrupt is requested.
Attribute memory select. REG remains high for all common memory accesses.
When REG
and to the I/O space (IORD
accessed section of card memory and is generally used to record card capacity
and other configuration and attribute information.
DMA acknowledge. REG
operations to a 16-bit PC Card that supports DMA. The PCI1251A asserts REG
to indicate a DMA operation. REG is used in conjunction with the DMA read
(IOWR
Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e.,
extend) the memory or I/O cycle in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC
Cards. WE
memory technologies.
DMA terminal count. WE
that supports DMA. The PCI1251A asserts WE
operation.
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of
the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is
used for the 16-bit port (IOIS16
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the
16-bit PC Card when the address on the bus corresponds to an address to which
the 16-bit PC Card responds, and the I/O port that is addressed is capable of
16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations
to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to
indicate a request for a DMA operation.
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction
I/O
with each other, determine the operating voltage of the 16-bit PC Card.
is asserted, access is limited to attribute memory (OE or WE active)
) or DMA write (IORD) strobes to transfer data.
is also used for memory PC Cards that employ programmable
is used as terminal count (TC) during DMA operations
is asserted by a 16-bit I/O PC Card to indicate to the host
or IOWR active). Attribute memory is a separately
is used as a DMA acknowledge (DACK) during DMA
is used as TC during DMA operations to a 16-bit PC Card
to indicate TC for a DMA read
) function.
.
SCPS038 – AUGUST 1998
to indicate TC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
PCI1251A GFN/GJG
FUNCTION
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Terminal Functions (Continued)
Table 16. CardBus PC Card Interface System (slots A and B)
TERMINAL
GFN NO. GJG NO.
NAME
CCLK T1 A17 N4 D15 O
CCLKRUN
CRST
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal T1 is A_CCLK.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal A17 is B_CCLK.
SLOT
SLOT
†
A
U7 B9 T6 A9 O
W1 C13 T2 D13 I/O
SLOT
‡
B
SLOT
†
A
B
I/O
TYPE
‡
CardBus PC Card clock. CCLK provides synchronous timing for all transactions on
the CardBus interface. All signals except CRST
CAUDIO, CCD2:1
all timing parameters are defined with the rising edge of this signal. CCLK operates
at the PCI bus clock frequency, but it can be stopped in the low state or slowed down
for power savings.
CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request
an increase in the CCLK frequency, and by the PCI1251A to indicate that the CCLK
frequency is decreased. CardBus clock run (CCLKRUN
(CLKRUN
CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific
registers, sequencers, and signals to a known state. When CRST
CardBus PC Card signals must be 3-stated, and the PCI1251A drives these signals
to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must
be synchronous to CCLK.
, and CVS2–CVS1 are sampled on the rising edge of CCLK, and
)
, CCLKRUN, CINT, CSTSCHG,
) follows the PCI clock run
is asserted, all
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
Terminal Functions (Continued)
Table 17. CardBus PC Card Address and Data (slots A and B)
TERMINAL
B
E8
B8
F8
E9
D9
I/O
TYPE
‡
PC Card address and data. These signals make up the multiplexed CardBus address
and data bus on the CardBus interface. During the address phase of a CardBus cycle,
I/O
CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31–CAD0 contain data. CAD31 is the most-significant bit.
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of a CardBus cycle,
CC/BE3
–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is
used as byte enables. The byte enables determine which byte paths of the full 32-bit
I/O
data bus carry meaningful data. CC/BE0
applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and
CC/BE3
applies to byte 3 (CAD31–CAD24).
CardBus parity. In all CardBus read and write cycles, the PCI1251A calculates even
parity across the CAD and CC/BE
PCI1251A outputs CP AR with a one-CCLK delay . As a target during CardBus cycles,
the calculated parity is compared to the initiator’s parity indicator; a compare error
results in a parity error assertion.
applies to byte 0 (CAD7–CAD0), CC/BE1
buses. As an initiator during CardBus cycles, the
GFN NO. GJG NO.
NAME
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CC/BE3
CC/BE2
CC/BE1
CC/BE0
CPAR N3 A19 M1 B18 I/O
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal N3 is A_CPAR.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_CPAR.
SLOT
†
A
W8
Y7
W7
V7
Y6
U5
V4
W4
W3
W2
V3
V2
T4
V1
U2
M4
M2
M3
L4
M1
L3
L2
L1
K3
J1
J4
J3
H2
H1
G1
H3
G2
Y2
T3
N1
K1
SLOT
‡
B
B7
C8
B8
A8
D9
C11
B11
A12
C12
A13
B13
A14
C14
A15
B15
C18
C19
B20
E17
D18
C20
D19
E18
E19
G17
G18
F19
G19
F20
H18
G20
H19
B12
D14
B19
D20
SLOT
†
A
W8
W7
V7
R7
P7
W4
V3
W3
V2
U2
T4
T1
R2
R1
P6
L2
L6
L1
K2
K4
K1
K6
J5
J1
H4
H6
H1
G1
G4
G6
G5
F2
W2
P4
L4
J2
SLOT
E11
B11
A11
E12
B12
A12
A13
E13
F13
A14
D16
D18
C19
E16
D19
E18
E19
F15
F18
G14
G19
G18
H15
G13
H18
H16
H19
D11
D14
C18
F16
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
PCI1251A GFN/GJG
FUNCTION
I
ith CVS1
CVS2 to identif
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
Terminal Functions (Continued)
Table 18. CardBus PC Card Interface Control (slots A and B)
TERMINAL
GFN NO. GJG NO.
NAME
CAUDIO Y5 D10 V5 D10 I
CBLOCK
CCD1
CCD2
CDEVSEL
CFRAME
CGNT
CINT
CIRDY
CPERR
CREQ
CSERR
CSTOP
CSTSCHG
CTRDY
CVS1
CVS2
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal Y5 is A_CAUDIO.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal D10 is B_CAUDIO.
SLOT
SLOT
†
A
P1 B18 M2 A18 I/O
G3 H20 F1 H14
W6 C9 W6 B9
R2 A18 N1 B16 I/O
U1 C15 P2 E14 I/O
P3 D16 N7 A16 I
Y4 A10 T5 F10 I
T2 A16 P1 B15 I/O
P2 B17 M4 A17 I/O
Y1 D12 V1 D12 I
V5 B10 R5 A10 I
R1 C17 M5 B17 I/O
V6 A9 R6 E10 I
P4 C16 N5 E15 I/O
Y3U3A11
SLOT
‡
B
B14V4R4
SLOT
†
A
B
F11
B13
I/O
TYPE
‡
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system
speaker. The PCI1251A supports the binary audio mode and outputs a binary signal
from the card to SPKROUT.
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction
w
the operating voltage and card type.
CardBus device select. The PCI1251A asserts CDEVSEL to claim a CardBus cycle
as the target device. As a CardBus initiator on the bus, the PCI1251A monitors
CDEVSEL
PCI1251A terminates the cycle with an initiator abort.
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle.
CFRAME
transfers continue while this signal is asserted. When CFRAME
CardBus bus transaction is in the final data phase.
CardBus bus grant. CGNT is driven by the PCI1251A to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been completed.
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt
servicing from the host.
CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete
the current data phase of the transaction. A data phase is completed on a rising
edge of CCLK when both CIRDY
CTRDY
CardBus parity error. CPERR is used to report parity errors during CardBus
transactions, except during special cycles. It is driven low by a target two clocks
following that data when a parity error is detected.
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires
use of the CardBus bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system
errors that could lead to catastrophic results. CSERR
synchronous to CCLK, but deasserted by a weak pullup, and may take several
CCLK periods. The PCI1251A can report CSERR
SERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop
the current CardBus transaction. CSTOP
commonly asserted by target devices that do not support burst data transfers.
CardBus status change. CSTSCHG is used to alert the system to a change in the
card’s status and is used as a wake-up mechanism.
CardBus target ready. CTRDY indicates the CardBus target’ s ability to complete the
current data phase of the transaction. A data phase is completed on a rising edge
of CCLK, when both CIRDY
are inserted.
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used
I/O
in conjunction with CCD1
to determine the operating voltage and card type.
and
until a target responds. If no target responds before timeout occurs, the
is asserted to indicate that a bus transaction is beginning, and data
are both sampled asserted, wait states are inserted.
on the PCI interface.
y card insertion and interrogate cards to determine
and CTRDY are asserted. Until CIRDY and
and CTRDY are asserted; until this time, wait states
and CCD2 to identify card insertion and interrogate cards
is deasserted, the
is driven by the card
to the system by assertion of
is used for target disconnects, and is
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
power supply sequencing
The PCI1251A contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltage.
The core power supply is always 3.3 V . The clamp voltage can be either 3.3 V or 5 V , depending on the interface.
The following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Apply 3.3-V power to the core.
2. Assert PRST
to the device to disable the outputs during power up. Output drivers must be powered up in
the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.
3. Apply the clamp voltage.
The power-down sequence is:
1. Use PRST
to switch outputs to a high-impedance state.
2. Remove the clamp voltage.
3. Remove the 3.3-V power from the core.
I/O characteristics
Figure 1 shows a 3-state bidirectional buffer. The
provides the electrical characteristics of the inputs and outputs.
NOTE:
The PCI1251A meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus
Specification Rev. 2.2.
Tied for Open Drain
OE
recommended operating conditions
V
CCP
Pad
table, on page 109,
Figure 1. 3-State Bidirectional Buffer
NOTE:
Unused pins (input or I/O) must be held high or low to prevent them from floating.
clamping rail voltages
The clamping voltages are set to match whatever external environment the PCI1251A will be working with: 3.3
V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage that protects the core from external
signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI1251A must reliably accommodate both voltage levels. This
is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied.
If a system designer desires a 5-V PCI bus, V
The PCI1251A requires five separate clamping voltages because it supports a wide range of features. The five
rails are listed and defined in the
recommended operating conditions
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
can be connected to a 5-V power supply.
CCP
, on page 109.
23
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
PCI interface
This section describes the PCI interface of the PCI1251A and how the device responds and participates in PCI
bus cycles. The PCI1251A provides all required signals for PCI master/slave devices, and can operate in either
5-V or 3.3-V PCI signaling environments by connecting the V
PCI bus lock (LOCK)
The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the
PCI1251A as an additional compatibility feature. The PCI LOCK
terminal function defaults to a general-purpose input (GPI). Note that the use of LOCK
PCI-to-CardBus bridges in the downstream direction (away from the processor).
terminals to the desired signaling level.
CCP
terminal is multiplexed with GPIO2, and the
is only supported by
PCI LOCK
asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a
transaction on the PCI bus does not guarantee control of LOCK
protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK
Note that the CardBus signal for this protocol is CBLOCK
An agent may need to do an exclusive operation because a critical access to memory might be broken into
several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock
is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without
interfering with nonexclusive real-time data transfer, such as video.
loading the subsystem identification (EEPROM interface)
The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space
located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile
dock) identification purposes and is required by some operating systems. Implementation of this unique
identifier register is a PC ’95 requirement.
The PCI1251A offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read only, but can be made read/write by clearing the SUBSYSRW bit in the system
control register (bit 5, offset 80h). Once this bit is cleared (0), the BIOS can write a subsystem identification value
into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID
register and subsystem ID register is limited to read-only access. This approach saves the added cost of
implementing the serial EEPROM.
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID
register must be loaded with a unique identifier through a serial EEPROM interface. The PCI1251A loads the
doubleword of data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND
gates the PCI reset from the entire PCI1251A core, including the serial EEPROM state machine (see
mode
a serial EEPROM.
indicates an atomic operation that may require multiple transactions to complete. When LOCK is
; control of LOCK is obtained under its own
to avoid confusion with the bus clock.
, on page 37, for details on using SUSPEND). The PCI1251A provides a two-line serial bus interface to
.
input
suspend
The system designer must implement a pulldown resistor on the PCI1251A LA TCH terminal to indicate the serial
EEPROM mode. Only when this pulldown resistor is present will the PCI1251A attempt to load data through
the serial EEPROM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA)
and one clock signal (SCL). SDA is mapped to the PCI1251A IRQMUX6 terminal and SCL is mapped to the
PCI1251A IRQMUX7 terminal. A typical PCI1251A application using the serial EEPROM interface is shown in
Figure 2.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
loading the subsystem identification (EEPROM interface) (continued)
V
CC
Serial
EEPROM
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
PCI1251A
A0
A1
A2
SCL
SDA
IRQMUX7
IRQMUX6
LATCH
Figure 2. Serial EEPROM Application
When the PCI1251A is reset, the subsystem data is read automatically from the EEPROM. The PCI1251A
masters the serial EEPROM bus and reads four bytes, as shown in Figure 3.
The EEPROM is addressed at word address 00h, as shown in Figure 3, and the address auto increments after
each byte transfer according to the protocol. Thus, to provide the subsystem register with data AABBCCDDh,
the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.
Slave Address Word Address
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
R/W
Data Byte 0 M
Data Byte 1 Data Byte 2 Data Byte 3 M PMM
M = Master acknowledgement
Sb6 b4b5 b3 b2 b1 b0 1 A
Restart
S/P = Start/stop conditionA = Slave acknowledgement
Slave Address
R/W
Figure 3. EEPROM Interface Subsystem Data Collection
The serial EEPROM is addressed at slave address 1010000b by the PCI1251A. All hardware address bits for
the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the
sample application circuit (Figure 2) assumes the 1010b high address nibble. The lower three address bits are
terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.
The serial EEPROM interface signals require pullup resistors, and the protocol is defined for the bidirectional
transfers. Both SCL and SDA are 3-stated and pulled high when the bus is not active. When the SDA line
transitions low, this signals a start condition (S). A low-to-high transition of SDA while SCL is high is defined as
the stop condition (P). One bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as a control
signal. Data is valid and stable during the clock high period. This protocol is shown in Figure 4.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
loading the subsystem identification (EEPROM interface) (continued)
SDA
SCL
Start
Condition
Stop
Condition
Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 4. Serial EEPROM Start/Stop Conditions and Bit Transfers
Each address byte and data transfer is followed by an acknowledge bit, as shown in Figure 3. When the
PCI1251A transmits the addresses, it returns SDA to the high state and 3-states the line. The PCI1251A then
generates an SCL clock cycle and expects the EEPROM to pull down SDA during the acknowledge pulse. This
procedure is referred to as a slave acknowledge with the PCI1251A transmitter and EEPROM receiver. General
acknowledges are shown in Figure 5.
During the data byte transfers from the serial EEPROM to the PCI1251A, the EEPROM clocks the SCL signal.
After the EEPROM transmits the data to the PCI1251A, it returns the SDA signal to the high state and 3-states
the line. The EEPROM then generates an SCL clock cycle and expects the PCI1251A to pull down SDA during
the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM transmitter
and PCI1251A receiver. General acknowledges are shown in Figure 5.
SCL From
Master
SDA Output
By Transmitter
123 789
SDA Output
By Receiver
Figure 5. Serial EEPROM Protocol – Acknowledge
EEPROM interface status information is communicated through the general status register located at PCI offset
85h. The EEDETECT bit in this register indicates whether or not the PCI1251A serial EEPROM circuitry detects
the pulldown resistor on LA TCH. An error condition, such as a missing acknowledge, results in the DATAERR
bit being set. The EEBUSY bit is set while the subsystem ID register is loading (serial EEPROM interface is
busy).
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PC Card applications
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
This section describes the following PC Card interfaces: PC Card recognition (which details the card
interrogation procedure), card-powering procedure (including the protocol of the P
2
C power-switch interface),
internal zoom video (ZV) buffering provided by the PCI1251A and programming model, standard PC Card
register models, and a brief discussion of the PC Card software protocol layers.
PC Card insertion/removal and recognition
The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, unpowered socket. Through this
interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined.
The scheme uses the CD1
, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). A
PC Card designer connects these four terminals in prescribed configuration determined by the type of card and
the supply voltage. The encoding scheme for this is defined in the 1997 PC Card Standard and is shown in
Table 19.
Table 19. PC Card Card-Detect and Voltage-Sense Connections
CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE
Ground Ground Open Open 5 V 16-bit PC Card 5 V
Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V
Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V
Ground Ground Open Ground LV 16-bit PC Card 3.3 V
Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V
Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V
Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V
Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V
Ground Ground Ground Open LV 16-bit PC Card Y.Y V
Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V
Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V
Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V
Ground Connect to CVS1 Ground Connect to CCD1 Reserved
Ground Connect to CVS2 Connect to CCD1 Ground Reserved
P2C power-switch interface (TPS2206)
A power switch with a PCMCIA-to-peripheral control (P
interface. The TI TPS2206 dual-slot PC Card power-interface switch provides the P
2
C) interface is required for the PC Card powering
2
C interface to the CLOCK,
DA TA, and LATCH terminals of the PCI1251A. Figure 6 shows the terminal assignments of the TPS2206 and
Figure 7 illustrates a typical application where the PCI1251A represents the PCMCIA controller.
The CLOCK terminal on the PCI1251A can be an input or an output depending on whether bit 27 of the system
control register is a 0 or a 1. The default is for the CLOCK terminal to be an input to control the serial interface
and the PCI1251A internal state machine. The P2CCLK bit in the system control register can be set by the
system BIOS to enable the PCI1251A to internally generate and drive the CLOCK from the PCI clock. When
the system design implements CLOCK as an output from the PCI1251A, an external pulldown resistor is
required since the CLOCK terminal defaults to an input.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
P2C power-switch interface (TPS2206) (continued)
Power Supply
12 V
5 V
3.3 V
Supervisor
5V
5V
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
NC
RESET
3.3V
NC – No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
NC
NC
NC
NC
NC
12V
BVPP
BVCC
BVCC
BVCC
NC
OC
3.3V
3.3V
Figure 6. TPS2206 Terminal Assignments
TPS2206
12V
5V
3.3V
RESET
RESET
AVPP
AVCC
AVCC
AVCC
V
V
V
V
PP1
PP2
CC
CC
PC Card
A
PCMCIA
Controller
3
Serial Interface
OC
BVPP
BVCC
BVCC
BVCC
Figure 7. TPS2206 Typical Application
V
V
V
V
PP1
PP2
CC
CC
PC Card
B
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
zoom video support
The ZV port on the PCI1251A provides an internally buffered 16-bit ZV PC Card data path. This internal routing
is programmed through the multimedia control register. Figure 8 shows the zoom video subsystem implemented
in the PCI1251A and details the bit functions found in the multimedia control register.
An output port (PORTSEL) is always selected. The PCI1251A defaults to socket 0 (see the multimedia control
register on page 59). When ZVOUTEN is asserted, the zoom video output terminals are enabled to allow the
PCI1251A to route the zoom video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is
enabled in the multimedia control register. When the PORTSEL maps to a card port that is disabled (ZVEN0
or ZVEN1) then the zoom video port is driven low; that is, no data is transmitted.
Zoom Video Subsystem
PC Card
Socket 0
PC Card
Socket 1
Card
Output
Enable
Logic
Card
Output
Enable
Logic
PC Card
Interface
PC Card
Interface
ZVEN0
ZVOUTEN
ZVSTAT
(see Note A)
VGA
PORTSEL
Zoom Video
Port
ZVEN1
NOTES: A. ZVSTAT must be enabled through the GPIO control register.
Figure 8. Zoom Video Subsystem
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
29
PCI1251A GFN/GJG
PC CARD CONTROLLER
SCPS038 – AUGUST 1998
SPKROUT usage
SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured
for I/O mode, the BVD2 pin becomes SPKR
applications. SPKR
passes a TTL-level digital audio signal to the PCI1251A. The CardBus CAUDIO signal also
can pass a single-amplitude binary waveform. The binary audio signals from the two PC Card sockets are
XORed in the PCI1251A to produce SPKROUT. Figure 9 shows the SPKROUT connection.
Bit 1, Card Control Register (offset 91h)
Card A SPKROUT Enable
Card A SPKR
Bit 1, Card Control Register (offset 91h)
Card B SPKROUT Enable
Card B SPKR
Figure 9. SPKROUT Connection to Speaker Driver
. This terminal, referred to as CAUDIO, is also used in CardBus
SPKROUT
Card A SPKROUT Enable
Card B SPKROUT Enable
Speaker
Driver
The SPKROUT signal is typically driven only by modem PC Cards. To verify SPKROUT on the PCI1251A, a
sample circuit was constructed, and this simplified schematic is shown in Figure 10.
NOTE:
Earlier versions of the PC Card controller multiplexed SUSPEND/SPKROUT on the same pin,
which meant that a pullup resistor was needed to differentiate the signals. Because the PCI1251A
does not multiplex this or any other function on SPKROUT, this terminal does not require a pullup
resistor.
V
CC
V
CC
SPKROUT
3
7
2
6
+
–
4
LM386
1
8
Speaker
Figure 10. Simplified Test Schematic
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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