TEXAS INSTRUMENTS PCI1251A Technical data

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(PCI) Power Management 1.0 Compliant

ACPI 1.0 Compliant

Packaged in GFN 256-Pin BGA or GJG MicroStar BGA

PCI Local Bus Specification Revision 2.2 Compliant

1997 PC Card Standard Compliant

PC 99 Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards

Supports Two PC Card or CardBus Slots With Hot Insertion and Removal

Uses Serial Interface to TI TPS2206 Dual Power Switch

Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and the CardBus Bus

Supports Serialized Interrupt request (IRQ) With PCI Interrupts

8-Way Legacy IRQ Multiplexing

System Interrupts Can Be Programmed as PCI Style or Industry Standard Architecture (ISA-IRQ) Style

ISA-IRQ Interrupts Can Be Serialized Onto a Single IRQ Serial (IRQSER) Pin

EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus

Supports Zoom Video With Internal Buffering

Four General Purpose I/Os

Multifunction PCI Device With Separate Configuration Space for Each Socket

Five PCI Memory Windows and Two I/O Windows Available for Each PC Card16 Socket

Two I/O Windows and Two Memory Windows Available to Each CardBus Socket

Exchangeable Card Architecture (ExCA) Compatible Registers Are Mappable in Memory and I/O Space

Supports Distributed DMA (DDMA) and PC/PCI DMA

Intel 82365SL-DF Register Compatible

Supports 16-Bit DMA on Both PC Card Sockets

Supports Ring Indicate, SUSPEND, PCI CLKRUN,

Advanced Submicron, Low-Power CMOS T echnology

Provides VGA/Palette Memory and I/O and Subtractive Decoding Options

LED Activity Pins

Supports PCI Bus Lock (LOCK)

and CardBus CCLKRUN

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Name/Terminal Number Sort Tables 4. . . . . . . . . . . . . . . . .

Terminal Functions 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Sequencing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Rail Voltages 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Interface 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Applications 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 32. . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 36. . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Controller Programming Model 39. . . . . . . . . . . . . . . . . .

PCI Configuration Registers (Functions 0 and 1) 39. . . . . . . . . . .

ExCA Compatibility Registers (Functions 0 and 1) 75. . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

CardBus Socket Registers (Functions 0 and 1) 98. . . . . . . . . . . . . . .

Distributed DMA (DDMA) Registers 106. . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 112. . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 114. . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 115. . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 116. . . . . . . . . . . . . . .

PC Card Cycle Timing 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements, (Memory Cycles) 118. . . . . . . . . . . . . . . . . . . .

Timing Requirements, (I/O Cycles) 118. . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics (Miscellaneous) 119. . . . . . . . . . . . . . . . . .

PC Card Parameter Mesasurement Information 120. . . . . . . . . . . . . .

Mechanical Data 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1251A GFN/GJG PC CARD CONTROLLER

SCPS038 – AUGUST 1998

description

The TI PCI1251A is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two independent PC Card sockets compliant with the 1997 PC Card Standard. The PCI1251A provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1251A supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or

3.3 V, as required. The PCI1251A is compliant with the latest

the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions.

Multiple system-interrupt signaling options are provided and they include:

Parallel PCI interrupts

Parallel ISA interrupts

Serialized ISA interrupts

Serialized ISA and PCI interrupts

Additionally, general-purpose inputs and outputs are provided for the board designer to implement sideband functions.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1251A is register compatible with the Intel 82365SL-DF ExCA controller . The PCI1251A internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1251A can also be programmed to accept fast posted writes to improve system-bus utilization.

The PCI1251A provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC board manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading specifications. Many other features, such as socket activity light-emitting diode (LED) outputs, are designed into the PCI1251A. These features are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

PCI Bus Power Management Specification

. It is also compliant with

Unused PCI1251A inputs must be pulled up using a 43 kW resistor.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

system block diagram

A simplified system block diagram using the PCI1251A is provided below. The zoomed video (ZV) capability can be used to route the ZV data directly to the VGA controller.

The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode), 23 of the 68 signals are redefined to support the ZV protocol.

The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. The ring indicate terminal is included in the interrupt interface because its function is to perform system wake up on incoming PC Card modem rings. Other miscellaneous system interface terminals available on the PCI1251A include:

Programmable general purpose multifunction terminals

SUSPEND, RI_OUT/PME (power management control signal)

SPKROUT

PCI Bus

Activity LED’s

CLKRUN

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video

mode, 23 pins are used for routing the zoomed video signals to the VGA controller.

23 for ZV

(See Note)

23 for ZV

PCI1251A

Enable

IRQSER

†

DMA PME

Zoom Video

South Bridge

19 Video

4 Audio

†

Interrupt Routing Options:

1) Serialized, including PCI and ISA

2) Serialized ISA and parallel PCI

3) Parallel PCI and parallel ISA

4) Parallel PCI interrupts only

Embedded

Controller

VGA

Controller

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1251A GFN/GJG PC CARD CONTROLLER

SCPS038 – AUGUST 1998

signal names and terminal assignments

Signal names and their terminal assignments are shown in Tables 1 through 4 sorted alpha-numerically by the assigned terminal.

Table 1. GFN Terminals Sorted Alpha-Numerically for CardBus and 16-Bit Signals

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8

GND ZV_UV3 ZV_Y7 V

CCZ

ZV_Y1 ZV_HREF B_RSVD//B_D2 B_CAD28//B_D8 B_CSTSCHG//B_BVD1(STSCHG B_CINT

//B_READY(IREQ) B_CVS1//B_VS1 B_CAD24//B_A2 B_CAD22//B_A4 B_CAD20//B_A6 B_CAD18//B_A7 B_CIRDY B_CCLK//B_A16 B_CDEVSEL B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV5 ZV_UV4 ZV_UV1 ZV_Y6 ZV_Y4 ZV_Y0 B_CAD31//B_D10 B_CAD29//B_D1 B_CCLKRUN B_CSERR B_CAD25//B_A1 B_CC/BE3 B_CAD21//B_A5 B_CVS2//B_VS2 B_CAD17//B_A24 V B_CPERR B_CBLOCK B_CC/BE1 B_CAD14//B_A9 ZV_RSVD1 ZV_SCLK ZV_UV6 ZV_UV2 ZV_Y5 ZV_Y3 ZV_VSYNC B_CAD30//B_D9

//B_A15

//B_A21

//B_WP(IOIS16)

//B_WAIT

//B_REG

CCB

//B_A14

//B_A19

//B_A8

/RI)

B_CCD2//B_CD2

C10

V C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F4 F17 F18 F19 F20 G1 G2 G3

CCB

B_CAD26//B_A0

B_CAD23//B_A3

B_CRST

B_CAD19//B_A25

B_CFRAME

B_CTRDY

B_CSTOP

B_CAD16//B_A17

B_CAD15//B_IOWR

B_CAD11//B_OE

ZV_UV7

ZV_MCLK

GND

ZV_UV0

ZV_Y2

GND

B_CAD27//B_D0

B_CAUDIO//B_BVD2(SPKR

B_CREQ

GND

B_CC/BE2

B_CGNT

GND

B_CAD12//B_A11

B_CAD10//B_CE2

B_CC/BE0//B_CE1

ZV_PCLK

ZV_SDATA

ZV_LRCLK

ZV_RSVD0

B_CAD13//B_IORD

B_CAD9//B_A10

B_CAD8//B_D15

B_RSVD//B_D14

B_CAD5//B_D6

B_CAD3//B_D5

A_CAD2//A_D1 1

A_CAD0//A_D3

A_CCD1

//B_RESET

CCZ

CC CC CCB

//A_CD1

//B_A23 //B_A22 //B_A20

//B_INPACK

//B_A12

//B_WE

G17

B_CAD7//B_D7

G18

B_CAD6//B_D13

G19

B_CAD4//B_D12

G20

B_CAD1//B_D4

A_CAD3//A_D5

A_CAD4//A_D12

A_CAD1//A_D4

GND

H17

GND

H18

B_CAD2//B_D1 1

H19

B_CAD0//B_D3

H20

B_CCD1

A_CAD7//A_D7

A_RSVD//A_D14

A_CAD5//A_D6

A_CAD6//A_D13

J17

PCLK

J18

CLKRUN

J19

PRST

J20

GNT

A_CC/BE0//A_CE1

)

A_CAD8//A_D15

K17

REQ

K18

AD31

K19

AD30

K20

A_CAD9//A_A10

A_CAD10//A_CE2

A_CAD11//A_OE

A_CAD13//A_IORD

L17

L18

AD28

L19

AD27

L20

AD29

A_CAD12//A_A11

A_CAD15//A_IOWR

A_CAD14//A_A9

A_CAD16//A_A17

M17

C/BE3

M18

AD24

M19

AD25

M20

AD26

A_CC/BE1

A_RSVD//A_A18

A_CPAR//A_A13

//B_CD1

CCA

CCP

//A_A8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

signal names and terminal assignments (continued)

Table 1. GFN Terminals Sorted Alpha-Numerically for CardBus and 16-Bit Signals (Continued)

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8

GND GND AD22 AD23 IDSEL A_CBLOCK A_CPERR A_CGNT A_CTRDY//A_A22 AD17 V

CCP

AD20 AD21 A_CSTOP A_CDEVSEL V

CCA

AD16 AD18 AD19 A_CCLK//A_A16 A_CIRDY A_CC/BE2 A_CAD19//A_A25 STOP IRDY FRAME C/BE2 A_CFRAME//A_23 A_CAD17//A_A24 A_CVS2//A_VS2 GND A_CAD26//A_A0 V

A_CCLKRUN GND

//A_A19

//A_A14

//A_WE

//A_A20

//A_A21

//A_A15

//A_A12

//A_WP(IOIS16)

IRQMUX1

U10

V U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5

PCGNT

/IRQMUX6 CLOCK GND AD6 V

AD11 GND PERR SERR TRDY A_CAD18//A_A7 A_CAD20//A_A6 A_CAD21//A_A5 A_CAD25//A_A1 A_CSERR A_CSTSCHG//A_BVD1(STSCHG/RI) A_CAD28//A_D8 A_RSVD//A_D2 IRQMUX2 V

CCI

GPIO0/LEDA1 DATA GPIO3/INTA AD3 V

CCP

AD8 AD12 AD15 GPIO2/LOCK DEVSEL A_CRST//A_RESET A_CAD22//A_A4 A_CAD23//A_A3 A_CAD24//A_A2 V

CCA

//A_WAIT

A_CCD2//A_CD2

A_CAD29//A_D1

A_CAD31//A_D10

IRQMUX3

W10

IRQMUX5

W11

GPIO1/LEDA2

W12

LATCH

W13

IRQSER/INTB

W14

AD1

W15

AD4

W16

AD7

W17

AD9

W18

AD13

W19

C/BE1

W20

V Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20

CCP

A_CREQ

A_CC/BE3//A_REG

A_CVS1//A_VS1

A_CINT//A_READY(IREQ)

A_CAUDIO//A_BVD2(SPKR

A_CAD27//A_D0

A_CAD30//A_D9

IRQMUX0

IRQMUX4

SPKROUT

SUSPEND

PCREQ/IRQMUX7

RI_OUT

/PME AD0 AD2 AD5 C/BE0 AD10 AD14 PAR

//A_INPACK

)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1251A GFN/GJG PC CARD CONTROLLER

SCPS038 – AUGUST 1998

signal names and terminal assignments (continued)

Table 2. GJG Terminals Sorted Alpha-Numerically for CardBus and 16-bit Signals

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11

ZV_UV6 ZV_UV4 ZV_UV2 ZV_Y6 ZV_Y3 ZV_VSYNC V

B_CCLKRUN B_CSERR B_CAD24//B_A2 B_CAD21//B_A5 B_CAD20//B_A6 B_CAD17//B_A24 V

CCB

B_CGNT B_CPERR//B_A14 B_CBLOCK ZV_SCLK ZV_UV5 ZV_UV3 ZV_UV1 ZV_Y7 ZV_Y4 ZV_Y0 B_CAD30//B_D9 B_CCD2 V

CCB

B_CAD25//B_A1 B_CAD22//B_A4 B_CVS2//B_VS2 GND B_CIRDY B_CDEVSEL B_CSTOP B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV7 ZV_MCLK B_CC/BE1 B_CAD14//B_A9 ZV_RSVD0 ZV_RSVD1 GND ZV_UV0 V

CCZ

GND B_RSVD//B_D2 B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR B_CC/BE3

//B_WP(IOIS16)

//B_WAIT

//B_WE

//B_A19

//B_CD2

//B_A15

//B_A21

//B_A20

//B_A8

//B_REG

D12

B_CREQ//B_INPACK

D13

B_CRST//B_RESET

D14

B_CC/BE2

D15

B_CCLK//B_A16

D16

B_CAD16//B_A17

D18

B_CAD15//B_IOWR

D19

B_CAD12//B_A11

ZV_SDATA

ZV_PCLK

V E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E18 E19 F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F18 F19 G1 G2 G4 G5 G6 G7 G13

)

G14 G15

CCZ

ZV_LRCLK

ZV_Y5

ZV_Y1

B_CAD31//B_D10

B_CAD28//B_D8

B_CSTSCHG//B_BVD1(STSCHG/RI

B_CAD26//B_A0

B_CAD23//B_A3

B_CAD19//B_A25

B_CFRAME

B_CTRDY

B_CAD13//B_IORD

B_CAD11//B_OE

B_CAD10//B_CE2

A_CCD1//A_CD1

A_CAD0//A_D3

GND

ZV_Y2

B_CAD29//B_D1

GND

B_CINT

B_CVS1//B_VS1

B_CAD18//B_A7

VCC

B_CAD9//B_A10

B_CC/BE0

B_CAD8//B_D15

CCB

A_CAD4//A_D12

A_CAD3//A_D5

A_CAD1//A_D4

A_CAD2//A_D1 1

ZV_HREF

B_CAD3//B_D5

B_CAD7//B_D7

B_RSVD//B_D14

//B_A12

//B_A23

//B_A22

//B_READY(IREQ)

//B_CE1

G16

GND

G18

B_CAD5//B_D6

G19

B_CAD6//B_D13

A_CAD5//A_D6

A_RSVD//A_D14

A_CAD7//A_D7

GND

A_CAD6//A_D13

H14

B_CCD1

H15

B_CAD4//B_D12

H16

B_CAD1//B_D4

H18

B_CAD2//B_D1 1

H19

B_CAD0//B_D3

A_CAD8//A_D15

A_CC/BE0

A_CAD9//A_A10

J14

GNT

J15

PCLK

J16

CLKRUN

J18

PRST

J19

GND

A_CAD11//A_OE

A_CAD13//A_IORD

A_CAD12//A_A11

GND

A_CAD10//A_CE2

K14

K15

REQ

K16

AD31

K18

AD30

K19

A_CAD14//A_A9

A_CAD16//A_A17

A_CC/BE1

A_RSVD//A_A18

A_CAD15//A_IOWR

L14

AD29

L15

AD28

L16

AD25

L18

AD27

L19

AD26

A_CPAR//A_A13

A_CBLOCK

A_CPERR

A_CSTOP

M14

AD22

M15

AD24

//B_CD1

//A_CE1

CCA

CCP

//A_A8

//A_A19 //A_A14 //A_A20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

signal names and terminal assignments (continued)

Table 2. GFN Terminals Sorted Alpha-Numerically for CardBus and 16-bit Signals. (Continued)

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

M16 M18 M19 N1 N2 N4 N5 N6 N7 N13 N14 N15 N16 N18 N19 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P18 P19 R1 R2 R4 R5

CBE3 IDSEL AD23 A_CDEVSEL GND A_CCLK//A_A16 A_CTRDY V

CCA

A_CGNT AD1 GND AD19 AD21 V

CCP

AD20 A_CIRDY A_CFRAME A_CC/BE2 V

A_CAD17//A_A24 A_CAD27//A_D0 V

CCI

SPKROUT PCREQ/IRQMUX7 RI_OUT AD5 AD8 C/BE2 AD16 AD18 AD17 A_CAD18//A_A7 A_CAD19//A_A25 A_CVS2//A_VS2 A_CSERR//A_WAIT

//A_A21

//A_A22

//A_WE

//A_A15

//A_23

//A_A12

/PME

A_CSTSCHG//A_BVD1(STSCHG/RI)

A_CAD28//A_D8

IRQMUX2

IRQMUX5

R10

PCGNT

/IRQMUX6

R11

CLOCK

R12

AD0

R13

GND

R14

C/BE0

R15

V R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U18 U19 V1 V2

TRDY

FRAME

IRDY

A_CAD20//A_A6

A_CRST

A_CAD21//A_A5

A_CINT

A_CCLKRUN

A_RSVD//A_D2

IRQMUX1

IRQMUX3

GPIO0/LEDA1

DATA

GPI03/INTA

AD4

AD7

AD11

AD15

DEVSEL

STOP

GND

A_CAD22//A_A4

PERR

SERR

A_CREQ//A_INPACK

A_CAD23//A_A3

//A_RESET

//A_READY(IREQ)

//A_WP(IOIS16)

A_CAD25//A_A1

A_CVS1//A_VS1

A_CAUDIO//A_BVD2(SPKR)

GND

A_CAD29//A_D1

IRQMUX0

GND

V10

GPI01/LEDA2

V11

LATCH

V12

V V13 V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18

AD3

CCP

AD10

AD13

C/BE1

CCP

GPI02/LOCK

A_CC/BE3//A_REG

A_CAD24//A_A2

A_CAD26//A_A0

CCA

A_CCD2

A_CAD30//A_D9

A_CAD31//A_D10

IRQMUX4

SUSPEND

GND

IRQSER/INTB

AD2

AD6

AD9

AD12

AD14

PAR

//A_CD2

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PCI1251A GFN/GJG PC CARD CONTROLLER

SCPS038 – AUGUST 1998

signal names and terminal assignments (continued)

Table 3. CardBus Signal Names Sorted Alpha-Numerically for GFN and GJG Pins

SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG

A_CAD0 A_CAD1 A_CAD2 A_CAD3 A_CAD4 A_CAD5 A_CAD6 A_CAD7 A_CAD8 A_CAD9 A_CAD10 A_CAD11 A_CAD12 A_CAD13 A_CAD14 A_CAD15 A_CAD16 A_CAD17 A_CAD18 A_CAD19 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD28 A_CAD29 A_CAD30 A_CAD31 A_CAUDIO A_CBLOCK A_CC/BE0 A_CC/BE1 A_CC/BE2 A_CC/BE3 A_CCD1 A_CCD2

G2 H3 G1 H1 H2 J3 J4 J1 K3 L1 L2 L3 M1 L4 M3 M2 M4 U2 V1 T4 V2 V3 W2 W3 W4 V4 U5 Y6 V7 W7 Y7 W8 Y5 P1 K1 N1 T3 Y2 G3 W6

F2 G5 G6 G4 G1 H1 H6 H4 J1 J5 K6 K1 K4 K2 L1 L6 L2 P6 R1 R2 T1 T4 U2 V2 W3 V3 W4 P7 R7 V7 W7 W8 V5 M2 J2 L4 P4 W2 F1 W6

A_CCLK A_CCLKRUN A_CDEVSEL A_FRAME A_CGNT A_CINT A_CIRDY A_CPAR A_CPERR A_CREQ A_CRST A_CSERR A_CSTOP A_CSTSCHG A_CTRDY A_CVS1 A_CVS2 A_RSVD A_RSVD A_RSVD B_CAD00 B_CAD01 B_CAD02 B_CAD03 B_CAD04 B_CAD05 B_CAD06 B_CAD07 B_CAD08 B_CAD09 B_CAD10 B_CAD11 B_CAD12 B_CAD13 B_CAD14 B_CAD15 B_CAD16 B_CAD17 B_CAD18 B_CAD19

T1 U7 R2 U1 P3 Y4 T2 N3 P2 Y1 W1 V5 R1 V6 P4 Y3 U3 J2 N2 V8 H19 G20 H18 F20 G19 F19 G18 G17 E19 E18 D19 C20 D18 E17 B20 C19 C18 B15 A15 C14

N4 T6 N1 P2 N7 T5 P1 M1 M4 V1 T2 R5 M5 R6 N5 V4 R4 H2 L5 T7 H19 H16 H18 G13 H15 G18 G19 G14 F18 F15 E19 E18 D19 E16 C19 D18 D16 A14 F13 E13

B_CAD20 B_CAD21 B_CAD22 B_CAD23 B_CAD24 B_CAD25 B_CAD26 B_CAD27 B_CAD28 B_CAD29 B_CAD30 B_CAD31 B_CAUDIO B_CBLOCK B_CCBE0 B_CCBE1 B_CCBE2 B_CCBE3 B_CCD1 B_CCD2 B_CCLK B_CCLKRUN B_CDEVSEL B_CFRAME B_CGNT B_CINT B_CIRDY B_CPAR B_CPERR B_CREQ B_CRST B_CSERR B_CSTOP B_CSTSCHG B_CTRDY B_CVS1 B_CVS2 B_RSVD B_RSVD B_RSVD

A14 B13 A13 C12 A12 B11 C11 D9 A8 B8 C8 B7 D10 B18 D20 B19 D14 B12 H20 C9 A17 B9 A18 C15 D16 A10 A16 A19 B17 D12 C13 B10 C17 A9 C16 A11 B14 A20 A7 E20

A13 A12 B12 E12 A11 B11 E11 D9 E9 F8 B8 E8 D10 A18 F16 C18 D14 D11 H14 B9 D15 A9 B16 E14 A16 F10 B15 B18 A17 D12 D13 A10 B17 E10 E15 F11 B13 B19 D8 G15

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SCPS038 – AUGUST 1998

signal names and terminal assignments (continued)

Table 4. 16 Bit Signal Names Sorted Alpha-Numerically for GFN and GJG Pins

SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG SIGNAL NAME GFN GJG

A_A00 A_A01 A_A02 A_A03 A_A04 A_A05 A_A06 A_A07 A_A08 A_A09 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19 A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 A_BVD1 A_BVD2 A_CD1 A_CD2 A_CE1 A_CE2 A_D00 A_D01 A_D02 A_D03 A_D04 A_D05 A_D06 A_D07

U5 V4 W4 W3 W2 V3 V2 V1 N1 M3 L1 M1 T3 N3 P2 T2 T1 M4 N2 P1 R1 R2 P4 U1 U2 T4 V6 Y5 G3 W6 K1 L2 Y6 W7 V8 G2 H3 H1 J3 J1

W4 V3 W3 V2 U2 T4 T1 R1 L4 L1 J5 K4 P4 M1 M4 P1 N4 L2 L5 M2 M5 N1 N5 P2 P6 R2 R6 V5 F1 W6 J2 K6 P7 V7 T7 F2 G5 G4 H1 H4

A_D08 A_D09 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_INPACK A_IORD A_IOWR A_OE A_RDY A_REG A_RESET A_VS1 A_VS2 A_WAIT A_WE A_WP B_A00 B_A01 B_A02 B_A03 B_A04 B_A05 B_A06 B_A07 B_A08 B_A09 B_A10 B_A11 B_A12 B_A13 B_A14 B_A15 B_A16 B_A17 B_A18 B_A19

V7 Y7 W8 G1 H2 J4 J2 K3 Y1 L4 M2 L3 Y4 Y2 W1 Y3 U3 V5 P3 U7 C11 B11 A12 C12 A13 B13 A14 A15 B19 B20 E18 D18 D14 A19 B17 A16 A17 C18 A20 B18

R7 W7 W8 G6 G1 H6 H2 J1 V1 K2 L6 K1 T5 W2 T2 V4 R4 R5 N7 T6 E11 B11 A11 E12 B12 A12 A13 F13 C18 C19 F15 D19 D14 B18 A17 B15 D15 D16 B19 A18

B_A20 B_A21 B_A22 B_A23 B_A24 B_A25 B_BVD1 B_BVD2 B_CD1 B_CD2 B_CE1 B_CE2 B_D00 B_D01 B_D02 B_D03 B_D04 B_D05 B_D06 B_D07 B_D08 B_D09 B_D10 B_D11 B_D12 B_D13 B_D14 B_D15 B_INPACK B_IORD B_IOWR B_OE B_RDY B_REG B_RESET B_VS1 B_VS2 B_WAIT B_WE B_WP

C17 A18 C16 C15 B15 C14 A9 D10 H20 C9 D20 D19 D9 B8 A7 H19 G20 F20 F19 G17 A8 C8 B7 H18 G19 G18 E20 E19 D12 E17 C19 C20 A10 B12 C13 A11 B14 B10 D16 B9

B17 B16 E15 E14 A14 E13 E10 D10 H14 B9 F16 E19 D9 F8 D8 H19 H16 G13 G18 G14 E9 B8 E8 H18 H15 G19 G15 F18 D12 E16 D18 E18 F10 D11 D13 F11 B13 A10 A16 A9

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PCI1251A GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

Table 5. Power Supply

TERMINAL

NAME GFN NO. GJG NO.

B14, D4, D7, F5, F9, G16, H5,

J19, K5, N2, N14, R13, U1, V6,

V9, W11

A8, F6, F12, F14, G2, J6, K19,

M6, P5, P8, R15, V12

Device ground terminals

Power supply terminal for core logic (3.3 V) Clamp voltage for PC Card A interface. Indicates Card A

signaling environment. Clamp voltage for PC Card B interface. Indicates Card B

signaling environment. Clamp voltage for interrupt subsystem interface and

miscellaneous I/O. Indicates signaling level of the following inputs and shared outputs: IRQSER, PCGNT SUSPEND INTA

, SPKROUT, GPIO1:0, IRQMUX7–IRQMUX0,

, INTB, CLOCK, DATA, LATCH, and RI_OUT.

, PCREQ,

GND

CCA

CCB

CCI

CCP

CCZ

A1, D4, D8, D13, D17, H4, H17,

N4, N17, U4, U8, U13, U17

D6, D11, D15, F4, F17, K4, L17,

R4, R17, U6, U10, U15

K2, R3, W5 J4, N6, W5

B16, C10, F18, A15, B10, F19

V10 P9

K20, P18, V15, W20 K14, N18, V14, V18 Clamp voltage for PCI signaling (3.3 V or 5 V)

A4, D1 D6, E4 Clamp voltage for zoom video interface (3.3 V or 5 V)

TERMINAL

NAME GFN NO. GJG NO.

CLOCK U12 R11 I/O

DATA V12 T11 O

LATCH W12 V11 O

I/O

TYPE

Table 6. PC Card power switch

3-line power switch clock. Information on the DA TA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1251A output by using the P2CCLK bit in the system control register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz. If a system design defines this terminal as an output, CLOCK requires an external pulldown resistor. The frequency of the PCI1251A output CLOCK is derived by dividing the PCI CLK by 36.

3-line power switch data. DA TA is used to serially communicate socket power-control information to the power switch.

3-line power switch latch. LATCH is asserted by the PCI1251A to indicate to the PC Card power switch that the data on the DATA line is valid.

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FUNCTION

Terminal Functions (Continued)

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Table 7. PCI system

TERMINAL

NAME GFN NO. GJG NO.

CLKRUN

PCLK J17 J15 I

PRST

J18 J16 I/O

J19 J18 I

I/O

TYPE

PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI1251A responds accordingly. If CLKRUN implemented, this pin should be tied low. CLKRUN (KEEPCLK) in the system control register.

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1251A to place all output buffers in a high-impedance state and reset all internal registers. When PRST asserted, the device is completely nonfunctional. After PRST is in its default state. When the SUSPEND the PRST high-impedance state, but the contents of the registers are preserved.

, and the internal registers are preserved. All outputs are placed in a

mode is enabled, the device is protected from

is enabled by default by bit 1

is deasserted, the PCI1251A

is not

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FUNCTION

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SCPS038 – AUGUST 1998

Terminal Functions (Continued)

Table 8. PCI Address and Data

TERMINAL

NAME GFN NO. GJG NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR Y20 W18 I/O

K18 K19 L20 L18

L19 M20 M19 M18 N19 N18 P20 P19 R20 R19 P17 R18 V18 Y19 W18 V17 U16 Y18 W17 V16 W16 U14 Y16 W15 V14 Y15 W14 Y14

M17

T20 W19 Y17

K16 K18

L14 L15 L18 L19

L16 M15 M19 M14 N16 N19 N15 P18 P19 P16 T16

W17

V16

W16

T15 V15

W15

P14 T14

W14

P13 T13 V13

W13

N13 R12

M16 P15 V17 R14

TYPE

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit

I/O

address or other destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which

I/O

byte paths of the full 32-bit data bus carry meaningful data. C/BE0 C/BE1

applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies

to byte 3 (AD31–AD24). PCI bus parity. In all PCI bus read and write cycles, the PCI1251A calculates even parity across

the AD31–AD0 and C/BE3 this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

–C/BE0 buses. As an initiator during PCI cycles, the PCI1251A outputs

–C/BE0 define the bus command.

applies to byte 0 (AD7–AD0),

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FUNCTION

Terminal Functions (Continued)

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Table 9. PCI Interface Control

TERMINAL

NAME GFN NO. GJG NO.

DEVSEL

FRAME

GNT

GPIO2/LOCK

IDSEL N20 M18 I

IRDY

PERR

REQ

SERR

STOP

TRDY

V20 T18 I/O

T19 R18 I/O

J20 J14 I

V19 V19 I/O

T18 R19 I/O

U18 U18 I/O

K17 K15 O

U19 U19 O

T17 T19 I/O

U20 R16 I/O

I/O

TYPE

PCI device select. The PCI1251A asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1251A monitors DEVSEL target responds before timeout occurs, the PCI1251A terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1251A access to the PCI bus after the current data transaction has completed. GNT bus request, depending on the PCI bus parking algorithm.

PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI LOCK

and used to gain exclusive access downstream. Since this functionality is not typically used, a general-purpose I/O may be accessed through this terminal. GPIO2/LOCK to a general-purpose input and can be configured through the GPIO2 control register.

Initialization device select. IDSEL selects the PCI1251A during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY

and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states

are inserted. PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity

does not match PAR when PERR is enabled through bit 6 of the command register. PCI bus request. REQ is asserted by the PCI1251A to request access to the PCI bus as an

initiator. PCI system error. SERR is an output that is pulsed from the PCI1251A when enabled

through the command register, indicating a system error has occurred. The PCI1251A need not be the target of the PCI cycle to assert this signal. When SERR control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP by target devices that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY inserted.

and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are

is deasserted, the PCI bus transaction is in the final data phase.

is used for target disconnects and is commonly asserted

until a target responds. If no

may or may not follow a PCI

defaults

is enabled in the bridge

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FUNCTION

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Terminal Functions (Continued)

Table 10. System Interrupt

TERMINAL

NAME GFN NO. GJG NO.

GPIO3/INTA

IRQSER/INTB W13 W12 I/O

IRQMUX7 IRQMUX6 IRQMUX5 IRQMUX4 IRQMUX3 IRQMUX2 IRQMUX1 IRQMUX0

RI_OUT/PME Y13 P12 O

NAME GFN NO. GJG NO.

PCGNT/

IRQMUX6

PCREQ/

IRQMUX7

V13 T12 I/O

Y12 U11

W10

V9 U9 Y8

TERMINAL

U11 R10 I/O

Y12 P11 O

P11 R10

T9 R8 T8 V8

I/O

TYPE

I/O

TYPE

Parallel PCI interrupt. INT A can be optionally mapped to GPI03 when parallel PCI interrupts are used. See

interrupt subsystem

to a general-purpose input. Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme.

Serialized PCI interrupts can also be sent in the IRQSER stream. See on page 32 for details on interrupt signaling. This terminal can be used to signal PCI INTB when one of the parallel interrupt modes is selected in the device control register.

Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide the ISA-type IRQ signaling supported by the PCI1251A. These interrupt multiplexer outputs can be mapped to any of 15 IRQs. The device control register must be programmed for the ISA IRQ interrupt mode and the IRQMUX routing register must have the IRQ routing programmed before these terminals are enabled.

All of these terminals have secondary functions, such as PCI INTB request/grant, ring indicate output, and zoom video status, that can be selected with the appropriate programming of this register. When the secondary functions are enabled, the respective terminals are not available for IRQ routing.

See the IRQMUX routing register for programming options. Ring Indicate Out and Power Management Event Output. Terminal provides an output for

ring-indicate or PME

on page 32 for details on interrupt signaling. GPIO3/INTA defaults

interrupt subsystem

, PC/PCI DMA

signals.

T able 11. PC/PCI DMA

PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI DMA scheme.

Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX6 takes precedence over PCGNT PC/PCI DMA.

This terminal is also used for the serial EEPROM interface. PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system

supporting the PC/PCI DMA scheme. Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7

interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX7 takes precedence over PCREQ PC/PCI DMA.

This terminal is also used for the serial EEPROM interface.

, and should not be enabled in a system using

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I/O

Terminal Functions (Continued)

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Table 12. Zoom Video

TERMINAL

NAME

ZV_HREF

ZV_VSYNC

ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0

ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 ZV_UV2 ZV_UV1 ZV_UV0

ZV_SCLK C2 B1 A7 O Audio SCLK PCM

ZV_MCLK D3 C2 A6 O Audio MCLK PCM

ZV_PCLK E1 E2 IOIS16 O Pixel clock to the zoom video port ZV_LRCLK E3 E5 INPACK O Audio LRCLK PCM ZV_SDATA E2 E1 SPKR O Audio SDATA PCM

NC F1 F4 O Reserved. No connection.

ZV_RSVD ZV_RSVD

GFN

GJG NO.

NO.

A6 G7 A10 O C7 A7 A11 O A3

B4 C5 B5 C6 D7 A5 B6

D2 C3 B1 B2 A2 C4 B3 D5

C1 E4

B5 A5 E6 B6 A6 F7 E7 B7

C1 A2 B2 A3 B3 A4 B4 D5

D2 D1

I/O AND MEMORY

INTERFACE

SIGNAL

A20 A14 A19 A13 A18

A17

A25 A12 A24 A15 A23 A16 A22 A21

A5 A4

TYPE

Horizontal sync to the zoom video port Vertical sync to the zoom video port

O Video data to the zoom video port in YV:4:2:2 format

Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0

are put into the high-impedance state by host adapter.

FUNCTION

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I/O

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Terminal Functions (Continued)

TERMINAL

NAME GFN NO.

GPIO0/LEDA1 V11 T10 I/O

GPIO1/LEDA2 W11 V10 I/O

SPKROUT

SUSPEND

Y10 P10 O

Y11 W10 I

GJG

NO.

TYPE

Table 13. Miscellaneous

FUNCTION

GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it provides an output indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be configured as a general-purpose input and output, GPIO0. The zoom video enable signal (ZV_STAT) can also be routed to this signal through the GPIO0 control register. GPIO0/LEDA1 defaults to a general-purpose input.

GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it provides an output indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be configured as a general-purpose input and output, GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be used for power switch overcurrent (OC) sensing. See to a general-purpose input.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1251A from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR

Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See

GPIO1 control register

SUSPEND mode

for programming details. GPIO1/LEDA2 defaults

//CAUDIO inputs.

for details.

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FUNCTION

Terminal Functions (Continued)

Table 14. 16-bit PC Card Address and Data (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

D15 D14 D13 D12

D10

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal T4 is A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal C14 is B_A25.

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D11

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SLOT

†

T4 U2 U1 P4 R2 R1 P1 N2 M4 T1 T2 P2 N3 T3 M1

L1 M3 N1 V1 V2 V3

W2 W3 W4

V4 U5

J4 H2 G1

Y7 V7

J3 H1 H3 G2 V8

SLOT

‡

C14 B15 C15 C16 A18 C17 B18 A20 C18 A17 A16 B17 A19 D14 D18 E18 B20 B19 A15 A14 B13 A13 C12 A12 B11 C11

E19

E20 G18 G19

H18

B7 C8 A8

G17

F19

F20 G20

H19

A7 B8 D9

SLOT

†

R2 P6 P2 N5 N1 M5 M2

L2 N4 P1 M4 M1 P4 K4

L4 R1 T1 T4 U2 V2

J1 H2 H6

G1 G6 W8 W7

R7 H4 H1

G4 G5

F2 T7 V7 P7

SLOT

E13 A14 E14 E15 B16 B17 A18 B19 D16 D15 B15 A17 B18 D14 D19 F15 C19 C18 F13 A13 A12 B12 E12 A11 B11 E11

F18 G15 G19 H15 H18

E8 B8

E9 G14 G18 G13 H16 H19

I/O

TYPE

‡

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

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PCI1251A GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Terminal Functions (Continued)

Table 15. 16-bit PC Card Interface Control (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

BVD1

(STSCHG

BVD2

(SPKR

CD1 CD2

CE1 CE2

INPACK Y1 D12 V1 D12 I

IORD

IOWR

SLOT

/RI)

)

SLOT

†

V6 A9 R6 E10 I

Y5 D10 V5 D10 I

G3W6H20C9F1W6H14

K1L2D20

L4 E17 K2 E16 O

M2 C19 L6 D18 O

SLOT

‡

D19J2K6

SLOT

†

F16 E19

I/O

TYPE

‡

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register this signal.

Status change. STSCHG write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that

include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register page 83 this signal.

Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1251A and are output on SPKROUT .

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1

CD2

80 Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1

odd-numbered address bytes. Input acknowledge. INP ACK is asserted by the PC Card when it can respond to

an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA

operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1251A to enable 16-bit I/O PC Card data output during host I/O read cycles.

DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1251A asserts IORD transfers from the PC Card to host memory.

I/O write. IOWR is driven low by the PCI1251A to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

DMA read. IOWR a 16-bit PC Card that supports DMA. The PCI1251A asserts IOWR transfers from host memory to the PC Card.

and the ExCA interface status register on page 80 for the status bits for

is used to alert the system to a change in the READY,

on page 84 for enable bits. See ExCA card status-change register on

and the ExCA interface status register on page 80 for the status bits for

are pulled low. For signal status, see ExCA interface status register on page

enables even-numbered address bytes, and CE2 enables

is used as the DMA write strobe during DMA operations from

and

during DMA

during

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FUNCTION

PCI1251A GFN/GJG

PC CARD CONTROLLER

Terminal Functions (Continued)

Table 15. 16-bit PC Card Interface Control (slots A and B) (continued)

TERMINAL

GFN NO. GJG NO.

NAME

OE L3 C20 K1 E18 O

READY

(IREQ

REG

RESET W1 C13 T2 D13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE P3 D16 N7 A16 O

(IOIS16

VS1 VS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal P3 is A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal D16 is B_WE

SLOT

†

)

Y4 A10 T5 F10 I

Y2 B12 W2 D11 O

V5 B10 R5 A10 I

U7 B9 T6 A9 I

)

Y3U3A11

SLOT

‡

B14V4R4

SLOT

†

F11 B13

I/O

TYPE

‡

Output enable. OE is driven low by the PCI1251A to enable 16-bit memory PC Card data output during host memory read cycles.

DMA terminal count. OE to a 16-bit PC Card that supports DMA. The PCI1251A asserts OE for a DMA write operation.

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ that a device on the 16-bit I /O PC Card requires service by the host software. IREQ

is high (deasserted) when no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG and to the I/O space (IORD accessed section of card memory and is generally used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG operations to a 16-bit PC Card that supports DMA. The PCI1251A asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE memory technologies.

DMA terminal count. WE that supports DMA. The PCI1251A asserts WE operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16

I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction

I/O

with each other, determine the operating voltage of the 16-bit PC Card.

is asserted, access is limited to attribute memory (OE or WE active)

) or DMA write (IORD) strobes to transfer data.

is also used for memory PC Cards that employ programmable

is used as terminal count (TC) during DMA operations

is asserted by a 16-bit I/O PC Card to indicate to the host

or IOWR active). Attribute memory is a separately

is used as a DMA acknowledge (DACK) during DMA

is used as TC during DMA operations to a 16-bit PC Card

to indicate TC for a DMA read

) function.

SCPS038 – AUGUST 1998

to indicate TC

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PCI1251A GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Terminal Functions (Continued)

Table 16. CardBus PC Card Interface System (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CCLK T1 A17 N4 D15 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal T1 is A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal A17 is B_CCLK.

SLOT

†

U7 B9 T6 A9 O

W1 C13 T2 D13 I/O

SLOT

‡

SLOT

†

I/O

TYPE

‡

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST CAUDIO, CCD2:1 all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1251A to indicate that the CCLK frequency is decreased. CardBus clock run (CCLKRUN (CLKRUN

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST CardBus PC Card signals must be 3-stated, and the PCI1251A drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

, and CVS2–CVS1 are sampled on the rising edge of CCLK, and

)

, CCLKRUN, CINT, CSTSCHG,

) follows the PCI clock run

is asserted, all

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FUNCTION

Terminal Functions (Continued)

Table 17. CardBus PC Card Address and Data (slots A and B)

TERMINAL

E8 B8 F8 E9 D9

I/O

TYPE

‡

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3

–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is

used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. CC/BE0 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and CC/BE3

applies to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1251A calculates even parity across the CAD and CC/BE PCI1251A outputs CP AR with a one-CCLK delay . As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

applies to byte 0 (CAD7–CAD0), CC/BE1

buses. As an initiator during CardBus cycles, the

GFN NO. GJG NO.

NAME

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR N3 A19 M1 B18 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal N3 is A_CPAR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_CPAR.

SLOT

†

V7 Y6 U5

V4 W4 W3 W2

U2 M4 M2 M3

L3 L2 L1

J1 J4

J3 H2 H1 G1 H3 G2

Y2 T3 N1 K1

SLOT

‡

B7 C8 B8 A8

D9 C11 B11 A12 C12 A13 B13 A14 C14 A15 B15 C18 C19 B20 E17 D18 C20 D19 E18 E19 G17 G18 F19 G19 F20 H18 G20 H19

B12 D14 B19 D20

SLOT

†

W8 W7

V7 R7 P7

V2 U2 T4 T1 R2 R1 P6

L2 L6

L1 K2 K4 K1 K6

J1 H4 H6 H1 G1 G4 G6 G5 F2

SLOT

E11 B11

A11 E12 B12 A12 A13 E13

F13 A14 D16 D18 C19 E16 D19 E18 E19

F15

F18 G14 G19 G18 H15 G13 H18 H16 H19

D11 D14 C18

F16

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1251A GFN/GJG

FUNCTION

ith CVS1

CVS2 to identif

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

Terminal Functions (Continued)

Table 18. CardBus PC Card Interface Control (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CAUDIO Y5 D10 V5 D10 I

CBLOCK

CCD1 CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 CVS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal Y5 is A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal D10 is B_CAUDIO.

SLOT

†

P1 B18 M2 A18 I/O

G3 H20 F1 H14

W6 C9 W6 B9

R2 A18 N1 B16 I/O

U1 C15 P2 E14 I/O

P3 D16 N7 A16 I

Y4 A10 T5 F10 I

T2 A16 P1 B15 I/O

P2 B17 M4 A17 I/O

Y1 D12 V1 D12 I

V5 B10 R5 A10 I

R1 C17 M5 B17 I/O

V6 A9 R6 E10 I

P4 C16 N5 E15 I/O

Y3U3A11

SLOT

‡

B14V4R4

SLOT

†

F11

B13

I/O

TYPE

‡

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1251A supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

w the operating voltage and card type.

CardBus device select. The PCI1251A asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1251A monitors CDEVSEL PCI1251A terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME transfers continue while this signal is asserted. When CFRAME CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI1251A to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY CTRDY

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1251A can report CSERR SERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’ s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY are inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

I/O

in conjunction with CCD1 to determine the operating voltage and card type.

and

until a target responds. If no target responds before timeout occurs, the

is asserted to indicate that a bus transaction is beginning, and data

are both sampled asserted, wait states are inserted.

on the PCI interface.

y card insertion and interrogate cards to determine

and CTRDY are asserted. Until CIRDY and

and CTRDY are asserted; until this time, wait states

and CCD2 to identify card insertion and interrogate cards

is deasserted, the

is driven by the card

to the system by assertion of

is used for target disconnects, and is

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PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

power supply sequencing

The PCI1251A contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltage. The core power supply is always 3.3 V . The clamp voltage can be either 3.3 V or 5 V , depending on the interface. The following power-up and power-down sequences are recommended.

The power-up sequence is:

1. Apply 3.3-V power to the core.

2. Assert PRST

to the device to disable the outputs during power up. Output drivers must be powered up in

the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.

3. Apply the clamp voltage. The power-down sequence is:

1. Use PRST

to switch outputs to a high-impedance state.

2. Remove the clamp voltage.

3. Remove the 3.3-V power from the core.

I/O characteristics

Figure 1 shows a 3-state bidirectional buffer. The provides the electrical characteristics of the inputs and outputs.

NOTE:

The PCI1251A meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification Rev. 2.2.

Tied for Open Drain

recommended operating conditions

CCP

Pad

table, on page 109,

Figure 1. 3-State Bidirectional Buffer

NOTE:

Unused pins (input or I/O) must be held high or low to prevent them from floating.

clamping rail voltages

The clamping voltages are set to match whatever external environment the PCI1251A will be working with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1251A must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, V

The PCI1251A requires five separate clamping voltages because it supports a wide range of features. The five rails are listed and defined in the

recommended operating conditions

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can be connected to a 5-V power supply.

CCP

, on page 109.

PCI1251A GFN/GJG PC CARD CONTROLLER

SCPS038 – AUGUST 1998

PCI interface

This section describes the PCI interface of the PCI1251A and how the device responds and participates in PCI bus cycles. The PCI1251A provides all required signals for PCI master/slave devices, and can operate in either 5-V or 3.3-V PCI signaling environments by connecting the V

PCI bus lock (LOCK)

The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1251A as an additional compatibility feature. The PCI LOCK terminal function defaults to a general-purpose input (GPI). Note that the use of LOCK PCI-to-CardBus bridges in the downstream direction (away from the processor).

terminals to the desired signaling level.

CCP

terminal is multiplexed with GPIO2, and the

is only supported by

PCI LOCK asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK Note that the CardBus signal for this protocol is CBLOCK

An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video.

loading the subsystem identification (EEPROM interface)

The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC ’95 requirement.

The PCI1251A offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read only, but can be made read/write by clearing the SUBSYSRW bit in the system control register (bit 5, offset 80h). Once this bit is cleared (0), the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial EEPROM.

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier through a serial EEPROM interface. The PCI1251A loads the doubleword of data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND gates the PCI reset from the entire PCI1251A core, including the serial EEPROM state machine (see

mode

a serial EEPROM.

indicates an atomic operation that may require multiple transactions to complete. When LOCK is

; control of LOCK is obtained under its own

to avoid confusion with the bus clock.

, on page 37, for details on using SUSPEND). The PCI1251A provides a two-line serial bus interface to

input

suspend

The system designer must implement a pulldown resistor on the PCI1251A LA TCH terminal to indicate the serial EEPROM mode. Only when this pulldown resistor is present will the PCI1251A attempt to load data through the serial EEPROM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and one clock signal (SCL). SDA is mapped to the PCI1251A IRQMUX6 terminal and SCL is mapped to the PCI1251A IRQMUX7 terminal. A typical PCI1251A application using the serial EEPROM interface is shown in Figure 2.

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loading the subsystem identification (EEPROM interface) (continued)

Serial

EEPROM

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

PCI1251A

A0 A1 A2

SCL

SDA

IRQMUX7 IRQMUX6

LATCH

Figure 2. Serial EEPROM Application

When the PCI1251A is reset, the subsystem data is read automatically from the EEPROM. The PCI1251A masters the serial EEPROM bus and reads four bytes, as shown in Figure 3.

The EEPROM is addressed at word address 00h, as shown in Figure 3, and the address auto increments after each byte transfer according to the protocol. Thus, to provide the subsystem register with data AABBCCDDh, the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.

Slave Address Word Address

Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

R/W

Data Byte 0 M

Data Byte 1 Data Byte 2 Data Byte 3 M PMM

M = Master acknowledgement

Sb6 b4b5 b3 b2 b1 b0 1 A

Restart

S/P = Start/stop conditionA = Slave acknowledgement

Slave Address

R/W

Figure 3. EEPROM Interface Subsystem Data Collection

The serial EEPROM is addressed at slave address 1010000b by the PCI1251A. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 2) assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

The serial EEPROM interface signals require pullup resistors, and the protocol is defined for the bidirectional transfers. Both SCL and SDA are 3-stated and pulled high when the bus is not active. When the SDA line transitions low, this signals a start condition (S). A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as a control signal. Data is valid and stable during the clock high period. This protocol is shown in Figure 4.

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PCI1251A GFN/GJG PC CARD CONTROLLER

SCPS038 – AUGUST 1998

loading the subsystem identification (EEPROM interface) (continued)

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 4. Serial EEPROM Start/Stop Conditions and Bit Transfers

Each address byte and data transfer is followed by an acknowledge bit, as shown in Figure 3. When the PCI1251A transmits the addresses, it returns SDA to the high state and 3-states the line. The PCI1251A then generates an SCL clock cycle and expects the EEPROM to pull down SDA during the acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI1251A transmitter and EEPROM receiver. General acknowledges are shown in Figure 5.

During the data byte transfers from the serial EEPROM to the PCI1251A, the EEPROM clocks the SCL signal. After the EEPROM transmits the data to the PCI1251A, it returns the SDA signal to the high state and 3-states the line. The EEPROM then generates an SCL clock cycle and expects the PCI1251A to pull down SDA during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM transmitter and PCI1251A receiver. General acknowledges are shown in Figure 5.

SCL From

Master

SDA Output

By Transmitter

123 789

SDA Output

By Receiver

Figure 5. Serial EEPROM Protocol – Acknowledge

EEPROM interface status information is communicated through the general status register located at PCI offset 85h. The EEDETECT bit in this register indicates whether or not the PCI1251A serial EEPROM circuitry detects the pulldown resistor on LA TCH. An error condition, such as a missing acknowledge, results in the DATAERR bit being set. The EEBUSY bit is set while the subsystem ID register is loading (serial EEPROM interface is busy).

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PC Card applications

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

This section describes the following PC Card interfaces: PC Card recognition (which details the card interrogation procedure), card-powering procedure (including the protocol of the P

C power-switch interface), internal zoom video (ZV) buffering provided by the PCI1251A and programming model, standard PC Card register models, and a brief discussion of the PC Card software protocol layers.

PC Card insertion/removal and recognition

The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined.

The scheme uses the CD1

, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). A PC Card designer connects these four terminals in prescribed configuration determined by the type of card and the supply voltage. The encoding scheme for this is defined in the 1997 PC Card Standard and is shown in Table 19.

Table 19. PC Card Card-Detect and Voltage-Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE

Ground Ground Open Open 5 V 16-bit PC Card 5 V Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Open Ground LV 16-bit PC Card 3.3 V Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V

Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V

Ground Ground Ground Open LV 16-bit PC Card Y.Y V

Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V

Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved

P2C power-switch interface (TPS2206)

A power switch with a PCMCIA-to-peripheral control (P interface. The TI TPS2206 dual-slot PC Card power-interface switch provides the P

C) interface is required for the PC Card powering

C interface to the CLOCK, DA TA, and LATCH terminals of the PCI1251A. Figure 6 shows the terminal assignments of the TPS2206 and Figure 7 illustrates a typical application where the PCI1251A represents the PCMCIA controller.

The CLOCK terminal on the PCI1251A can be an input or an output depending on whether bit 27 of the system control register is a 0 or a 1. The default is for the CLOCK terminal to be an input to control the serial interface and the PCI1251A internal state machine. The P2CCLK bit in the system control register can be set by the system BIOS to enable the PCI1251A to internally generate and drive the CLOCK from the PCI clock. When the system design implements CLOCK as an output from the PCI1251A, an external pulldown resistor is required since the CLOCK terminal defaults to an input.

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PCI1251A GFN/GJG PC CARD CONTROLLER

SCPS038 – AUGUST 1998

P2C power-switch interface (TPS2206) (continued)

Power Supply

12 V

5 V

3.3 V

Supervisor

5V 5V

DATA

CLOCK

LATCH

RESET

12V

AVPP AVCC AVCC AVCC

GND

RESET

3.3V

NC – No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

5V NC NC NC NC NC 12V BVPP BVCC BVCC BVCC NC OC

3.3V

Figure 6. TPS2206 Terminal Assignments

TPS2206

12V 5V

3.3V

RESET RESET

AVPP

AVCC AVCC

AVCC

V V V V

PP1 PP2 CC CC

PC Card

PCMCIA

Controller

Serial Interface

BVPP

BVCC BVCC BVCC

Figure 7. TPS2206 Typical Application

V V V V

PP1 PP2 CC CC

PC Card

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PC CARD CONTROLLER

SCPS038 – AUGUST 1998

zoom video support

The ZV port on the PCI1251A provides an internally buffered 16-bit ZV PC Card data path. This internal routing is programmed through the multimedia control register. Figure 8 shows the zoom video subsystem implemented in the PCI1251A and details the bit functions found in the multimedia control register.

An output port (PORTSEL) is always selected. The PCI1251A defaults to socket 0 (see the multimedia control register on page 59). When ZVOUTEN is asserted, the zoom video output terminals are enabled to allow the PCI1251A to route the zoom video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled in the multimedia control register. When the PORTSEL maps to a card port that is disabled (ZVEN0 or ZVEN1) then the zoom video port is driven low; that is, no data is transmitted.

Zoom Video Subsystem

PC Card

Socket 0

PC Card

Socket 1

Card Output Enable

Logic

Card Output Enable

Logic

PC Card Interface

ZVEN0

ZVOUTEN

ZVSTAT (see Note A)

VGA

PORTSEL

Zoom Video

Port

ZVEN1

NOTES: A. ZVSTAT must be enabled through the GPIO control register.

Figure 8. Zoom Video Subsystem

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SPKROUT usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 pin becomes SPKR applications. SPKR

passes a TTL-level digital audio signal to the PCI1251A. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the two PC Card sockets are XORed in the PCI1251A to produce SPKROUT. Figure 9 shows the SPKROUT connection.

Bit 1, Card Control Register (offset 91h)

Card A SPKROUT Enable

Card A SPKR

Bit 1, Card Control Register (offset 91h)

Card B SPKROUT Enable

Card B SPKR

Figure 9. SPKROUT Connection to Speaker Driver

. This terminal, referred to as CAUDIO, is also used in CardBus

SPKROUT

Card A SPKROUT Enable Card B SPKROUT Enable

Speaker

Driver

The SPKROUT signal is typically driven only by modem PC Cards. To verify SPKROUT on the PCI1251A, a sample circuit was constructed, and this simplified schematic is shown in Figure 10.

NOTE:

Earlier versions of the PC Card controller multiplexed SUSPEND/SPKROUT on the same pin, which meant that a pullup resistor was needed to differentiate the signals. Because the PCI1251A does not multiplex this or any other function on SPKROUT, this terminal does not require a pullup resistor.

SPKROUT

3 7 2

+ –

LM386

Speaker

Figure 10. Simplified Test Schematic

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Reserved

Page

Reserved

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

LED socket activity indicators

Socket activity LEDs provided indicate when a PC Card is being accessed. The LED signals are multiplexed with general-purpose inputs and outputs (GPIOs), and the default for these terminals is GPI. When configured for LED outputs, these terminals output an active high signal to indicate socket activity . LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity.

The LED signal is active high and is driven for 64-ms periods. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 1 1 can be implemented to provide LED signaling, and the board designer can implement the circuit that best fits the application.

As indicated, the LED signals are driven for 64 ms, and this is accomplished by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when either SUSPEND

If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), the LED signals remain driven.

is asserted or when the PCI clock is stopped per the CLKRUN protocol.

Current Limiting

R ≈ 500 Ω

PCI1251A

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

LED

Figure 11. Two Sample LED Circuits

PC Card16 DMA support

The PCI1251A supports both PC/PCI (centralized) DMA and a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. The DDMA register configuration is provided in Table 20.

Table 20. Distributed DMA Registers

TYPE REGISTER NAME

R W R W R N/A W Mode R Multichannel W Mask

Current address 00h

Base address

Current count 04h

Base count

N/A Status 08h

Request Command

N/A

Master clear

BASE ADDRESS

OFFSET

DMA

0Ch

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CardBus socket registers

The PCI1251A has socket registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge specification. These CardBus socket registers are listed in Table 21 below.

Table 21. CardBus Socket Registers

Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch

Socket power management 20h

programmable interrupt subsystem

Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1251A. The PCI1251A provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1251A is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required.

The PCI1251A detects PC Card interrupts and events at the PC Card interface and notifies the host controller via one of several interrupt signaling protocols. T o simplify the discussion of interrupts in the PCI1251A, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts.

The method by which any type of PCI1251A interrupt is communicated to the host interrupt controller varies from system to system. The PCI1251A offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. Traditional ISA IRQ signaling is provided through eight IRQMUX terminals. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow.

PC Card functional and CSC interrupts

PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards.

Card status change-type interrupts are defined as events at the PC Card interface that are detected by the PCI1251A and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.

Table 22 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are 16-bit memory card, 16-bit I/O card, and CardBus cards. Note that functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type.

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CSC

memory

PCI1251A GFN/GJG

PC CARD CONTROLLER

PC Card functional and CSC interrupts (continued)

Table 22. PC Card Interrupt Events and Description

CARD TYPE EVENT TYPE SIGNAL DESCRIPTION

A transition on BVD1 indicates a change in the PC Card battery conditions.

A transition on BVD2 indicates a change in the PC Card battery conditions.

A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data.

The assertion of STSCHG indicates a status change on the PC Card.

The assertion of IREQ indicates an interrupt request from the PC Card.

The assertion of CSTSCHG indicates a status change on the PC Card.

The assertion of CINT indicates an interrupt request from the PC Card.

An interrupt is generated when a PC Card power-up cycle has completed.

A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit CardBus PC Card.

An interrupt is generated when a PC Card power-up cycle has completed.

16-bit

16-bit I/O

CardBus

All PC Cards

Battery conditions

(BVD1, BVD2)

Wait states

(READY)

Change in card status (STSCHG

Interrupt request

Change in card status

(CSTSCHG)

Interrupt request

Power cycle

complete

Card insertion

or removal

Power cycle

complete

(IREQ

(CINT

)

BVD1(STSCHG)//CSTSCHG

BVD2(SPKR)//CAUDIO

CSC READY(IREQ)//CINT

CSC BVD1(STSCHG)//CSTSCHG

Functional READY(IREQ)//CINT

CSC BVD1(STSCHG)//CSTSCHG

Functional READY(IREQ)//CINT

CSC N/A

CSC

CSC N/A

CD1//CCD1,

CD2

//CCD2

SCPS038 – AUGUST 1998

The naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well as CardBus. For example, READY(IREQ cards, and CINT

for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name

)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O

second, enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI1251A when an

insertion event occurs and the host requests that the socket V

and VPP be powered. Upon completion of this

power-up sequence, the PCI1251A interrupt scheme can be used to notify the host system (see Table 23), denoted by the power cycle complete event. This interrupt source is considered a PCI1251A internal event, because it depends on the completion of applying power to the socket.

interrupt masks and flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 23 by setting the appropriate bits in the PCI1251A. By individually masking the interrupt sources listed, software can control those events that cause a PCI1251A interrupt. Host software has some control over the system interrupt the PCI1251A asserts by programming the appropriate routing registers. The PCI1251A allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. A discussion of interrupt routing is somewhat specific to the interrupt signaling method used, and is discussed in more detail in the following sections.

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CardBus

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interrupt masks and flags (continued)

When an interrupt is signaled by the PCI1251A, the interrupt service routine must determine which of the events in Table 23 caused the interrupt. Internal registers in the PCI1251A provide flags that report which interrupt source was the cause of the interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.

T able 23 details the registers and bits associated with masking and reporting potential interrupts. All interrupts, except the functional PC Card interrupts, can be masked. An interrupt status flag is available for all types of interrupts.

Table 23. Interrupt Mask and Flag Registers

CARD TYPE EVENT MASK FLAG

16-bit memory

All 16-bit PC Cards

Battery conditions

(BVD1, BVD2)

Wait states

(READY)

Change in card status

(STSCHG

Interrupt request

Power cycle complete Change in card status

(CSTSCHG)

Interrupt request

Power cycle complete

Card insertion or

removal

(IREQ

(CINT

)

ExCA offset 05h/45h/805h

bits 1 and 0

ExCA offset 05h/45h/805h

bit 2

ExCA offset 05h/45h/805h

bit 0

Always enabled

ExCA offset 05h/45h/805h

bit 3

Socket mask

bit 0

Always enabled

Socket mask

bit 3

Socket mask

bits 2 and 1

ExCA offset 04h/44h/804h

bits 1 and 0

ExCA offset 04h/44h/804h

bit 2

ExCA offset 04h/44h/804h

bit 0

PCI configuration offset 91h

bit 0

ExCA offset 04h/44h/804h

bit 3

Socket event

bit 0

PCI configuration offset 91h

bit 0

Socket event

bit 3

Socket event

bits 2 and 1

Notice that there is not a mask bit to stop the PCI1251A from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization.

V arious methods of clearing the interrupt flag bits are listed in T able 23. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared by two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the

read

method.

flag cleared on

The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning.

legacy interrupt multiplexer

The IRQ multiplexer implemented in the PCI1251A provides a mechanism to route the IRQMUX signals to any of the 15 legacy IRQ signals. IRQMUX7–IRQMUX6 share the PC/PCI DMA terminals and take precedence when routed. The other six IRQMUX signals (IRQMUX5–IRQMUX0) are available in all platforms. To use the IRQMUX interrupt signaling, software must program the device control register (PCI offset 92h) to select the legacy IRQ signaling scheme.

The IRQMUX functionality describing PCREQ/IRQMUX7 is shown in Figure 12.

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legacy interrupt multiplexer (continued)

System Control Register (Bit 3):

When bit 3 = 0 EEPROM SCL is routed on IRQMUX7 When bit 3 = 1 PCREQ is routed on IRQMUX7

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

EEPROM SCL

PCREQ

0000

0001

  

0010

  

1111

IRQMUX Routing Register

PCREQ/IRQMUX7/SCL

Figure 12. Interrupt Mux Functionality – Example of IRQMUX7 Routing

If parallel ISA IRQs are selected in the device control register, then the IRQMUX routing register (PCI of fset 8Ch) must be programmed with the associated ISA IRQ connections. The PCI1251A supports up to eight parallel ISA IRQ signal connections (IRQMUX7–IRQMUX0). Figure 13 is an example of PCI1251A IRQ implementation that provides eight ISA interrupts. The system In this example cannot support PC/PCI DMA because all eight ISA IRQs are used. In this example, IRQMUX7 and IRQMUX6 are used to signal ISA IRQs and are not available for PC/PCI DMA. For systems not using all eight IRQs, PC/PCI DMA can be implemented and can coexist with ISA IRQs by using IRQMUX6 and IRQMUX7 for PC/PCI DMA; that is, legacy IRQs and PC/PCI DMA implementation are not mutually exclusive. However, if the IRQMUX registers are programmed to use IRQMUX7–6, they override PC/PCI DMA.

PCI1251A PCI

IRQMUX0 IRQMUX1 IRQMUX2 IRQMUX3 IRQMUX4 IRQMUX5 IRQMUX6 IRQMUX7

IRQ3 IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15

Figure 13. IRQ Implementation

Software is responsible for programming the IRQMUX routing register to reflect the IRQ configuration shown in Figure 13. In this example, programming is accomplished by writing a doubleword of data (FCBA9543h) to the PCI1251A IRQMUX routing register, PCI of fset 8Ch. In this example (FCBA9543h), F corresponds to IRQ15, C to IRQ12, B to IRQ11, A to IRQ10, 9 to IRQ9, 5 to IRQ5, 4 to IRQ4, and 3 to IRQ3.

The IRQMUX routing register is shared between the two PCI1251A functions, and only one write to function 0 or function 1 is necessary to configure the IRQMUX signals.

using parallel PCI interrupts

Parallel PCI interrupts are available when in: parallel PCI interrupt mode, IRQMUX signaling mode, or when IRQs are serialized with the IRQSER protocol. The PCI interrupt signaling is dependent on the interrupt mode. The interrupt mode is selected via the device control register (92h). The IRQSER/INTB

pin signals INTB when

one of the parallel interrupt modes is selected via bits 2–1 in the device control register (92h).

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using parallel PCI interrupts (continued)

PCI INTB routing register (8Ch). PCI INTA

is also available on the IRQMUX0 terminal by programming bits 3–0 to 0001b. See the IRQMUX

is available on the GPIO3 terminal by programming bits 7–6 in the GPIO3

control register (8Bh) to 00b. The value read from the interrupt pin register is card slot dependent. The value read also depends on the

interrupt INTRTIE bit in the system control register and the signaling mode selected through the device control register. When the INTRTIE bit is set, this register reads 0x01 (INTA) for both functions. The PCI1251A defaults to signaling PCI and IRQ interrupts through IRQSER serial interrupt terminal. Refer to Table 24 for a complete description of the register contents.

Table 24. Interrupt Pin Register Cross Reference

INTERRUPT SIGNALING MODE

Parallel PCI interrupts only 0 0x01 (INTA) 0x02 (INTB) Parallel IRQ and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB) IRQ serialized (IRQSER) and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB)

IRQ and PCI serialized (IRQSER) interrupts (default) 0 0x01 (INTA) 0x02 (INTB)

Parallel PCI interrupts only 1 0x01 (INTA) 0x01 (INTA) Parallel IRQ and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA)

IRQ and PCI serialized (IRQSER) interrupts (default) 1 0x01 (INTA) 0x01 (INTA)

INTRTIE

BIT

INTPIN

FUNCTION 0

INTPIN

FUNCTION 1

power management overview

TI has expended great effort to provide a high-performance device with low power consumption. In addition to the low-power CMOS technology process used for the PCI1251A, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section.

PCI CLKRUN

The PCI CLKRUN Since some chipsets do not implement CLKRUN alternate power savings features are provided. If CLKRUN be tied low. CLKRUN

protocol

feature is the primary method of power management on the PCI bus side of the PCI1251A.

, this is not always available to the system designer, and

is not implemented the CLKRUN terminal should

is enabled by default using bit 1 (KEEPCLK) in the system control register (80h).

CardBus PC Card power management

The PCI1251A implements its own card power-management engine that can be used to turn off the CCLK at a socket when there is no activity to the CardBus PC Card. The CCLK can also be configured as divide by 16 instead of

stopped

. The clock run protocol is followed on the CardBus interface to control this

clock management.

PCI power management (PCIPM)

The PCI power-management (PCIPM) specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software-visible power-management states that result in varying levels of power savings.

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PCI power management (PCIPM) (continued)

The four power-management states of PCI functions are:

D0 – Fully-on state

D1 and D2 – Intermediate states

D3 – Off state

Similarly , bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the originating bridge device.

For the operating system (OS) to power manage the device power states on the PCI bus, the PCI function should support four power-management operations. These are capabilities reporting, power status reporting, setting the power state, and system wake up. The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1 in the capabilities list bit in the PCI Status register (bit 4) and providing access to a capabilities list.

The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1251A, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, the next item pointer should be set to 0. The registers following the next item pointer are specific to the function’s capability . The PCIPM capability implement the register block outlined in Table 25.

Table 25. Power-Management Registers

Power-management capabilities Next item pointer Capability ID 0

Data PMCSR bridge support extensions Power-management control status (CSR) 4

The PMC register is a static read-only register that provides information on the capabilities of the function related to power management. The PMCSR register enables control of power-management states and enables/ monitors power-management events. The data register is an optional register that provides state-dependent power measurements, such as power consumption or heat dissipation.

suspend mode

The SUSPEND PCI1251A. However, additional functionality has been defined for SUSPEND power-management options.

SUSPEND potentially save power while in an idle state; however, it requires substantial design ef fort to implement. Some issues to consider are:

What if cards are present in the sockets?

What if the cards in the sockets are powered?

How to pass CSC (insertion/removal) events?

Even without the PCI clock to the PCI1251A core, there are asynchronous-type functions (such as RI_OUT that can pass CSC events, wake-up events, etc., back to the system. If a system designer chooses to not pass card removal events through to the system, then the PCI1251A would not be able to power down the empty socket without the power switch clock (CLOCK) generated externally . Refer to the P on page 27 for details. Figure 14 is a functional implementation diagram.

signal is provided for backward compatibility , and gates the PCI reset (PRST) signal from the

to provide additional

provides a mechanism to gate the PCLK from the PCI1251A, as well as gate PRST. This can

C power switch interface

)

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suspend mode (continued)

PRST

SUSPEND

GNT

PCLK

Figure 14. SUSPEND Functional Implementation

requirements for suspend mode

The PCI bus must not be parked on the PCI1251A when SUSPEND SUSPEND reset.

The GPIOs, IRQMUX signals, and RI_OUT appropriate PCI1251A registers.

ring indicate

The RI_OUT go into a suspended mode and wake up on modem rings and other card events. TI has designed in flexibility to this signal to fit wide platform requirements. RI_OUT following conditions:

being asserted by placing the REQ pin in a high impedance state and gates the internal clock and

signals are active during SUSPEND unless they are disabled in the

output is an important feature in power management and is basically used so that a system can

on the PCI1251A can be asserted under any of the

A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call.

is asserted. The PCI1251A responds to

PCI1251A

Core

A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.

A CSC event occurs, such as insertion/removal of cards, battery voltage levels.

CSTSCHG from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT function; however, it does not show the masking of CSC events (see a detailed description of CSC interrupt masks and flags).

RI_OUT In PCI power management systems the PME power-management control/status register (A4h) and setting RIMUX 80h to 1.

In addition to bit 0 in the system control register, the RIENB bit (bit 7) in the card control register (91h) must be set to enable RI_OUT

events are enabled separately. Figure 15 shows various enable bits for the PCI1251A RI_OUT

interrupt masks and flags

is multiplexed with PME on the same terminal. The default is for RI_OUT to be signaled on this terminal.

signal should be enabled by setting bit 8 (PME_EN) in the

, on page 33, for

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ring indicate (continued)

PC Card

Socket 0

PC Card

Socket 1

Card

I/F

Card

I/F

RI_OUT Function

CSTSMASK

CSC

RINGEN

CDRESUME

CSC

CSTSMASK

CSC

RINGEN

CDRESUME

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

RIENB

RI_OUT

CSC

Figure 15. RI_OUT Functional Diagram

Routing of CSC events to RI_OUT

is enabled on a per-socket basis, and is programmed by the RIENB bit in

the card control register on page 66. This bit is socket dependent (not shared), as shown in Figure 15. Ring indicate (RI) from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the interrupt

and general control register on page 82. This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket.

The CBWAKE signaling to RI_OUT

is enabled through the same mask as the CSC event for CSTSCHG. The mask bit, CSTSMASK, is programmed through the socket mask register (page 100) in the CardBus socket registers.

PC Card controller programming model

This section describes the PCI1251A PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1251A function. As noted, some bits are global in nature and should be accessed only through function 0.

PCI configuration registers (functions 0 and 1)

The PCI1251A is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The configuration header is compliant with the PCI specification as a CardBus bridge header, and is PC99 compliant as well. Table 26 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers.

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Table 26. PCI Configuration Registers (Functions 0 and 1)

Device ID Vendor ID 00h

Status Command 04h

Class code Revision ID 08h

BIST Header type Latency timer Cache line size 0Ch

CardBus socket/ExCA base address 10h

Secondary status Reserved Capability pointer 14h

CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h

Memory base register 0 1Ch

Memory limit register 0 20h

Memory base register 1 24h

Memory limit register 1 28h

I/O base register 0 2Ch

I/O limit register 0 30h

I/O base register 1 34h

I/O limit register 1 38h

Bridge control Interrupt pin Interrupt line 3Ch

Subsystem ID Subsystem vendor ID 40h

PC Card 16-bit I/F legacy-mode base address 44h

Reserved 48h–7Fh

System control 80h

Reserved Reserved General status Multimedia control 84h

GPIO3 control GPIO2 control GPIO1 control GPIO0 control 88h

IRQMUX routing 8Ch

Diagnostic Device control Card control Retry status 90h

Socket DMA register 0 94h Socket DMA register 1 98h

Reserved 9Ah–9Fh

Power-management capabilities Next-item pointer Capability ID A0h

Data (reserved)

PMCSR Bridge Support

Extensions

Power-management control/status A4h

vendor ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

Register: Vendor ID Type: Read only Offset: 00h (functions 0, 1) Default: 104Ch Description: This 16-bit read-only register contains a value allocated by the PCI SIG (special interest

group) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch.

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device ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 1 0 1

Register: Device ID Type: Read only Offset: 02h (functions 0, 1) Default: AC1Dh Description: This 16-bit read-only register contains a value assigned to the PCI1251A by TI. The device

identification for the PCI1251A is AC1D.

command register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R R R R/W R R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Command Type: Read only, read/write (see individual bit descriptions) Offset: 04h Default: 0000h Description: The command register provides control over the PCI1251A interface to the PCI bus. All bit

functions adhere to the definitions in PCI Local Bus Specification 2.2. None of the bit functions in this register are shared between the two PCI1251A PCI functions. Two command registers exist in the PCI1251A, one for each function. Software must manipulate the two PCI1251A functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the two functions, and these control bits appear separately according to their software function.

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Table 27. Command Register

BIT SIGNAL TYPE FUNCTION

15–10 RSVD R Reserved. Bits 15–10 are read only and return 0s when read. Writes have no effect.

9 FBB_EN R

8 SERR_EN R/W

7 ADSTPNG R

6 PERR_EN R/W

5 VGA_SNP R

4 MWI_EN R

3 SP_CYCL R

2 BUSMSTR R/W

1 MEM_EN R/W

0 IO_EN R/W

Fast back-to-back enable. The PCI251 does not generate fast back-to-back transactions; therefore, bit 9 is read only and returns 0s when read.

System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set for the PCI1251A to report address parity errors.

Address/data stepping control. The PCI1251A does not support address/data stepping, and bit 7 is hardwired to 0. Writes to this bit have no effect.

Parity error response enable. Bit 6 controls the PCI1251A’ s response to parity errors through PERR. Data parity errors are indicated by asserting PERR SERR

VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette registers. The PCI1251A does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit 5 is read only and returns 0 when read. Writes to this bit have no effect.

Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and Invalidate commands. The PCI1251A controller does not support memory write and invalidate commands; it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 is read only and returns 0 when read. Writes to this bit have no effect.

Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1251A does not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 is read only and returns 0 when read. Writes to this bit have no effect.

Bus master control. Bit 2 controls whether or not the PCI1251A can act as a PCI bus initiator (master). The PCI1251A can take control of the PCI bus only when this bit is set.

Memory space enable. Bit 1 controls whether or not the PCI1251A can claim cycles in PCI memory space.

I/O space control. Bit 0 controls whether or not the PCI1251A can claim cycles in PCI I/O space.

0 = Disable SERR 1 = Enable SERR

0 = PCI1251A ignores detected parity error (default). 1 = PCI1251A responds to detected parity errors.

0 = Disables the PCI1251A’s ability to generate PCI bus accesses (default). 1 = Enables the PCI1251A’s ability to generate PCI bus accesses.

0 = Disables the PCI1251A’s response to memory space accesses (default). 1 = Enables the PCI1251A’s response to memory space accesses.

0 = Disables the PCI1251A from responding to I/O space accesses (default). 1 = Enables the PCI1251A to respond to I/O space accesses.

output driver (default).

output driver.

, whereas address parity errors are indicated by asserting

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status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Status Type R/W R/W R/W R/W R/W R R R/W R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Register: Status Type: Read only, read/write (see individual bit descriptions) Offset: 06h (functions 0, 1) Default: 0210h Description: The status register provides device information to the host system. Bits in this register may be

read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Local Bus Specification 2.2. PCI bus status is shown through each function (see Table 28).

Table 28. Status Register

BIT SIGNAL TYPE FUNCTION

15 PAR_ERR R/W

14 SYS_ERR R/W

13 MABORT R/W

12 TABT_REC R/W

11 TABT_SIG R/W

10–9 PCI_SPEED R

8 DAT APAR R/W

7 FBB_CAP R

6 UDF R

5 66_CAP R

4 CAP_LST R

3–0 RSVD R Reserved. Bits 3–0 return 0s when read.

Detected parity error. Bit 15 is set when a parity error is detected (either address or data). W rite a 1 to clear this bit.

Signaled system error. Bit 14 is set when SERR is enabled and the PCI1251A signals a system error to the host. Write a 1 to clear this bit.

Received master abort. Bit 13 is set when a cycle initiated by the PCI1251A on the PCI bus has been terminated by a master abort. Write a 1 to clear this bit.

Received target abort. Bit 12 is set when a cycle initiated by the PCI1251A on the PCI bus was terminated by a target abort. Write a 1 to clear this bit.

Signaled target abort. Bit 1 1 is set by the PCI1251A when it terminates a transaction on the PCI bus with a target abort. Write a 1 to clear this bit.

DEVSEL timing. These read-only bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1251A asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.

Data parity error detected. Write a 1 to clear this bit.

Fast back-to-back capable. The PCI1251A cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0.

User-definable feature support. The PCI1251A does not support the user-definable features; thus, bit 6 is hardwired to 0.

66-MHz capable. The PCI1251A operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

Capabilities list. Bit 4 is read only and returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function.

0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred, and the following conditions were met:

a. PERR b. The PCI1251A was the bus master during the data parity error. c. The parity error response bit is set in the command.

was asserted by any PCI device including the PCI1251A.

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revision ID register

Bit 7 6 5 4 3 2 1 0 Name Revision ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1

Register: Revision ID Type: Read only Offset: 08h (functions 0, 1) Default: 01h Description: This read-only register indicates the silicon revision of the PCI1251A. This data sheet reflects

the PCI1251A revision is 01h silicon.

PCI class code register

Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code

Base class Sub class Programming interface

Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

Register: PCI Class code Type: Read only Offset: 09h (functions 0, 1) Default: 060700h Description: The class code register recognizes the PCI1251A functions 0 and 1 as a bridge device (06h),

and CardBus bridge device (07h) with a 00h programming interface.

cache line size register

Bit 7 6 5 4 3 2 1 0 Name Cache line size Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Cache line size Type: Read/write Offset: 0Ch (functions 0, 1) Default: 00h Description: The cache line size register is programmed by host software to indicate the system cache line

size.

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latency timer register

Bit 7 6 5 4 3 2 1 0 Name Latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Latency timer Type: Read/write Offset: 0Dh Default: 00h Description: The latency timer register specifies the latency timer for the PCI1251A in units of PCI clock

cycles. When the PCI1251A is a PCI bus initiator and asserts FRAME begins counting from zero. If the latency timer expires before the PCI1251A transaction has terminated, the PCI1251A terminates the transaction when its GNT is deasserted.

header type register

Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 1 0 0 0 0 0 1 0

, the latency timer

Register: Header type Type: Read only Offset: 0Eh (functions 0, 1) Default: 82h Description: This read-only register returns 82h when read, indicating that the PCI1251A functions 0 and 1

configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h–FFh is user-definable extension registers.

BIST register

Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: BIST Type: Read only Offset: 0Fh (functions 0, 1) Default: 00h Description: Because the PCI1251A does not support a built-in self-test (BIST), this register is read only

and returns the value of 00h when read. This register is read only, returning 0s for the two PCI1251A functions.

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CardBus socket registers/ExCA base-address register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: CardBus socket/ExCA base address Type: Read only, read/write Offset: 10h Default: 0000 0000h Description: The CardBus socket registers/ExCA base-address register is programmed with a base

address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4K-byte boundary. Bits 11–0 are read only, returning 0s when read. When software writes all 1s to this register, the value readback is FFFF F000h, indicating that at least 4K-bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. This register is not shared by functions 0 and 1, mapping each socket control separately.

capability pointer register

Bit 7 6 5 4 3 2 1 0 Name Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0

Register: Capability pointer Type: Read only Offset: 14h Default: A0h Description: The capability pointer register provides a pointer into the PCI configuration header where the

PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read only and returns A0h when read.

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secondary status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Secondary status Type R/W R/W R/W R/W R/W R R R/W R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Register: Secondary status Type: Read only, read/write (see individual bit descriptions) Offset: 16h Default: 0200h Description: The secondary status register (see Table 29) is compatible with the PCI-to-PCI bridge

secondary status register and indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (offset 06h), and status bits are cleared by writing a 1. on a per-socket basis.

Table 29. Secondary Status Register

BIT SIGNAL TYPE FUNCTION

15 CBPARITY R/W

14 CBSERR R/W

13 CBMABORT R/W

12 REC_CBTA R/W

11 SIG_CBTA R/W

10–9 CB_SPEED R

8 CB_DP AR R/W

7 CBFBB_CAP R

6 CB_UDF R

5 CB66MHZ R

4–0 RSVD R Reserved. Bits 4–0 return 0s when read.

Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). W rite a 1 to clear this bit.

Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1251A does not assert CSERR

Received master abort. Bit 13 is set when a cycle initiated by the PCI1251A on the CardBus bus has been terminated by a master abort. Write a 1 to clear this bit.

Received target abort. Bit 12 is set when a cycle initiated by the PCI1251A on the CardBus bus is terminated by a target abort. Write a 1 to clear this bit.

Signaled target abort. Bit 1 1 is set by the PCI1251A when it terminates a transaction on the CardBus bus with a target abort. Write a 1 to clear this bit.

CDEVSEL timing. These read-only bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the PCI1251A asserts CB_SPEED at a medium speed.

CardBus data parity error detected. Write a 1 to clear this bit.

Fast back-to-back capable. The PCI1251A cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0.

User-definable feature support. The PCI1251A does not support the user-definable features; thus, bit 6 is hardwired to 0.

66-MHz capable. The PCI1251A CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

This register is not shared by the two socket functions and is accessed

. Write a 1 to clear this bit.

0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred and the following conditions were met:

a. CPERR b. The PCI1251A was the bus master during the data parity error. c. The parity error response bit is set in the bridge control.

was asserted on the CardBus interface.

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PCI bus number register

Bit 7 6 5 4 3 2 1 0 Name PCI bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: PCI bus number Type: Read/write Offset: 18h (functions 0, 1) Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the

PCI bus to which the PCI1251A is connected. The PCI1251A uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

CardBus bus number register

Bit 7 6 5 4 3 2 1 0 Name CardBus bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: CardBus bus number Type: Read/write Offset: 19h Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the

CardBus bus to which the PCI1251A is connected. The PCI1251A uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI1251A controller function.

subordinate bus number register

Bit 7 6 5 4 3 2 1 0 Name Subordinate bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Subordinate bus number Type: Read/write Offset: 1Ah Default: 00h Description: This read/write register is programmed by the host system to indicate the highest-numbered

bus below the CardBus bus. The PCI1251A uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function.

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CardBus latency timer register

Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: CardBus latency timer Type: Read/write Offset: 1Bh (functions 0, 1) Default: 00h Description: This read/write register is programmed by the host system to specify the latency timer for the

PCI1251A CardBus interface in units of CCLK cycles. When the PCI1251A is a CardBus initiator and asserts CFRAME expires before the PCI1251A transaction has terminated, then the PCI1251A terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed.

memory base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

, the CardBus latency timer begins counting. If the latency timer

Register: Memory base registers 0, 1 Type: Read only, read/write Offset: 1 Ch, 24h Default: 0000 0000h Description: The Memory base registers indicate the lower address of a PCI memory address range.

These registers are used by the PCI1251A to determine when to forward a memory transaction to the CardBus bus, and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write which allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11–0 are read only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1251A to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K-bytes of memory to CardBus).

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memory limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Memory limit registers 0, 1 Type: Read only, read/write Offset: 20h, 24h Default: 0000 0000h Description: The Memory limit registers indicate the upper address of a PCI memory address range. These

registers are used by the PCI1251A to determine when to forward a memory transaction to the CardBus bus, and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11–0 are read only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1251A to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K-bytes of memory to CardBus).

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I/O base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O base registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O base registers 0, 1 Type: Read only, read/write Offset: 2Ch, 34h Default: 0000 0000h Description: The I/O base registers indicate the lower address of a PCI I/O address range. These registers

are used by the PCI1251A to determine when to forward an I/O transaction to the CardBus bus, and when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K-byte page, and the upper 16 bits (31–16) are all 0, which locates this 64K-byte page in the first page of the 32-bit PCI I/O address space. Bits 31–16 and bits 1–0 are read only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary in the first 64 kilobyte page of PCI I/O address space. These I/O windows are enabled when either the I/O base register or the I/O limit register are nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus.

NOTE:

Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.

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I/O limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O limit registers 0, 1 Type: Read only, read/write Offset: 30h, 38h Default: 0000 0000h Description: The I/O limit registers indicate the upper address of a PCI I/O address range. These registers

are used by the PCI1251A to determine when to forward an I/O transaction to the CardBus bus, and when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64K-byte page, and the upper 16 bits are a page register that locates this 64K-byte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64K-byte page (indicated by bits 31–16 of the appropriate I/O base ) on doubleword boundaries.

Bits 31–16 are read only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are read only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to read-only bits have no effect. The PCI1251A assumes that the lower two bits of the limit address are 1s.

These I/O windows are enabled when either the I/O base register or the I/O limit register are nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus).

NOTE:

Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.

interrupt line register

Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1

Register: Interrupt line Type: Read/write Offset: 3Ch Default: FFh Description: The interrupt line register is read/write and is used to communicate interrupt line routing

information. This register is not used by the PCI1251A, because there are many programmable interrupt signaling options. This register is considered reserved; however, host software may read and write to this register. Each PCI1251A function 0 and 1 has an interrupt line register.

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interrupt pin register

Bit 7 6 5 4 3 2 1 0 Name Interrupt pin Type R R R R R R R R Default 1 1 1 1 1 1 1 1

Register: Interrupt pin Type: Read only Offset: 3Dh Default: Depends on the interrupt signaling mode Description: The value read from the interrupt pin register is function dependent and depends on the

interrupt INTRTIE bit in the system control register and the signaling mode selected through the device control register. When the INTRTIE bit is set, this register reads 0x01 (INTA) for both functions. The PCI1251A defaults to signaling PCI and IRQ interrupts through IRQSER serial interrupt terminal. Refer to Table 30 for a complete description of the register contents.

Table 30. Interrupt Pin Register Cross Reference

INTERRUPT SIGNALING MODE

Parallel PCI interrupts only 0 0x01 (INTA) 0x02 (INTB) Parallel IRQ and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB) IRQ serialized (IRQSER) and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB)

IRQ and PCI serialized (IRQSER) interrupts (default) 0 0x01 (INTA) 0x02 (INTB)

Parallel PCI interrupts only 1 0x01 (INTA) 0x01 (INTA) Parallel IRQ and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA)

IRQ and PCI serialized (IRQSER) interrupts (default) 1 0x01 (INTA) 0x01 (INTA)

INTRTIE

BIT

INTPIN

FUNCTION 0

INTPIN

FUNCTION 1

bridge control register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Bridge control Type R R R R R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W Default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0

Register: Bridge control Type: Read only, read/write (see individual bit descriptions) Offset: 3Eh (functions 0, 1) Default: 0340h Description: The bridge control register provides control over various PCI1251A bridging functions. Some

bits in this register are global and should be accessed only through function 0. Refer to Table 31 for a complete description of the register contents.

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Table 31. Bridge Control Register

BIT SIGNAL TYPE FUNCTION

15–1 1 RSVD R Reserved. Bits 15–11 return 0s when read.

Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables

10 POSTEN R/W

9 PREFETCH1 R/W

8 PREFETCH0 R/W

7 INT_RT_EN R/W

6 CRST R/W

†

MABTMODE R/W

4 RSVD R Reserved. Bit 4 returns 0 when read. 3 VGAEN R/W

2 ISAEN R/W

1 CSERREN R/W

0 CPERREN R/W

†

This bit is global and should be accessed only through function 0.

posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles. Note that bursted write data can be posted, but various write transactions may not. Bit 10 is socket dependent and is not shared between functions 0 and 1.

Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. Bit 9 is encoded as:

Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is encoded as:

PCI interrupt – IREQ routing enable. Bit 7 is used to select whether PC Card functional interrupts are routed to PCI interrupts or the IRQ specified in the ExCA registers.

CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted by passing a PRST

Master abort mode. Bit 5 controls how the PCI1251A responds to a master abort when the PCI1251A is an initiator on the CardBus interface. This bit is common between each socket.

VGA enable. Bit 3 affects how the PCI1251A responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded.

ISA mode enable. Bit 2 affects how the PCI1251A passes I/O cycles within the 64K-byte ISA range. This bit is not common between sockets. When this bit is set, the PCI1251A does not forward the last 768 bytes of each 1K I/O range to CardBus.

CSERR enable. Bit 1 controls the response of the PCI1251A to CSERR signals on the CardBus bus. This bit is separate for each socket.

CardBus parity error response enable. Bit 0 controls the response of the PCI1251A to CardBus parity errors. This bit is separate for each socket.

0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default).

0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default).

0 = Functional interrupts routed to PCI interrupts (default) 1 = Functional interrupts routed by ExCA s

0 = CRST 1 = CRST

0 = Master aborts not reported (default) 1 = Signal target abort on PCI and SERR

0 = CSERR 1 = CSERR

0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR

assertion to CardBus. deasserted asserted (default)

is not forwarded to PCI SERR. is forwarded to PCI SERR.

(if enabled)

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subsystem vendor ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Subsystem vendor ID Type: Read only (read/write when bit 5 in the system control register is 0) Offset: 40h (functions 0, 1) Default: 0000h Description: The subsystem vendor ID register is used for system and option-card identification purposes,

and may be required for certain operating systems. This register is read only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read only. The default mode is read only.

subsystem ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Subsystem ID Type: Read only (read/write when bit 5 in the system control register is 0) Offset: 42h (functions 0, 1) Default: 0000h Description: The subsystem ID register is used for system and option-card identification purposes and may

be required for certain operating systems. This register is read only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read only. The default mode is read only.

If an EEPROM is present, the subsystem ID and subsystem vendor ID will be loaded from EEPROM after a reset.

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PC Card 16-bit I/F legacy-mode base address register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Register: PC Card 16-bit I/F legacy-mode base address Type: Read only, read/write (see individual bit descriptions) Offset: 44h (functions 0, 1) Default: 0000 0000h Description: The PCI1251A supports the index/data scheme of accessing the ExCA registers, which is

mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read only, returning 1 when read. As specified in the shared by functions 0 and 1. Refer to the ExCA register set description for register offsets.

PCI to PCMCIA CardBus Bridge Register Description

(Yenta), this register is

system control register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System control Type R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name System control Type R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0

Register: System control Type: Read only, read/write (see individual bit descriptions) Offset: 80h (functions 0, 1) Default: 0044 9060h Description: System-level initializations are performed through programming this doubleword register.

Some of the bits are global and should be written only through function 0. Refer to Table 32 for a complete description of the register contents.

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Table 32. System Control Register

BIT SIGNAL TYPE FUNCTION

Serialized PCI interrupt routing step. Bits 31–30 are used to configure the serialized PCI interrupt stream signaling, and accomplish an even distribution of interrupts signaled on the four PCI interrupt

†

31–30

28 RSVD R Reserved. Bit 28 is read only and returns 0 when read.

25 SMISTA TUS R/W

23 RSVD R Reserved

22 CBRSVD R/W

21 VCCPROT R/W

20 RSVD R/W Reserved. Bit 20 returns 0 when read.

19 CDREQEN R/W

18–16 CDMACHAN R/W

†

These bits are global and should be accessed only through function 0.

SER_STEP R/W

†

INTRTIE R/W

P2CCLK R/W

SMIROUTE R/W

SMIENB R/W

MRBURSTDN R/W

slots. Bits 31–30 are global to both PCI1251A functions.

Tie internal PCI interrupts. When this bit is set, the INT A and INTB signals are tied together internally and are signaled as INTA both PCI1251A functions.

P2C power switch clock. The PCI1251A defaults CLOCK as an input clock to control the serial interface and the internal state machine. Bit 27 can be set to enable the PCI1251A to generate and drive the CLOCK from the PCI clock. When in a SUSPEND PCI1251A to successfully power down sockets after card removal without indicating to the system the removal event.

SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket.

SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to bit 25 clears the status.

SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling is enabled and generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).

CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated.

VCC protection enable. Bit 21 is socket dependent.

PC/PCI DMA card enable. When bit 19 is set, the PCI1251A allows 16-bit PC Cards to request PC/PCI DMA using the DREQ

CDMACHANPC/PCI DMA channel assignment. Bits 18–16 are encoded as:

Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst downstream.

00 = INTA 01 = INTA 10 = INTA 11 = INTA

0 = INTA 1 = INTA

0 = CLOCK provided externally, input to PCI1251A (default) 1 = CLOCK generated by PCI clock and driven by PCI1251A

0 = PC Card power change interrupts routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes.

0= SMI interrupt signaled 1 = SMI interrupt not signaled

0 = SMI interrupt mode is disabled (default). 1 = SMI interrupt mode is enabled.

0 = 3-state CardBus RSVD 1 = Drive Cardbus RSVD low (default)

0 = VCC protection enabled for 16-bit cards (default) 1 = VCC protection disabled for 16-bit cards

0 = Ignore DREQ 1 = Signal DMA request on DREQ

0–3 = 8-bit DMA channels 4 = PCI master; not used (default). 5–7 = 16-bit DMA channels

0 = MRBURSTDN downstream is disabled. 1 = MRBURSTDN downstream is enabled (default).

/INTB signal in INTA/INTB IRQSER slots (default) /INTB signal in INTB/INTC IRQSER slots /INTB signal in INTC/INTD IRQSER slots /INTB signal in INTD/INTA IRQSER slots

. INTA can then be shifted by using the SER_STEP bits. This bit is global to

and INTB are not tied together internally (default). and INTB are tied together internally.

signaling. DREQ is selected through the socket DMA register 0.

signaling from PC Cards (default)

PCI1251A GFN/GJG

PC CARD CONTROLLER

SCPS038 – AUGUST 1998

state, however, CLOCK must be input to the

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Table 32. System Control Register (Continued)

BIT SIGNAL TYPE FUNCTION

Memory read burst enable upstream. When bit 14 is set, the PCI1251A allows memory read

†

These bits are global and should be accessed only through function 0.

MRBURSTUP R/W

13 SOCACTIVE R

12 RSVD R Reserved. Bit 12 is read only and returns 1 when read. This is the power-rail bit in functions 0 and 1.

†

PWRSTREAM R

†

DELAYUP R

†

DELAYDOWN R

8 INTERROGATE R

7 RSVD R Reserved. Bit 7 is read only and returns 0 when read.

†

PWRSAVINGS R/W

†

2 RSVD R Reserved

SUBSYSRW R/W

†

CB_DPAR R/W

CDMA_EN R/W

KEEPCLK R/W

RIMUX R/W

transactions to burst upstream.

Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card, and is cleared upon read of this status bit. This bit is socket dependent.

Power stream in progress status bit. When set high, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. When this bit is clear, it indicates that the power stream is complete.

Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has expired.

Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay has expired.

Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. This bit is socket dependent.

Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock, the applicable CB state machine will not be clocked.

Subsystem ID (SSID), subsystem vendor ID (SSVID), ExCA ID, and revision register read/write enable. Bit 5 is shared by functions 0 and 1.

CardBus data parity SERR signaling enable

PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set, and disables IRQMUX7 and IRQMUX6 signaling.

Keep clock. This bit works with PCI and CB CLKRUN protocols.

RI_OUT/PME multiplex enable.

0 = MRBURSTUP upstream is disabled (default). 1 = MRBURSTUP upstream is enabled.

0 = No socket activity (default) 1 = Socket activity

0 = Power stream is complete and delay has expired. 1 = Power stream is in progress.

0 = Power-up delay has expired. 1 = Power-up stream sent to switch. Power may not be stable.

0 = Power-down delay has expired. 1 = Power-down stream sent to switch. Power may not be stable.

0 = Interrogation not in progress (default) 1 = Interrogation in progress

0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read only (default).

0 = CardBus data parity not signaled on PCI SERR 1 = CardBus data parity signaled on PCI SERR

0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled

0 = Allows normal functioning of both CLKRUN 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN

0 = RI_OUT and PME signals are both routed to the RI_OUT/PME terminal. If both are enabled at the same time, RI_OUT will have precedence over PME. 1 = Only PME signals are routed to the RI_OUT/PME terminal.

(default)

protocols.(default)

protocols.

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multimedia control register

Bit 7 6 5 4 3 2 1 0 Name Multimedia control Type R/W R/W R R R R R/W R/W Default 0 0 0 0 0 0 0 0

Register: Multimedia control Type: Read only, read/write (see individual bit descriptions) Offset: 84h (functions 0, 1) Default: 00h Description: The multimedia control register provides port mapping for the PCI1251A zoom video/data

ports (see Refer to Table 33 for a complete description of the register contents.

BIT SIGNAL TYPE FUNCTION

7 ZVOUTEN R/W

6 PORTSEL R/W

5–2 RSVD R Reserved. Bits 5–2 return 0s when read. Writes have no effect.

1 ZVEN1 R/W

0 ZVEN0 R/W

zoom video support

, on page 29). Access this register only through function 0.

Table 33. Multimedia Control Register

ZV output enable. Bit 7 enables the output for the PCI1251A outsourcing ZV terminals. When this bit is reset 0, these terminals are in a high-impedance state.

ZV port select. Bit 6 controls the multiplexing control over which PC Card ZV port data is driven to the outsourcing PCI1251A ZV port.

PC Card 1 ZV mode enable. Bit 1 enables the zoom video mode for socket 1. When set, the PCI1251A inputs ZV data from the PC Card interface and disables output drivers on ZV terminals.

PC Card 0 ZV mode enable. Bit 0 enables the zoom video mode for socket 0. When set, the PCI1251A inputs ZV data from the PC Card interface and disables output drivers on ZV terminals.

0 = PCI1251A ZV output terminals disabled (default) 1 = PCI1251A ZV output terminals enabled

0 = Output card 0 ZV if enabled (default) 1 = Output card 1 ZV if enabled

0 = PC Card 1 ZV disabled (default) 1 = PC Card 1 ZV enabled

0 = PC Card 0 ZV disabled (default) 1 = PC Card 0 ZV enabled

general status register

Bit 7 6 5 4 3 2 1 0 Name General status Type R R R R R R R R Default 0 0 0 0 0 X 0 0

Register: General status Type: Read only Offset: 85h (functions 0, 1) Default: 0Xh Description: The general status register provides general device status information. The status of the

serial EEPROM interface is provided through this register. Refer to Table 34 for a complete description of the register contents.

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Table 34. General Status Register

BIT SIGNAL TYPE FUNCTION

7–3 RSVD R Reserved. Bits 7–3 are read only and return 0s when read.

Serial EEPROM detect. When bit 2 is cleared, it indicates that the PCI1251A serial EEPROM circuitry has

†

EEDETECT R

†

These bits are global and should be accessed only through function 0.

DATAERR R

†

EEBUSY R

GPIO0 control register

Bit 7 6 5 4 3 2 1 0 Name GPIO0 control Type R/W R/W R R/W R/W R R/W R/W Default 1 0 0 0 0 0 0 0

detected an EEPROM. A pullup resistor must be implemented on LA TCH for bit 2 to be set. This status bit is encoded as:

0 = EEPROM not detected (default) 1 = EEPROM detected

Serial EEPROM data error status. Bit 1 indicates when a data error occurs on the serial EEPROM interface. Bit 2 may be set due to a missing acknowledge. This bit is cleared by writing a 1.

0 = No error detected (default) 1 = Data error detected

Serial EEPROM busy status. Bit 0 indicates the status of the PCI1251A serial EEPROM circuitry. This bit is set during the loading of the subsystem ID value.

0 = Serial EEPROM circuitry not busy (default) 1 = Serial EEPROM circuitry busy

Register: GPIO0 control Type: Read only, read/write (see individual bit descriptions) Offset: 88h (functions 0, 1) Default: 80h Description: The GPIO0 control register is used for control of the general-purpose I/O 0 (GPIO0). This

terminal defaults to a general-purpose input but can be reconfigured as the socket 0 activity LED output, a zoom video enabled status output, or general-purpose output. Access this register only through function 0. Refer to Table 35 for a complete description of the register contents.

Table 35. GPIO0 Control Register

BIT SIGNAL TYPE FUNCTION

General-purpose 0 mode. Bits 7–6 select the functionality of LEDA1/GPIO0. These bits are encoded as:

7–6 GP0 R/W

5 RSVD R Reserved. Bits 5–4 return 0s when read. Writes have no effect. 4 GPINTEN0 R/W

3 DELTA0 R/W 2 RSVD R Reserved. Bit 2 returns 0 when read. Writes have no effect. 1 DATAOUT0 R/W

0 DATAIN0 R/W

GP interrupt enable. When bit 4 is set, a socket A card status change (CSC) interrupt is generated when the DELTA0 bit is set.

DAT AIN0 change status. Bit 3 is set when the DAT AIN0 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1.

General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output.

General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

00 = Signal LEDA1 to indicate PC Card socket 0 activity 01 = Signal ZVSTAT to indicate zoom video output enabled 10 = General-purpose input (GPI) 11 = General-purpose output (GPO)

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GPIO1 control register

Bit 7 6 5 4 3 2 1 0 Name GPIO1 control Type R/W R/W R R/W R/W R R/W R/W Default 1 0 0 0 0 0 0 0

Register: GPIO1 control Type: Read only, read/write (see individual bit descriptions) Offset: 89h (functions 0, 1) Default: 80h Description: The GPIO1 control register is used for control of the general-purpose I/O 1 (GPIO1). This

terminal defaults to a general-purpose input, but can be reconfigured as the socket 1 activity LED output or general-purpose output. Access this register only through function 0. Refer to Table 36 for a complete description of the register contents.

Table 36. GPIO1 Control Register

BIT SIGNAL TYPE FUNCTION

General-purpose 1 mode. Bits 7–6 select the functionality of LEDA2/GPIO1. These bits are encoded as:

7–6 GP1 R/W

5 RSVD R Reserved. Bit 5 returns 0 when read. Writes have no effect. 4 GPINTEN1 R/W

3 DELTA1 R/W 2 RSVD R Reserved. Bit 2 returns 0 when read. Writes have no effect. 1 DATAOUT1 R/W

0 DATAIN1 R/W

GP interrupt enable. When bit 4 is set, a socket A card status change (CSC) interrupt is generated when the DELTA1 bit is set.

DAT AIN1 change status. Bit 3 is set when the DAT AIN1 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1.

General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output.

General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

00 = Signal LEDA2 to indicate PC Card socket 1 activity. 01 = Reserved. 10 = General-purpose input (GPI). 11 = General-purpose output (GPO).

GPIO2 control register

Bit 7 6 5 4 3 2 1 0 Name GPIO2 control Type R/W R/W R R/W R/W R R/W R/W Default 1 0 0 0 0 0 0 0

Register: GPIO2 control Type: Read only, read/write (see individual bit descriptions) Offset: 8Ah (functions 0, 1) Default: 80h Description: The GPIO2 control register is used for control of the general-purpose I/O 2 (GPIO2). This

terminal defaults to a general-purpose input but can be reconfigured as PCI LOCK

, a zoom video enabled status output, or general-purpose output. Access this register only through function 0. Refer to Table 37 for a complete description of the register contents.

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Table 37. GPIO2 Control Register

BIT SIGNAL TYPE FUNCTION

General-purpose 2 mode. Bits 7–6 select the functionality of LOCK/GPIO2. These bits are encoded as:

7–6 GP2 R/W

5 RSVD R Reserved. Bit 5 returns 0 when read. Writes have no effect. 4 GPINTEN2 R/W

3 DELTA2 R/W 2 RSVD R Reserved. Bit 2 returns 0 when read. Writes have no effect. 1 DATAOUT2 R/W

0 DATAIN2 R/W

GP interrupt enable. When bit 4 is set, a socket B card status change (CSC) interrupt is generated when the DELTA2 bit is set.

DAT AIN2 change status. Bit 3 is set when the DAT AIN2 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1.

General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output.

General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

GPIO3 control register

Bit 7 6 5 4 3 2 1 0 Name GPIO3 control Type R/W R/W R R/W R/W R R/W R/W Default 1 0 0 0 0 0 0 0

00 = Terminal is configured as PCI LOCK 01 = Signal ZVSTAT to indicate zoom video output is enabled. 10 = General-purpose input (GPI) 11 = General-purpose output (GPO)

Register: GPIO3 control Type: Read only, read/write (see individual bit descriptions) Offset: 8Bh (functions 0, 1) Default: 80h Description: The GPIO3 control register is used for control of the general-purpose I/O 3 (GPIO3). This

terminal defaults to a general-purpose input but can be reconfigured as PCI INTA general-purpose output. Access this register only through function 0. Refer to Table 38 for a complete description of the register contents.

Table 38. GPIO3 Control Register

BIT SIGNAL TYPE FUNCTION

General-purpose 3 mode. Bits 7–6 select the functionality of INTA/GPIO3. These bits are encoded as:

7–6 GP3 R/W

5 RSVD R Reserved. Bit 5 returns 0 when read. Writes have no effect. 4 GPINTEN3 R/W

3 DELTA3 R/W 2 RSVD R Reserved. Bit 2 returns 0 when read. Writes have no effect. 1 DATAOUT3 R/W

0 DATAIN3 R/W

GP interrupt enable. When bit 4 is set, a socket B card status change (CSC) interrupt is generated when the DELTA3 bit is set.

DAT AIN3 change status. Bit 3 is set when the DAT AIN3 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1.

General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output.

General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

00 = Terminal is configured as PCI INT A 01 = Reserved 10 = General-purpose input (GPI) 11 = General-purpose output (GPO)

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IRQMUX routing register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name IRQMUX routing Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IRQMUX routing Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: IRQMUX routing Type: Read/write (see individual bit descriptions) Offset: 8Ch (functions 0, 1) Default: 0000 0000h Description: The IRQMUX routing register is used for the legacy interrupt mux routing feature of the

PCI1251A, which is described in the p parallel IRQ interrupt scheme is selected, all PCI1251A interrupts sent to ISA IRQs are signaled on the corresponding IRQMUX7–IRQMUX0 signals. These signals are routed directly to various IRQ inputs on the system PIC, and the routing information is programmed through this register. Each terminal has at least one secondary function that can be selected by programming the bits appropriately. Access this register only through function 0. Refer to Table 39 for a complete description of the register contents.

rogrammable interrupt subsystem

on page 32. If the

Table 39. IRQMUX Routing Register

BIT SIGNAL TYPE FUNCTION

IRQMUX7 routing. Bits 31–28 select one of 15 interrupts that may be routed on IRQMUX7. When these bits are 0000 and bit 3 in the system control register is set, this pin is used for PCREQ

NOTE: These bits must not be configured for IRQ signaling if IRQMUX7 is being used for PCREQ

31–28 IRQMUX7 R/W

NOTES: 1. These bits must not be configured for IRQ signaling if IRQMUX6 is being used for PCGNT

27–24 IRQMUX6 R/W

signaling.

0000 = EEPROM SCL routed on IRQMUX7 (default) 0000 = PCREQ routed on IRQMUX7 when bit 3 of the system control register is 1 0001 = PCREQ 0010 = IRQ2 routed on IRQMUX7 0011 = IRQ3 routed on IRQMUX7 : 1111 = IRQ15 routed on IRQMUX7

IRQMUX6 routing. Bits 27–24 select one of 15 interrupts that may be routed on IRQMUX6. When these bits are 0000 and bit 3 in the system control register is set, this pin is used for PCGNT

signaling.

2. An EEPROM cannot be used if IRQMUX7 and IRQMUX6 are being used for DMA PCREQ PCGNT.

0000 = EEPROM SDA routed on IRQMUX6 (default) 0000 = PCGNT 0001 = IRQ1 routed on IRQMUX6 0010 = IRQ2 routed on IRQMUX6 0011 = IRQ3 routed on IRQMUX6 : 1111 = IRQ15 routed on IRQMUX6

routed on IRQMUX7

routed on IRQMUX6 when bit 3 of the system control register is 1

DMA signaling.

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Table 39. IRQMUX Routing Register (Continued)

BIT SIGNAL TYPE FUNCTION

IRQMUX5 routing. Bits 23–20 select one of 15 interrupts that may be routed on IRQMUX5. When these bits are 0000, then no routing is selected.

23–20 IRQMUX5 R/W

IRQMUX4 routing. Bits 19–16 select one of 15 interrupts that may be routed on IRQMUX4. When these bits are 0000, then no routing is selected.

19–16 IRQMUX4 R/W

IRQMUX3 routing. Bits 15–12 select one of 15 interrupts that may be routed on IRQMUX3. When these bits are 0000, then no routing is selected.

15–12 IRQMUX3 R/W

IRQMUX2 routing. Bits 11–8 select one of 15 interrupts that may be routed on IRQMUX2. When these bits are 0000, then no routing is selected.

11–8 IRQMUX2 R/W

IRQMUX1 routing. Bits 7–4 select one of 15 interrupts that may be routed on IRQMUX1. When these bits are 0000, then no routing is selected.

7–4 IRQMUX1 R/W

IRQMUX0 routing. Bits 3–0 select one of 15 interrupts that may be routed on IRQMUX0. When these bits are 0000, then no routing is selected.

3–0 IRQMUX0 R/W

0000 = No IRQ routing selected (default) 0001 = CardBus audio (CBAUDIO) routed on IRQMUX5 0010 = IRQ2 routed on IRQMUX5 0011 = IRQ3 routed on IRQMUX5 : 1111 = IRQ15 routed on IRQMUX5

0000 = No IRQ routing selected (default) 0001 = ZVSTAT routed on IRQMUX4 0010 = RI_OUT 0011 = IRQ3 routed on IRQMUX4 0100 = IRQ4 routed on IRQMUX4 : 1111 = IRQ15 routed on IRQMUX4

0000 = No IRQ routing selected (default) 0001 = LEDA or LEDB routed on IRQMUX3 0010 = RI_OUT 0011 = IRQ3 routed on IRQMUX3 0100 = IRQ4 routed on IRQMUX3 : 1111 = IRQ15 routed on IRQMUX3

0000 = No IRQ routing selected (default) 0001 = LEDB routed on IRQMUX2 0010 = IRQ2 routed on IRQMUX2 0011 = IRQ3 routed on IRQMUX2 : 1111 = IRQ15 routed on IRQMUX2

0000 = No IRQ routing selected (default) 0001 = LEDA routed on IRQMUX1 0010 = IRQ2 routed on IRQMUX1 0011 = IRQ3 routed on IRQMUX1 : 1111 = IRQ15 routed on IRQMUX1

0000 = No IRQ routing selected (default) 0001 = INTB 0010 = IRQ2 routed on IRQMUX0 0011 = IRQ3 routed on IRQMUX0 : 1111 = IRQ15 routed on IRQMUX0

routed on IRQMUX4

routed on IRQMUX3

routed on IRQMUX0

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retry status register

Bit 7 6 5 4 3 2 1 0 Name Retry status Type R/W R/W R/W R R R R/W R Default 1 1 0 0 0 0 0 0

Register: Retry status Type: Read only, read/write (see individual bit descriptions) Offset: 90h (functions 0, 1) Default: C0h Description: The retry status register enables the retry timeout counters and displays the retry expiration

status. The flags are set when the PCI1251A retries a PCI or CardBus master request, and the master does not return within 2 bit. These bits are expected to be incorporated into the PCI command, PCI status, and bridge control registers by the PCI SIG. Access this register only through function 0. Refer to Table 40 for a complete description of the register contents.

Table 40. Retry Status Register

BIT SIGNAL TYPE FUNCTION

PCI retry timeout counter enable. Bit 7 is encoded:

7 PCIRETRY R/W

†

CBRETRY R/W

5 TEXP_CBB R/W

4 RSVD R Reserved. Bit 4 returns 0 when read.

†

TEXP_CBA R

2 RSVD R Reserved. Bit 2 returns 0 when read.

1 TEXP_PCI R/W

0 RSVD R Reserved. Bit 0 returns 0 when read.

†

These bits are global and should be accessed only through function 0.

CardBus retry timeout counter enable. Bit 6 is encoded:

CardBus target B retry expired. Write a 1 to clear bit 5.

CardBus target A retry expired. Write a 1 to clear bit 3.

PCI target retry expired. Write a 1 to clear bit 1.

0 = PCI retry counter disabled 1 = PCI retry counter enabled (default)

0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default)

0 = Inactive (default) 1 = Retry has expired

0 = Inactive (default) 1 = Retry has expired.

PCI clock cycles. The flags are cleared by writing a 1 to the

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card control register

Bit 7 6 5 4 3 2 1 0 Name Card control Type R/W R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Card control Type: Read only, read/write (see individual bit descriptions) Offset: 91h Default: 00h Description: The card control register is provided for PCI1130 compatibility. It provides the PC Card

function interrupt flag (IFG) and an alias for the ZVEN0 and ZVEN1 bits found in the PCI1251A multimedia control register. When this register is accessed by function 0, the ZVEN0 bit will alias with ZVENABLE. When this register is accessed by function 1, the ZVEN1 bit will alias with ZVENABLE. Setting ZVENABLE only places the PC Card socket interface ZV terminals in a high-impedance state, but does not enable the PCI1251A to drive ZV data onto the ZV terminals. RI_OUT is enabled through this register, and the enable bit is shared between functions 0 and 1. Refer to Table 41 for a complete description of the register contents.

Table 41. Card Control Register

BIT SIGNAL TYPE FUNCTION

Ring indicate output enable.

†

6 ZVENABLE R/W 5 RSVD R Reserved. Bit 5 returns 0 when read.

4–3 RSVD R Reserved. Bits 4–3 are read only and default to 0.

2 AUD2MUX R/W

1 SPKROUTEN R/W

0 IFG R/W

†

This bit is global and should be accessed only through function 0.

RIENB R/W

to 0, and for routing to IRQMUX3/4. Compatibility ZV mode enable. When set, the corresponding PC Card Socket interface ZV terminals

enter a high-impedance state. This bit defaults to 0.

CardBus Audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding IRQMUX terminal. Function 0, A_CAUDIO is routed to IRQMUX0, and function 1, B_AUDIO is routed to IRQMUX1. If this bit is set for both functions, function 0 is routed.

Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT on the PCI bus. The SPKR sent to SPKROUT. The SPKROUT terminal drives data only when either functions SPKROUTEN bit is set. This bit is encoded as:

Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a functional interrupt is signaled from a PC Card interface and is socket dependent (i.e., not global). Write back a 1 to clear this bit.

0 = Disables any routing of RI_OUT 1 = Enables RI_OUT

0 = CAUDIO set to CAUDPWM on IRQMUX routed (default) 1 = CAUDIO is not routed.

signal from socket 0 is exclusive ORed with the SPKR signal from socket 1 and

0 = SPKR 1 = SPKR

0 = No PC Card functional interrupt detected (default) 1 = PC Card functional interrupt detected

to SPKROUT not enabled to SPKROUT enabled

signal for routing to the RI_OUT/PME terminal when RIMUX is set

signal (default).

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device control register

Bit 7 6 5 4 3 2 1 0 Name Device control Type R R/W R/W R R/W R/W R/W R/W Default 0 1 1 0 0 1 1 0

Register: Device control Type: Read only, read/write (see individual bit descriptions) Offset: 92h (functions 0, 1) Default: 66h Description: The device control register is provided for PCI1130 compatibility and contains bits that are

shared between functions 0 and 1. The interrupt mode select is programmed through this register which is composed of PCI1251A global bits. The socket-capable force bits are also programmed through this register. Refer to Table 42 for a complete description of the register contents.

Table 42. Device Control Register

BIT SIGNAL TYPE FUNCTION

7 RSVD R Reserved. Bit 7 Returns 0 when read.

†

3VCAPABLE R/W

5 IO16R2 R/W Diagnostic bit. This bit defaults to 1. 4 RSVD R Reserved. Bit 4 returns 0 when read. Writes have no effect.

†

2–1

†

These bits are global and should be accessed only through function 0.

TEST R/W TI test. Only a 0 should be written to bit 3. This bit can be set to shorten the interrogation counter.

INTMODE R/W

RSVD R/W

3-V socket capable force

Interrupt mode. Bit 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded:

Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI1251A, and it tests only the pins that are inputs or I/Os. Any output-only terminal on the PCI1251A is excluded from the NAND tree test.

0 = Not 3-V capable 1 = 3-V capable (default)

00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupts INTA 11 = IRQ and PCI serialized interrupts (default)

and INTB

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diagnostic register

Bit 7 6 5 4 3 2 1 0 Name Diagnostic Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 0 0 0 0 1

Register: Diagnostic Type: Read/write Offset: 93h (functions 0, 1) Default: 61h Description: The diagnostic register is provided for internal TI test purposes. It is a read/write register, but

only 0s should be written to this register. Refer to Table 43 for a complete description of the register contents.

Table 43. Diagnostic Register

BIT SIGNAL TYPE FUNCTION

†

6-5 RSVD R/W

4 3 2 1

†

These bits are global and should be accessed only through function 0.

TRUE_VAL R/W

† † † †

†

DIAG R/W Diagnostic RETRY_DIS. Delayed transaction disable. DIAG R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. DIAG R/W Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. DIAG R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.

ASYNC_CSC R/W

True value. This bit defaults to 0 when read. This bit is encoded as:

0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in reads to the PCI vendor ID and PCI device ID registers

Reserved. These bits are reserved for TI internal test purposes. The value of these bits should not be changed for normal operation.

Asynchronous interrupt generation.

0 = CSC interrupt not generated asynchronously 1 = CSC interrupt generated asynchronously (default)

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socket DMA register 0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Socket DMA register 0 Type: Read only, read/write (see individual bit descriptions) Offset: 94h (functions 0, 1) Default: 0000 0000h Description: The socket DMA register 0 provides control over the PC Card DMA request (DREQ

Refer to Table 44 for a complete description of the register contents.

Table 44. Socket DMA Register 0

BIT SIGNAL TYPE FUNCTION

31–2 RSVD R Reserved. Bits 31–2 are read only and return 0s when read.

DMA request (DREQ). Bits 1–0 indicate which pin on the 16-bit PC Card interface acts as DREQ during DMA transfers. This field is encoded as:

1–0 DREQPIN R/W

00 = Socket not configured for DMA (default). 01 = DREQ 10 = DREQ 11 = DREQ

uses SPKR. uses IOIS16. uses INPACK.

) signaling.

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socket DMA register 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket DMA register 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket DMA register 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Socket DMA register 1 Type: Read only, read/write (see individual bit descriptions) Offset: 98h (functions 0, 1) Default: 0000 0000h Description: The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and

the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K-bytes of PCI I/O address space. Refer to Table 45 for a complete description of the register contents.

NOTE:

32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits.

Table 45. Socket DMA Register 1

BIT SIGNAL TYPE FUNCTION

31–16 RSVD R Reserved. Bits 31–16 are read only and return 0s when read.

DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit

15–4 DMABASE R/W

3 EXTMODE R Extended addressing. This feature is not supported by the PCI1251A and always returns a 0.

2–1 XFERSIZE R/W

0 DDMAEN R/W

PCI I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K-bytes of I/O address space. The lower four bits are hardwired to 0 and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary.

Transfer size. Bits 2–1 specify the width of the DMA transfer on the PC Card interface and are encoded as:

00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved

DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value of DMABASE.

0 = Disabled (default) 1 = Enabled

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capability ID register

Bit 7 6 5 4 3 2 1 0 Name Capability ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1

Register: Capability ID Type: Read only Offset: A0h Default: 01h Description: The capability ID register identifies the linked list item as the register for PCI power

management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value.

next-item pointer register

Bit 7 6 5 4 3 2 1 0 Name Next-item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Next-item pointer Type: Read only Offset: A1h Default: 00h Description: The next-item pointer register is used to indicate the next item in the linked list of the PCI power

management capabilities. Because the PCI1251A functions only include one capabilities item, this register returns 0s when read.

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power-management capabilities register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management capabilities Type R R R R R R R R R R R R R R R R Default 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1

Register: Power-management capabilities Type: Read only (see individual bit descriptions) Offset: A2h (functions 0, 1) Default: 7E21h Description: The power-management capabilities register contains information on the capabilities of the

PC Card function related to power management. Both PCI1251A CardBus bridge functions support D0, D2, and D3 power states. Refer to Table 46 for a complete description of the register contents.

Table 46. Power-Management Capabilities Register

BIT SIGNAL TYPE FUNCTION

PME support. This 4-bit field indicates the power states from which the PCI1251A supports asserting PME. A 0 for any bit indicates that the CardBus function cannot assert PME bits return 1110b when read. Each of these bits is described below:

15–1 1 PME_SUP R

10 D2_SUP R

9 D1_SUP R

8–6 RSVD R Reserved. These bits are reserved and return 000b when read.

5 DSI R

4 AUX_PWR R

3 PMECLK R

2–0 R

D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device power state.

D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device power state.

Device-specific initialization. Bit 5 is read only and returns 1 when read, indicating that the CardBus controller functions require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it.

Auxiliary power source. This bit is meaningful only if bit 15 (D3 4 indicates that support for PME

PME clock. When set, bit 3 indicates that the function relies on the presence of the PCI clock for PME operation.

Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power management (PM) registers as described in the PCI Bus Power Management Interface Specification Revision 1.0.

Bit 15 contains the value 0, indicating that PME Bit 14 contains the value 1, indicating that PME Bit 13 contains the value 1, indicating that PME Bit 12 contains the value 1, indicating that PME Bit 11 contains the value 1, indicating that PME

0 = Function supplies its own auxiliary power source 1 = Support for PME

proprietary source.

0 = PCI clock not required for the function to generate PME 1 = PCI function required to generate PME

in D3cold requires auxiliary power.

in D3c

requires auxiliary power supplied to the system by a

old

from that power state. These four

cannot be asserted from D3 can be asserted from D3 can be asserted from D2 state. can be asserted from D1 state. can be asserted from the D0 state.

supporting PME) is set. When set, bit

cold

hot

cold state.

state.

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power-management control/status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management control/status Type R/W R R R R R R R/W R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Power-management control/status Type: Read only, read/write (see individual bit descriptions) Offset: A4h (functions 0, 1) Default: 000000h Description: The power-management control/status register determines and changes the current power

state of the PCI1251A CardBus function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3 for a complete description of the register contents.

NOTE:

A transition from the D3

state to D0 state resets all PCI, ExCA, and CardBus registers. TI specific,

hot

PCI power management, and legacy base address registers are not affected.

Table 47. Power-Management Control/Status Register

to D0 state. Refer to Table 47

hot

BIT SIGNAL TYPE FUNCTION

PME status. Bit 15 is set when the CardBus function would normally assert PME, independent of the

15 PMESTAT R/W

14–13 DATASCALE R

12–9 DATASEL R

8 PME_EN R/W PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, assertion of PME is disabled.

7–2 RSVD R Reserved. Bits 7–2 are read only and return 0s when read.

1–0 PWRSTATE R/W

state of the PME_EN bit. Bit 15 is cleared by a write back of 1, and this also clears the PME PME

was asserted by this function. Writing a 0 to this bit has no effect.

Data scale. This 2-bit field is read only, returning 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit.

Data select. This 4-bit field is read only and returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit.

Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. This field is encoded as:

00 = D0 01 = D1 10 = D2 11 = D3

hot

signal if

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power-management control/status register bridge support extensions

Bit 7 6 5 4 3 2 1 0 Name Power-management control/status register bridge support extensions Type R R R R R R R R Default 1 0 0 0 0 0 0 0

Register: Power-management control/status register bridge support extensions Type: Read only Offset: A6h (functions 0, 1) Default: 80h Description: The power-management control/status register bridge support extensions support PCI bridge

specific functionality and are required for all PCI-to-PCI bridges. Refer to Table 48 for a complete description of the register contents.

Table 48. Power-Management Control/Status Register Bridge Support Extensions

BIT SIGNAL TYPE FUNCTION

Bus power/clock control. When read, bit 7 returns 1b. This bit is encoded as:

7 BPCC_EN R

6 B2_B3 R

5–0 RSVD R Reserved. These bits are read only and return 0s when read.

A 0 indicates that the bus power/clock control policies defined in the PCI Power Management specification are disabled. When the bus power/clock control enable mechanism is disabled the bridge’s PMCSR PowerState field cannot be used by the system software to control the power or the clock of the bridge’s secondary bus. A 1 indicates that the bus power/clock control mechanism is enabled.

B2/B3 support for D3 of programming the function to D3 is encoded as:

0 = Bus power/clock control is disabled. 1 = Bus power/clock control is enabled (default).

. The state of this bit determines the action that is to occur as a direct result

hot

0 = When the bridge is programmed to D3

(B3)

1 = When the bridge is programmed to D3

(B2).

. This bit is meaningful only if bit 7 BPCC_Enable is a 1. This bit

hot

, its secondary bus has its power removed

hot

, its secondary bus’s PCI clock is stopped

hot

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ExCA compatibility registers (functions 0 and 1)

The ExCA (Exchangeable Card Architecture) registers implemented in the PCI1251A are register-compatible with the popular Intel 82365SL–DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-Bit I/F legacy mode base address register, which is shared by both card sockets. The offsets from this base address run contiguous from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. Refer to Figure 16 for an ExCA I/O mapping illustration. Table 49 identifies each ExCA register and its respective ExCA offset.

PCI1251A Configuration Registers

CardBus Socket/ExCA Base Address

16-Bit Legacy-Mode Base Address

Offset

10h

†

44h

Host I/O Space

Index

Data

PC Card A

ExCA

Registers

PC Card B

ExCA

Registers

Offset

00h

3Fh 40h

7Fh

†

The 16-bit legacy mode base address register is shared by functions 0 and 1 as indicated by the shading.

Figure 16. ExCA Register Access Through I/O

The TI PCI1251A also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus Socket Registers/ExCA Registers Base Address Register (PCI Register 10h) at memory offset 800h. Each socket has a separate base address programmable by function. Refer to Figure 17 for an ExCA memory mapping illustration. The memory offsets are 800h–844h for both functions 0 and 1. This illustration also identifies the CardBus Socket Register mapping, which are mapped into the same 4 K window at memory offset 0h.

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ExCA compatibility registers (functions 0 and 1) (continued)

Host

PCI1251A Configuration Registers

10h

CardBus Socket/ExCA Base Address

16-Bit Legacy-Mode Base Address

†

The CardBus socket/ExCA base address mode register is separate for functions 0 and 1.

†

44h

Memory Space

CardBus Socket A

Registers

ExCA

Registers

Card A

Offset

00h

20h

800h

844h

Host

Memory Space

CardBus Socket B

Registers

ExCA

Registers

Card B

Figure 17. ExCA Register Access Through Memory

The interrupt registers, as defined by the 82365SL Specification, in the ExCA register control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1251A to ensure that all possible PCI1251A interrupts can potentially be routed to the programmable interrupt controller . The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h.

OffsetOffset

00h

20h

800h

844h

Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity .

Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. Memory windows have 4K-byte granularity.

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Table 49. ExCA Registers and Offsets

PCI MEMORY ADDRESS

OFFSET (HEX)

Identification and revision 800 00 40 Interface status 801 01 41 Power control 802 02 42 Interrupt and general control 803 03 43 Card status change 804 04 44 Card status-change-interrupt configuration 805 05 45 Address window enable 806 06 46 I / O window control 807 07 47 I / O window 0 start-address low byte 808 08 48 I / O window 0 start-address high byte 809 09 49 I / O window 0 end-address low byte 80A 0A 4A I / O window 0 end-address high byte 80B 0B 4B I / O window 1 start-address low byte 80C 0C 4C I / O window 1 start-address high byte 80D 0D 4D I / O window 1 end-address low byte 80E 0E 4E I / O window 1 end-address high byte 80F 0F 4F Memory window 0 start-address low byte 810 10 50 Memory window 0 start-address high byte 811 11 51 Memory window 0 end-address low byte 812 12 52 Memory window 0 end-address high byte 813 13 53 Memory window 0 offset-address low byte 814 14 54 Memory window 0 offset-address high byte 815 15 55 Card detect and general control 816 16 56 Reserved 817 17 57 Memory window 1 start-address low byte 818 18 58 Memory window 1 start-address high byte 819 19 59 Memory window 1 end-address low byte 81A 1A 5A

Memory window 1 end-address high byte 81B 1B 5B Memory window 1 offset-address low byte 81C 1C 5C Memory window 1 offset-address high byte 81D 1D 5D Global control 81E 1E 5E Reserved 81F 1F 5F Memory window 2 start-address low byte 820 20 60 Memory window 2 start-address high byte 821 21 61 Memory window 2 end-address low byte 822 22 62 Memory window 2 end-address high byte 823 23 63 Memory window 2 offset-address low byte 824 24 64 Memory window 2 offset-address high byte 825 25 65 Reserved 826 26 66 Reserved 827 27 67

ExCA OFFSET (HEX) CARD A CARD B

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Table 49. ExCA Registers and Offsets (Continued)

PCI MEMORY ADDRESS

OFFSET (HEX)

Memory window 3 start-address low byte 828 28 68 Memory window 3 start-address high byte 829 29 69 Memory window 3 end-address low byte 82A 2A 6A Memory window 3 end-address high byte 82B 2B 6B Memory window 3 offset-address low byte 82C 2C 6C Memory window 3 offset-address high byte 82D 2D 6D Reserved 82E 2E 6E Reserved 82F 2F 6F Memory window 4 start-address low byte 830 30 70 Memory window 4 start-address high byte 831 31 71 Memory window 4 end-address low byte 832 32 72 Memory window 4 end-address high byte 833 33 73 Memory window 4 offset-address low byte 834 34 74 Memory window 4 offset-address high byte 835 35 75 I/O window 0 offset-address low byte 836 36 76 I/O window 0 offset-address high byte 837 37 77 I/O window 1 offset-address low byte 838 38 78 I/O window 1 offset-address high byte 839 39 79 Reserved 83A 3A 7A Reserved 83B 3B 7B Reserved 83C 3C 7C Reserved 83D 3D 7D Reserved 83E 3E 7E Reserved 83F 3F 7F Memory window page 0 840 – – Memory window page 1 841 – – Memory window page 2 842 – – Memory window page 3 843 – – Memory window page 4 844 – –

ExCA OFFSET (HEX) CARD A CARD B

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ExCA identification and revision register† (index 00h)

Bit 7 6 5 4 3 2 1 0 Name ExCA identification and revision Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 0 1 0 0

Register: ExCA identification and revision Type: Read only, read/write (see individual bit descriptions) Offset: CardBus socket address + 800h; Card A ExCA offset 00h

Card B ExCA offset 40h Default: 84h Description: This register provides host software with information on 16-bit PC Card support and Intel

82365SL-DF compatibility. Refer to Table 50 for a complete description of the register

†

When bit 5 in the system control register is 1, this register is read only.

BIT SIGNAL TYPE FUNCTION

7–6 IFTYPE R/W 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation.

3–0 365REV R/W

contents.

Table 50. ExCA Identification and Revision Register (Index 00h)

Interface type. These bits default to 10b and identify the 16-bit PC Card support provided by the PCI1251A. The PCI1251A supports both I/O and memory 16-bit PC cards.

Intel 82365SL-DF revision. This read/write field stores the Intel 82365SL-DF revision supported by the PCI1251A. Host software can read this field to determine compatibility to the Intel This field defaults to 0100b upon PCI1251A reset.

82365SL-DF register set.

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ExCA interface status register (index 01h)

Bit 7 6 5 4 3 2 1 0 Name ExCA interface status Type R R R R R R R R Default 0 0 X X X X X X

Register: ExCA interface status Type: Read only (see individual bit descriptions) Offset: CardBus socket address + 801h; Card A ExCA offset 01h

Card B ExCA offset 41h Default: 00XX XXXXb Description: This register provides information on the current status of the PC Card interface. An X in the

default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. Refer to Table 51 for a complete description of the register contents.

Table 51. ExCA Interface Status Register (Index 01h)

BIT SIGNAL TYPE FUNCTION

7 RSVD R Reserved. Bit 7 is read only and returns 0 when read. Writes have no effect.

Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the power

6 CARDPWR R

5 READY R

4 CARDWP R

3 CDETECT2 R

2 CDETECT1 R

1–0 BVDSTAT R

control register has been programmed. Bit 6 is encoded as:

Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.

Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to the PCI1251A whether or not the memory card is write protected. Furthermore, write protection for an entire PCI1251A 16-bit memory window is available by setting the appropriate bit in the memory window offset high-byte register.

Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket.

Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket.

Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD1 status and bit 0 reflects BVD2.

When a 16-bit I/O card is inserted, this field indicates the status of SPKR the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.

0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on

0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer

0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read only.

0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted.

0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted.

00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good

(bit 1) and STSCHG (bit 0) at

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ExCA power-control register (index 02h)

Bit 7 6 5 4 3 2 1 0 Name ExCA power control Type R/W R R R/W R/W R R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA power control Type: Read only, read/write (see individual bit descriptions) Offset: CardBus socket address + 802h; Card A ExCA offset 02h

Card B ExCA offset 42h Default: 00h Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit outputs

on the socket interface and can be used for power management in 16-bit PC Card applications. Refer to Table 52 for a complete description of the register contents.

Table 52. ExCA Power-Control Register (Index 02h)

BIT SIGNAL TYPE FUNCTION

Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1251A. This bit is

7 COE R/W

6–5 RSVD R Reserved. Bits 6–5 are read only and return 0s when read. Writes have no effect.

4–3 EXCAVCC R/W

2 RSVD R Reserved. Bit 2 is read only and returns 0 when read. Writes have no effect.

1–0 EXCAVPP R/W

encoded as:

VCC. Bits 4–3 are used to request changes to card VCC. This field is encoded as:

VPP. Bits 1–0 are used to request changes to card VPP. The PCI1251A ignores this field unless VCC to the socket is enabled (i.e., 5 V or 3.3 V). This field is encoded as:

0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled

00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3 V

00 = 0 V (default) 01 = V

10 = 12 V 11 = 0 V reserved

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ExCA interrupt and general-control register (index 03h)

Bit 7 6 5 4 3 2 1 0 Name ExCA interrupt and general control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA interrupt and general control Type: Read/write (see individual bit descriptions) Offset: CardBus socket address + 803h; Card A ExCA offset 03h

Card B ExCA offset 43h Default: 00h Description: This register controls interrupt routing for I/O interrupts, as well as other critical 16-bit

PC Card functions. Refer to Table 53 for a complete description of the register contents.

Table 53. ExCA Interrupt and General-Control Register (Index 03h)

BIT SIGNAL TYPE FUNCTION

7 RINGEN R/W

6 CARD_RST R/W

5 CARDTYPE R/W

4 CSCROUTE R/W

3–0 INTSELECT R/W

Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:

Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as

Card type. Bit 5 indicates the PC card type. This bit is encoded as:

PCI Interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 in the ExCA card status change interrupt configuration register. This bit is encoded as:

Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as:

0 = Ring indicate disabled (default) 1 = Ring indicate enabled

0 = RESET signal asserted (default) 1 = RESET signal deasserted

0 = Memory PC Card installed (default) 1 = I/O PC Card installed

0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts.

0000 = No interrupt routing (default). 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

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ExCA card status-change register (index 04h)

Bit 7 6 5 4 3 2 1 0 Name ExCA card status change Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: ExCA card status change Type: Read only (see individual bit descriptions) Offset: CardBus socket address + 804h; Card A ExCA offset 04h

Card B ExCA offset 44h Default: 00h Description: This register reflects the status of PC Card CSC interrupt sources. The ExCA card

status-change interrupt configuration register, Table 55, enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit write back of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the global control register. Refer to Table 54 for a complete description of the register contents.

Table 54. ExCA Card Status-Change Register (Index 04h)

BIT SIGNAL TYPE FUNCTION

7–4 RSVD R Reserved. Bits 7–4 are read only and return 0s when read. Writes have no effect.

Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card

3 CDCHANGE R

2 READYCHANGE R

1 BATWARN R

0 BA TDEAD R

interface. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1251A interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

When a 16-bit I/O card is installed, bit 2 is always 0. Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether

the source of a PCI1251A interrupt was due to a battery-low warning condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

When a 16-bit I/O card is installed, bit 1 is always 0. Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates

whether the source of a PCI1251A interrupt was due to a battery dead condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

Ring indicate. When the PCI1251A is configured for ring indicate operation, bit 0 indicates the status of RI.

0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2

0 = No low-to-high transition detected on READY (default) 1 = Detected low-to-high transition on READY

0 = No battery warning condition (default) 1 = Detected battery warning condition

0 = STSCHG 1 = STSCHG

deasserted (default) asserted

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ExCA card status-change-interrupt configuration register (index 05h)

Bit 7 6 5 4 3 2 1 0 Name ExCA status-change-interrupt configuration Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA card status-change-interrupt configuration Type: Read/write (see individual bit descriptions) Offset: CardBus socket address + 805h; Card A ExCA offset 05h

Card B ExCA offset 45h Default: 00h Description: This register controls interrupt routing for card status-change interrupts, as well as masking

CSC interrupt sources. Refer to Table 55 for a complete description of the register contents.

Table 55. ExCA Card Status-Change-Interrupt Configuration Register (Index 05h)

BIT SIGNAL TYPE FUNCTION

Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change

7–4 CSCSELECT R/W

3 CDEN R/W

2 READYEN R/W

1 BATWARNEN R/W

0 BATDEADEN R/W

interrupts. This field is encoded as:

Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:

Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as:

Battery Warning Enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as:

Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG

0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes

0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation

I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation

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ExCA address window enable register (index 06h)

Bit 7 6 5 4 3 2 1 0 Name ExCA address window enable Type R/W R/W R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA address window enable Type: Read only, read/write (see individual bit descriptions) Offset: CardBus socket address + 806h; Card A ExCA offset 06h

Card B ExCA offset 46h Default: 00h Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default,

all windows to the card are disabled. The PCI1251A does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. Refer to Table 56 for a complete description of the register contents.

Table 56. ExCA Address Window Enable Register (Index 06h)

BIT SIGNAL TYPE FUNCTION

I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:

7 IOWIN1EN R/W

I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:

6 IOWIN0EN R/W

5 RSVD R Reserved. Bit 5 is read only and returns 0 when read. Writes have no effect.

Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is

4 MEMWIN4EN R/W

3 MEMWIN3EN R/W

2 MEMWIN2EN R/W

1 MEMWIN1EN R/W

0 MEMWIN0EN R/W

encoded as:

Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is encoded as:

Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is encoded as:

Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is encoded as:

Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is encoded as:

0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled

0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled

0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled

0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled

0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled

0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled

0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled

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ExCA I/O window control register (index 07h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window control Type: Read/write (see individual bit descriptions) Offset: CardBus socket address + 807h; Card A ExCA offset 07h

Card B ExCA offset 47h Default: 00h Description: This register contains parameters related to I/O window sizing and cycle timing. Refer to

Table 57 for a complete description of the register contents.

Table 57. ExCA

BIT SIGNAL TYPE FUNCTION

I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel

7 WAITSTATE1 R/W

6 ZEROWS1 R/W

5 IOIS16W1 R/W

4 DATASIZE1 R/W

3 WAITSTATE0 R/W

2 ZEROWS0 R/W

1 IOIS16W0 R/W

0 DATASIZE0 R/W

This bit is encoded as:

I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:

I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16

I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if the I/O window 1 IOIS16

I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel This bit is encoded as:

I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:

I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16

I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if the I/O window 0 IOIS16

I/O Window Control Register (Index 07h)

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:

0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16

source bit (bit 5) is set. This bit is encoded as:

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:

0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16

source bit (bit 1) is set. This bit is encoded as:

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

82365SL-DF .

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ExCA I/O window 0 and 1 start-address low-byte register (index 08h, 0Ch)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 48h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch; Card A ExCA offset 0Ch

Card B ExCA offset 4Ch Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0

and 1. The eight bits of these registers correspond to the lower eight bits of the start address.

ExCA I/O window 0 and 1 start-address high-byte register (index 09h, 0Dh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 49h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh; Card A ExCA offset 0Dh

Card B ExCA offset 4Dh Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the start address.

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ExCA I/O window 0 and 1 end-address low-byte register (index 0Ah, 0Eh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 4Ah Register: ExCA Offset: CardBus socket address + 80Eh; Card A ExCA offset 0Eh

Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0

ExCA I/O window 0 and 1 end-address high-byte register (index 0Bh, 0Fh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

I/O window 1 end-address low byte

Card B ExCA offset 4Eh

and 1. The eight bits of these registers correspond to the lower eight bits of the end address.

Card B ExCA offset 4Bh Register: ExCA

I/O window 1 end-address high byte

Offset: CardBus socket address + 80Fh; Card A ExCA offset 0Fh

Card B ExCA offset 4Fh Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

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ExCA memory window 0–4 start-address low-byte register (index 10h, 18h, 20h, 28h, 30h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 50h Register: ExCA memory window 1 start-address low byte Offset: CardBus socket address + 818h; Card A ExCA offset 18h

Card B ExCA offset 58h Register: ExCA memory window 2 start-address low byte Offset: CardBus socket address + 820h; Card A ExCA offset 20h

Card B ExCA offset 60h Register: ExCA memory window 3 start-address low byte

Offset: CardBus socket address + 828h; Card A ExCA offset 28h

Card B ExCA offset 68h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h; Card A ExCA offset 30h

Card B ExCA offset 70h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window start address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address.

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ExCA memory window 0–4 start-address high-byte register (index 11h, 19h, 21h, 29h, 31h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 51h Register: ExCA memory window 1 start-address high byte Offset: CardBus socket address + 819h; Card A ExCA offset 19h

Card B ExCA offset 59h Register: ExCA memory window 2 start-address high byte Offset: CardBus socket address + 821h; Card A ExCA offset 21h

Card B ExCA offset 61h Register: ExCA memory window 3 start-address high byte Offset: CardBus socket address + 829h; Card A ExCA offset 29h

Card B ExCA offset 69h Register: ExCA memory window 4 start-address high byte Offset: CardBus socket address + 831h; Card A ExCA offset 31h

Card B ExCA offset 71h Type: Read/write Default: 00h Size: One byte Description: These registers contain the high nibble of the 16-bit memory window start address for memory

windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register. Refer to Table 58 for a complete description of the register contents.

Table 58. ExCA Memory Window 0–4 Start-Address High-Byte Register (Index 11h, 19h, 21h, 29h, 31h)

BIT SIGNAL TYPE FUNCTION

Data size. Bit 7 controls the memory window data width. This bit is encoded as:

7 DATASIZE R/W

Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel

6 ZEROWAIT R/W

5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 are read/write and have no effect on memory window operation. 3–0 STAHN R/W

Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window start address.

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

82365SL-DF. This bit is encoded as:

0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

16-bit cycles are reduced to equivalent of two ISA cycles.

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ExCA memory window 0–4 end-address low-byte register (index 12h, 1Ah, 22h, 2Ah, 32h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 52h Register: ExCA memory window 1 end-address low byte Offset: CardBus socket address + 81Ah; Card A ExCA offset 1Ah

Card B ExCA offset 5Ah Register: ExCA memory window 2 end-address low byte Offset: CardBus socket address + 822h; Card A ExCA offset 22h

Card B ExCA offset 62h Register: ExCA memory window 3 end-address low byte Offset: CardBus socket address + 82Ah; Card A ExCA offset 2Ah

Card B ExCA offset 6Ah Register: ExCA memory window 4 end-address low byte Offset: CardBus socket address + 832h; Card A ExCA offset 32h

Card B ExCA offset 72h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address.

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ExCA memory window 0–4 end-address high-byte register (index 13h, 1Bh, 23h, 2Bh, 33h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address high byte Type R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 53h Register: ExCA memory window 1 end-address high byte Offset: CardBus socket address + 81Bh; Card A ExCA offset 1Bh

Card B ExCA offset 5Bh Register: ExCA memory window 2 end-address high byte Offset: CardBus socket address + 823h; Card A ExCA offset 23h

Card B ExCA offset 63h Register: ExCA memory window 3 end-address high byte Offset: CardBus socket address + 82Bh; Card A ExCA offset 2Bh

Card B ExCA offset 6Bh Register: ExCA memory window 4 end-address high byte Offset: CardBus socket address + 833h; Card A ExCA offset 33h

Card B ExCA offset 73h Type: Read only, read/write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high nibble of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register. Refer to Table 59 for a complete description of the register contents.

Table 59. ExCA Memory Window 0–4 End-Address High-Byte Register (Index 13h, 1Bh, 23h, 2Bh, 33h)

BIT SIGNAL TYPE FUNCTION

7–6 MEMWS R/W 5–4 RSVD R Reserved. Bits 5–4 are read only and return 0s when read. Writes have no effect. 3–0 ENDHN R/W

Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits.

End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address.

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ExCA memory window 0–4 offset-address low-byte register (index 14h, 1Ch, 24h, 2Ch, 34h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 54h Register: ExCA memory window 1 offset-address low byte Offset: CardBus socket address + 81Ch; Card A ExCA offset 1Ch

Card B ExCA offset 5Ch Register: ExCA memory window 2 offset-address low byte Offset: CardBus socket address + 824h; Card A ExCA offset 24h

Card B ExCA offset 64h Register: ExCA memory window 3 offset-address low byte Offset: CardBus socket address + 82Ch; Card A ExCA offset 2Ch

Card B ExCA offset 6Ch Register: ExCA memory window 4 offset-address low byte Offset: CardBus socket address + 834h; Card A ExCA offset 34h

Card B ExCA offset 74h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window offset address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address.

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ExCA memory window 0–4 offset-address high-byte register (index 15h, 1Dh, 25h, 2Dh, 35h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 offset-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 55h Register: ExCA memory window 1 offset-address high byte Offset: CardBus socket address + 81Dh; Card A ExCA offset 1Dh

Card B ExCA offset 5Dh Register: ExCA memory window 2 offset-address high byte Offset: CardBus socket address + 825h; Card A ExCA offset 25h

Card B ExCA offset 65h Register: ExCA memory window 3 offset-address high byte Offset: CardBus socket address + 82Dh; Card A ExCA offset 2Dh

Card B ExCA offset 6Dh Register: ExCA memory window 4 offset-address high byte Offset: CardBus socket address + 835h; Card A ExCA offset 35h

Card B ExCA offset 75h Type: Read only, read/write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high six bits of the 16-bit memory window offset address for

memory windows 0, 1, 2, 3, and 4. The lower six bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register . Refer to Table 60 for a complete description of the register contents.

Table 60. ExCA Memory Window 0–4 Offset-Address High-Byte Register (Index 15h, 1Dh, 25h, 2Dh, 35h)

BIT SIGNAL TYPE FUNCTION

Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is

7 WINWP R/W

6 REG R/W

5–0 OFFHB R/W

encoded as:

0 = Write operations are allowed (default). 1 = Write operations are not allowed.

Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as:

0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory.

Offset-address high byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window offset address.

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ExCA I/O window 0 and 1 offset-address low-byte register (index 36h, 38h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 76h Register: ExCA I/O window 1 offset-address low byte Offset: CardBus socket address + 838h; Card A ExCA offset 38h

Card B ExCA offset 78h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0

and 1. The eight bits of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0.

ExCA I/O window 0 and 1 offset-address high-byte register (index 37h, 39h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 77h Register: ExCA I/O window 1 offset-address high byte Offset: CardBus socket address + 839h; Card A ExCA offset 39h

Card B ExCA offset 79h Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the offset address.

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ExCA card detect and general-control register (index 16h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O card detect and general control Type R R W R/W R R R/W R Default X X 0 0 0 0 0 0

Register: ExCA card detect and general control Type: Read only, write only, read/write (see individual bit descriptions) Offset: CardBus socket address + 816h; Card A ExCA offset 16h

Card B ExCA offset 56h Default: XX00 0000b Description: This register controls how the ExCA registers for the socket respond to card removal, as well

as reports the status of VS1 complete description of the register contents.

Table 61. ExCA Card Detect and General-Control Register (Index 16h)

BIT SIGNAL TYPE FUNCTION

VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have

7 VS2STAT R

6 VS1STAT R

5 SWCSC W

4 CDRESUME R/W

3–2 RSVD R Reserved. Bits 3–2 are read only and return 0s when read. Writes have no effect.

1 REGCONFIG R/W

0 RSVD R Reserved. Bit 0 is read only and returns 0 when read. Writes have no effect.

a default value.

0 = VS2 1 = VS2

VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have a default value.

0 = VS1 1 = VS1

Software card detect interrupt. If the card detect enable bit in the card status change interrupt configuration register is set, writing a 1 to bit 5 causes a card detect card status change interrupt for the associated card socket. If the card detect enable bit is cleared to 0 in the card status change interrupt configuration register , writing a 1 to the software card detect interrupt bit has no effect. Bit 5 is write only . A read operation of this bit always returns 0. Writing a 1 to this bit also clears it. If bit 2 of the global control register is set, and a 1 is written to clear bit 3 of the ExCA card status change interrupt register, this bit also is cleared.

Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1 and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until the card status change bit in the card status change register is cleared. If this bit is a 0, then the card detect resume functionality is disabled.

0 = Card detect resume disabled (default) 1 = Card detect resume enabled

Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as:

0 = No change to ExCA registers on card removal (default) 1 = Reset ExCA registers on card removal

and VS2 at the PC Card interface. Refer to Table 61 for a

low high

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ExCA global-control register (index 1Eh)

Bit 7 6 5 4 3 2 1 0 Name ExCA global control Type R R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA global control Type: Read only, read/write (see individual bit descriptions) Offset: CardBus socket address + 81Eh; Card A ExCA offset 1Eh

Card B ExCA offset 5Eh Default: 00h Description: This register controls both PC Card sockets and is not duplicated for each socket. The host

interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. Refer to Table 62 for a complete description of the register contents.

Table 62. ExCA Global-Control Register (Index 1Eh)

BIT SIGNAL TYPE FUNCTION

7–5 RSVD R Reserved. Bits 7–5 are is read only and returns 0s when read. Writes have no effect.

Level/edge interrupt mode select – card B. Bit 4 selects the signaling mode for the PCI1251A host interrupt

4 INTMODEB R/W

3 INTMODEA R/W

2 IFCMODE R/W

1 CSCMODE R/W

0 PWRDWN R/W

for card B interrupts. This bit is encoded as:

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

Level/edge interrupt mode select – card A. Bit 3 selects the signaling mode for the PCI1251A host interrupt for card A interrupts. This bit is encoded as:

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA card status change register. This bit is encoded as:

0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit write back of 1.

Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1251A host interrupt for card status changes. This bit is encoded as:

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

Power-down mode select. When bit 0 is set to 1, the PCI1251A is in power-down mode. In power-down mode, the PCI1251A card outputs are 3-stated until an active cycle is executed on the card interface. Following an active cycle, the outputs are again 3-stated. The PCI1251A still receives DMA requests, functional interrupts, and/or card status change interrupts; however , an actual card access is required to wake up the interface. This bit is encoded as:

0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled.

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ExCA memory window 0–4 page register (index 40h, 41h, 42h, 43h, 44h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA memory window 0–4 page Type: Read/write Offset: CardBus socket address + 840h 841h, 842h, 843h, 844h Default: 00h Description: The upper eight bits of a 4-byte PCI memory address are compared to the contents of this

register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. These registers are only accessible when the ExCA registers are memory mapped, i.e., these registers can not be accessed using the index/data I/O scheme.

CardBus socket registers (functions 0 and 1)

The PCMCIA CardBus specification requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI1251A provides the CardBus socket/ExCA base address register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate base address register for accessing the CardBus socket registers (see Figure 18). Table 63 gives the location of the socket registers in relation to the CardBus socket/ExCA base address.

The PCI1251A implements an additional register at offset 20h that provides power management control for the socket.

Host

PCI1251A Configuration Registers

CardBus Socket/ExCA Base Address

16-Bit Legacy-Mode Base Address

NOTE: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1.

Offset

10h

44h

Memory Space

CardBus Socket A

Registers

ExCA

Registers

Card A

Offset

00h

20h

800h

844h

Host

Memory Space

CardBus Socket B

Registers

ExCA

Registers

Card B

Figure 18. Accessing CardBus Socket Registers Through PCI Memory

Offset

00h

20h

800h

844h

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CardBus socket registers (functions 0 and 1) (continued)

Table 63. CardBus Socket Registers

Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket Power Management 20h

socket event register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket event Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Socket event Type: Read only, read/write (see individual bit descriptions) Offset: CardBus socket address + 00h Default: 0000 0000h Description: The socket event register indicates a change in socket status has occurred. These bits do not

indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software must clear this register before enabling interrupts. If it is not cleared, when interrupts are enabled an interrupt is generated (but not masked) based on any bit set. Refer to Table 64 for a complete description of the register contents.

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Table 64. Socket Event Register

BIT SIGNAL TYPE FUNCTION

31–4 RSVD R Reserved. Bits 31–4 are read only and return 0s when read.

3 PWREVENT R/W

2 CD2EVENT R/W

1 CD1EVENT R/W

0 CSTSEVENT R/W

socket mask register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket mask Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Power cycle. Bit 3 is set when the PCI1251A detects that the PWRCYCLE bit in the socket present-state register has changed. This bit is cleared by writing a 1.

CCD2. Bit 2 is set when the PCI1251A detects that the CDETECT2 field in the socket present-state register has changed. This bit is cleared by writing a 1.

CCD1. Bit 3 is set when the PCI1251A detects that the CDETECT1 field in the socket present-state register has changed. This bit is cleared by writing a 1.

CSTSCHG. Bit 0 is set when the CARDSTS field in the socket present-state register has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1.

Register: Socket mask Type: Read only, read/write (see individual bit descriptions) Offset: CardBus socket address + 04h Default: 0000 0000h Description: The socket mask register allows software to control the CardBus card events that generate a

status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register. Refer to Table 65 for a complete description of the register contents.

Table 65. Socket Mask Register

BIT SIGNAL TYPE FUNCTION

31–4 RSVD R Reserved. Bits 31–4 are read only and return 0s when read.

Power cycle. Bit 3 masks the PWRCYCLE bit in the socket present state register from causing a status

3 PWRMASK R/W

2–1 CDMASK R/W

0 CSTSMASK R/W

change interrupt.

0 = PWRCYCLE event does not cause CSC interrupt (default). 1 = PWRCYCLE event causes CSC interrupt.

Card detect mask. Bits 2–1 mask the CDETECT1 and CDETECT2 bits in the socket present-state register from causing a CSC interrupt.

00 = Insertion/removal does not cause CSC interrupt (default). 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal causes CSC interrupt.

CSTSCHG mask. Bit 0 masks the CARDSTS field in the socket present-state register from causing a CSC interrupt.

0 = CARDSTS event does not cause CSC interrupt (default). 1 = CARDSTS event causes CSC interrupt.

100

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TEXAS INSTRUMENTS PCI1251A Technical data

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