TEXAS INSTRUMENTS PCI1225 Technical data

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PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

 PCI Bus Power Management Interface

Specification 1.0 Compliant

 ACPI 1.0 Compliant  Fully Compatible With the Intel 430TX

(Mobile Triton II) Chipset

 Packaged in a 208-Pin Low-Profile QFP

(PDV) or GHK High Density Ball Grid Array (BGA)

 PCI Local Bus Specification Revision 2.2

Compliant

 1997 PC Card Standard Compliant  PC 99 Compliant  3.3-V Core Logic With Universal PCI

Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments

 Mix-and-Match 5-V/3.3-V 16-bit PC Cards

and 3.3-V CardBus Cards

 Supports Two PC Card or CardBus Slots

With Hot Insertion and Removal

 Uses Serial Interface to TI TPS2202/2206

Dual-Slot PC Card Power Switch

 Supports Burst Transfers to Maximize Data

Throughput on the PCI Bus and CardBus Bus

 Supports Parallel PCI Interrupts, Parallel

ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts

 Serial EEPROM Interface for Loading

Subsystem ID and Subsystem Vendor ID

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T erminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Name/Terminal Number Sort Tables 6. . . . . . . . . . . . . . . . . . . . . . . . . .

T erminal Functions 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Sequencing 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Rail Voltages 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Component Interconnect (PCI) Interface 23. . . . . . . . . . . . . . . .

PC Card Applications 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Bus Interface 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Controller Programming Model 45. . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Configuration Registers (Functions 0 and 1) 46. . . . . . . . . . . . . . . . . . .

ExCA Compatibility Registers (Functions 0 and 1) 83. . . . . . . . . . . . . . . . . .

 Pipelined Architecture Allows Greater Than

130-MBps Throughput From CardBus-to-PCI and From PCI-to-CardBus

 Supports up to Five General-Purpose I/Os  Programmable Output Select for CLKRUN  Multifunction PCI Device With Separate

Configuration Space for Each Socket

 Five PCI Memory Windows and T wo I/O

Windows Available for Each R2 Socket

 Two I/O Windows and Two Memory

Windows Available to Each CardBus Socket

 Exchangeable Card Architecture (ExCA)

Compatible Regesters Are Mapped in Memory and I/O Space

 Intel 82365SL-DF Register Compatible  Supports Distributed DMA (DDMA) and

PC/PCI DMA

 Supports 16-Bit DMA on Both PC Card

Sockets

 Supports Ring Indicate, SUSPEND, PCI

CLKRUN, and CardBus CCLKRUN

 LED Activity Pins  Supports PCI Bus Lock (LOCK)  Advanced Submicron, Low-Power CMOS

T echnology

CardBus Socket Registers (Functions 0 and 1) 106. . . . . . . . . . . . . . . . . . . . . .

Distributed DMA (DDMA) Registers 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 124. . . . . . . . . . . . . . . . . . . . . . .

PC Card Cycle Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements (Memory Cycles) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements (I/O Cycles) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics (Miscellaneous 127. . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Parameter Measurement Information 128. . . . . . . . . . . . . . . . . . . . . . .

Mechanical Data 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

description

The TI PCI1225 is a high-performance PCI-to-PC Card controller that supports two independent card sockets compliant with the 1997 PC Card Standard. The PCI1225 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2 and defines the new 32-bit PC Card (CardBus), capable of full 32-bit data transfers at 33 MHz. The PCI1225 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1225 is compliant with the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1225 is also compliant with the latest

Management Interface Specification

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1225 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1225 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architacture provide an unsurpassed performance level with sustained bursting. The PCI1225 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1225, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.

PCI Bus Power

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

Unused PCI1225 inputs must be pulled up using a 43-k resistor.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

system block diagram

A simplified block diagram of the PCI1225 is provided below. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface terminals include multifunction terminals: SUSPEND

, RI_OUT/PME (power management control signal), and SPKROUT.

PCI Bus

INTA

Activity LEDs

INTB

Interrupt

Controller

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed

video signals to the VGA controller and audio subsystem.

PCI1225

68 68

IRQSER

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

IRQ2–15

VGA

Controller

Audio

Subsystem

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

terminal assignments

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30 AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17 AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

SUSPEND

GND

MFUNC0

DATA

SPKROUT

LATCH

CLOCK

152

151

150

149

VCCI

148

MFUNC1

154

153

156

155

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_CAD31

A_CAD30

A_RSVD

146

145

147

A_CAD28

A_CAD29

142

144

143

A_CCD2

A_CAD27

A_CCLKRUN

140

139

141

A_CAUDIO

A_CSTSCHG

138

137

A_CINT

A_CSERR

A_CVS1

134

136

135

A_CAD25

A_CAD26

A_CAD24

132

131

133

PCI1225 CorePCI

A_CC/BE3

A_CAD23

GND

128

130

129

Card A

A_CAD21

A_CAD22

A_CREQ

126

125

127

A_CRST

124

A_CAD20

A_CAD19

A_CVS2

122

121

123

Card B

CCA

A_CAD18

119

120

A_CC/BE2

A_CAD17

118

117

A_CFRAME

A_CTRDY

A_CIRDY

114

113

116

115

A_CCLKVA_CDEVSEL

112

A_CGNT

111

110

A_CSTOP

A_CBLOCK

A_CPERR

108

107

109

A_RSVD

A_CPAR

105 104

103 102 101 100

51 106

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

A_CC/BE1 A_CAD16 A_CAD14 A_CAD15 A_CAD12 A_CAD13 A_CAD11 A_CAD10 GND A_CAD9 A_CC/BE0 A_CAD8 A_CAD7 A_RSVD A_CAD5 A_CAD6 A_CAD3 A_CAD4

CC A_CAD1 A_CAD2 A_CAD0 A_CCD1 B_CAD31 B_RSVD B_CAD30 B_CAD29 B_CAD28 B_CAD27 GND B_CCD2 B_CCLKRUN B_CSTSCHG B_CAUDIO B_CSERR B_CINT B_CVS1 B_CAD26 B_CAD25 B_CAD24 V

CC B_CC/BE3

B_CAD23 B_CREQ B_CAD22 B_CAD21 B_CRST B_CAD20 B_CVS2 B_CAD19 B_CAD18 B_CAD17

CCP

AD10

AD9

AD8

AD7

C/BE0

AD6

AD5

AD3

AD1

AD0

AD2

AD4

GND

B_CAD0

B_CAD2

B_CCD1

B_CAD1

B_CAD4

B_CAD3

GND

B_CAD6

B_CAD5

B_CAD7

B_RSVD

B_CAD8

B_CAD9

B_CAD10

B_CC/BE0

B_CAD11

B_CAD13

B_CAD14

B_CAD12

B_CAD15

CCB

B_CAD16

B_CC/BE1

B_CPAR

B_RSVD

B_CBLOCK

GND

B_CSTOP

B_CPERR

B_CCLK

B_CGNT

B_CDEVSEL

B_CIRDY

B_CTRDY

B_CFRAME

B_CC/BE2

PCI-to-CardBus Terminal Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

terminal assignments (continued)

PDV LOW-PROFILE QUAD FLAT PACKAGE

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

TOP VIEW

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30 AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17

AD16

C/BE2

FRAME

GND IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

A_D10

A_D2

146

147

A_D9

A_D1

144

145

143

A_D8

A_D0

142

141

A_CD2

A_WP(IOIS16)

140

139

A_BVD1(STSCHG/RI)

A_READY(IREQ)

A_WAIT

A_A0

A_VS1

A_A2

136

135

134

133

A_A1

132

131

A_BVD2(SPKR)

138

137

PCI1225 CorePCI

A_REG

GND

130

129

Card A

A_A3

128

A_INPACK

127

A_A4

126

A_A5

125

CCI

SPKROUT

GND

MFUNC0

DATA

LATCH

CLOCK

152

151

150

149

148

SUSPEND

MFUNC1

154

153

156

155

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_A6

A_RESET

A_VS2

122

124

123

Card B

CCA

A_A25

120

121

A_A7

119

A_A24

118

A_A23

A_A12

116

117

A_A22

A_A15

114

115

A_A16VA_A21

112

113

111

A_A20

A_WE

110

109

A_A19

A_A14

108

107

A_A18

A_A13

105

104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

51 106

A_A8 A_A17 A_A9 A_IOWR A_A11 A_IORD A_OE A_CE2 GND A_A10 A_CE1 A_D15 A_D7 A_D14 A_D6 A_D13 A_D5 A_D12

CC A_D4 A_D11 A_D3 A_CD1 B_D10 B_D2 B_D9 B_D1 B_D8 B_D0 GND B_CD2 B_WP(IOIS16) B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A0 B_A1 B_A2 V

CC B_REG B_A3 B_INPACK B_A4 B_A5 B_RESET B_A6

B_VS2 B_A25 B_A7 B_A24

CCP

AD9

AD10

AD8

AD7

C/BE0

AD4

AD6

AD5

AD3

AD1

AD0

AD2

GND

B_D3

B_CD1

B_D11

B_D4

B_D5

B_D12

GND

B_D6

B_D13

B_D7

B_D14

B_D15

B_CE1

B_A10

B_CE2

B_OE

B_IORD

B_A11

B_IOWR

B_A9

CCB

B_A17

B_A8

B_A18

B_A13

B_A19

GND

B_A14

B_WE

B_A20

B_A21

B_A16

B_A15

B_A22

B_A23

B_A12

PCI-to-PC Card (16-Bit) Terminal Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

terminal assignments (continued)

V U T R P N

L K J H G F E D C B A

GHK PLASTIC BALL GRID ARRAY

BOTTOM VIEW

810

13141511

1917

signal names and terminal assignments

Table 1 and Table 2 show the terminal assignments for the CardBus PC Card; Table 3 and Table 4 show the terminal assignments for the 16-bit PC Card; Table 1 and Table 3 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the associated GHK package terminal number; and Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and its associated terminal numbers.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TERM. NO.

SIGNAL NAME

GHK PDV

D1 1 A4 208 E6 206 C6 202

F7 198 E8 194 A8 190 B9 186

C10 182 E11 178 A12 174 A13 170 A14 166 A15 162 E14 159 C15 158 A16 157

E3 2 C5 207 B5 205 A5 203 A6 199 A7 195 B8 191 C9 187

E10 183 F11 179 A11 175 E12 171 F12 167 C14 163 F13 160 E17 155 D19 156

F5 3 G6 4 E2 5

F6 204 B6 200 B7 196 C8 192

F9 188

F10 184 A10 180 B11 176 C12 172 C13 168 B14 164 B15 161 E18 153 F15 154

E1 6

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

T able 1. CardBus PC Card Signal Names by GHK/PDV Terminal Number

CCP

AD12 AD13 PAR STOP GND AD17 AD20 IDSEL V

CCP

AD28 AD31 PRST C/BE3 MFUNC4 MFUNC3 MFUNC2 AD10 GND AD14 C/BE1 PERR IRDY AD16 V

AD23 AD24 V

AD30 GND RI_OUT/PME MFUNC5 MFUNC1 SUSPEND AD9 AD8 C/BE0 AD15 SERR TRDY C/BE2 AD19 AD22 PCLK AD27 AD11 GNT V

MFUNC6/CLKRUN GND MFUNC0 AD7

TERM. NO.

GHK PDV

F3 7 F2 8 E7 201 C7 197 F8 193 E9 189

A9 185 B10 181 C11 177 B12 173 B13 169 E13 165 G15 149 F14 152 E19 151 F17 150

F1 10

H6 11

G3 12

G5 9 G17 145 F18 148 F19 147 G14 146

G1 14

H5 15 H3 16

G2 13 H14 141 G18 144 G19 143 H15 142

H1 18 J1 19 J2 20

H2 17 J15 137 H17 140 H18 139 H19 138

J5 22

J6 23

K1 24

J3 21 J19 133 J14 136 J17 135 J18 134

K3 26

K5 27

K6 28

K2 25

AD6 V

DEVSEL FRAME AD18 AD21 GND AD26 AD29 REQ AD25 SPKROUT DATA CLOCK LATCH AD4 AD3 AD2 AD5 A_CAD30 V

CCI

A_CAD31 A_RSVD AD1 AD0 B_CCD1 GND A_CAD27 A_CAD29 V

A_CAD28 B_CAD2 B_CAD1 B_CAD4 B_CAD0 A_CAUDIO A_CCD2 A_CCLKRUN A_CSTSCHG GND B_CAD6 B_CAD5 B_CAD3 A_CAD26 A_CSERR A_CINT A_CVS1 B_CAD7 B_CAD8 B_CC/BE0 B_RSVD

TERM. NO.

GHK PDV

K18 129 K14 132 K15 131 K17 130

L2 30 L3 31 L6 32

L1 29 L17 125 K19 128 L14 127 L15 126

M1 34 M2 35 M3 36

L5 33

M18 121

L18 124 L19 123

M19 122

M5 38

N1 39

N2 40

M6 37

N18 117 M17 120 M15 119

N19 118

N6 42 P1 43 P2 44

N3 41 N15 113 N17 116

M14 115

P19 114

P3 46

R1 47

P6 48

N5 45

R7 61

V7 65

V8 69

U9 73 V10 77

W11 81

R11 85 P12 89 U13 93 R13 97 P18 112 P17 111

GND A_CAD25 A_CAD24 A_CC/BE3 B_CAD10 V

B_CAD11 B_CAD9 A_CAD21 A_CAD23 A_CREQ A_CAD22 B_CAD12 B_CAD15 B_CAD14 B_CAD13 A_CAD19 A_CRST A_CAD20 A_CVS2 V

CCB

B_CC/BE1 B_RSVD B_CAD16 A_CC/BE2 V

CCA

A_CAD18 A_CAD17 B_CBLOCK B_CPERR GND B_CPAR V

A_CFRAME A_CIRDY A_CTRDY B_CGNT B_CDEVSEL B_CCLK B_CSTOP B_CREQ B_CAD24 B_CINT B_CCLKRUN B_CAD28 B_CAD31 A_CAD1 A_CAD6 A_CAD8 A_CAD10 A_CCLK A_CDEVSEL

PCI1225 GHK/PDV

TERM. NO.

GHK PDV

R19 110

P5 50

R2 49

V5 57

V6 60 U7 64 U8 68

V9 72

W10 76

P10 80 P11 84 U12 88 V13 92 V14 96 P14 100 R18 109 N14 108 P15 107

T1 52 R3 51

P7 56 U6 59

P8 63 R8 67 W9 71

P9 75

R10 79 U11 83

V12 87 W13 91 W14 95 W15 99

V15 101

U15 103

R17 106

W4 53 U5 54 R6 55 W5 58 W6 62 W7 66 W8 70

R9 74 U10 78 V11 82

W12 86

R12 90 P13 94 U14 98 R14 102

W16 104

T19 105

A_CGNT B_CIRDY B_CTRDY B_CAD20 B_CAD22 V

B_CVS1 B_CSTSCHG B_CAD27 B_RSVD A_CAD2 A_CAD3 A_CAD7 GND A_CAD12 A_CSTOP A_CPERR A_CBLOCK B_CC/BE2 B_CFRAME B_CVS2 B_CAD21 B_CC/BE3 B_CAD26 B_CAUDIO GND B_CAD30 A_CAD0 A_CAD4 A_RSVD A_CAD9 A_CAD13 A_CAD15 A_CAD16 A_CPAR B_CAD17 B_CAD18 B_CAD19 B_CRST B_CAD23 B_CAD25 B_CSERR B_CCD2 B_CAD29 A_CCD1 V

A_CAD5 A_CC/BE0 A_CAD11 A_CAD14 A_CC/BE1 A_RSVD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 2. CardBus PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

A_CAD0 A_CAD1 A_CAD2 A_CAD3 A_CAD4 A_CAD5 A_CAD6 A_CAD7 A_CAD8 A_CAD9 A_CAD10 A_CAD11 A_CAD12 A_CAD13 A_CAD14 A_CAD15 A_CAD16 A_CAD17 A_CAD18 A_CAD19 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD28 A_CAD29 A_CAD30 A_CAD31 A_CAUDIO A_CBLOCK A_CC/BE0 A_CC/BE1 A_CC/BE2 A_CC/BE3 A_CCD1 A_CCD2 A_CCLK A_CCLKRUN A_CDEVSEL A_CFRAME A_CGNT A_CINT A_CIRDY A_CPAR A_CPERR A_CREQ A_CRST A_CSERR

TERM. NO.

GHK PDV

U11 83 R11 85 P11 84 U12 88 V12 87 R12 90 P12 89 V13 92 U13 93

W14 95

R13 97 U14 98 P14 100

W15 99

R14 102 V15 101 U15 103

N19 118 M15 119 M18 121

L19 123

L17 125

L15 126 K19 128 K15 131 K14 132

J19 133 H14 141 H15 142 G18 144 G17 145

F19 147

J15 137 P15 107 P13 94

W16 104

N18 117 K17 130

V11 82 H17 140 P18 112 H18 139 P17 111 N17 116 R19 110

J17 135 M14 115 R17 106 N14 108

L14 127

L18 124

J14 136

SIGNAL NAME

A_CSTOP A_CSTSCHG A_CTRDY A_CVS1 A_CVS2 A_RSVD A_RSVD A_RSVD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 B_CAD0 B_CAD1 B_CAD2 B_CAD3 B_CAD4 B_CAD5 B_CAD6 B_CAD7 B_CAD8 B_CAD9 B_CAD10 B_CAD11

TERM. NO.

GHK PDV

R18 109 H19 138 P19 114

J18 134

M19 122

G14 146

W13 91

T19 105

H5 15 G1 14 G3 12

H6 11

F1 10 G5 9

F2 8

E1 6 G6 4

F5 3

E3 2

C12 172

A4 208

E6 206

B5 205

F6 204

B8 191

A8 190

E9 189

F9 188

B9 186

A9 185

F10 184 E10 183

F11 179 E13 165 C11 177 B11 176 A12 174 B12 173 E12 171 A13 170

H2 17

J1 19

H1 18

J3 21 J2 20

K1 24

J6 23 K3 26 K5 27 L1 29 L2 30 L6 32

SIGNAL NAME

B_CAD12 B_CAD13 B_CAD14 B_CAD15 B_CAD16 B_CAD17 B_CAD18 B_CAD19 B_CAD20 B_CAD21 B_CAD22 B_CAD23 B_CAD24 B_CAD25 B_CAD26 B_CAD27 B_CAD28 B_CAD29 B_CAD30 B_CAD31 B_CAUDIO B_CBLOCK B_CC/BE0 B_CC/BE1 B_CC/BE2 B_CC/BE3 B_CCD1 B_CCD2 B_CCLK B_CCLKRUN B_CDEVSEL B_CFRAME B_CGNT B_CINT B_CIRDY B_CPAR B_CPERR B_CREQ B_CRST B_CSERR B_CSTOP B_CSTSCHG B_CTRDY B_CVS1 B_CVS2 B_RSVD B_RSVD B_RSVD C/BE0 C/BE1 C/BE2 C/BE3

TERM. NO.

GHK PDV

M1 34

L5 33 M3 36 M2 35 M6 37 W4 53

U5 54 R6 55 V5 57 U6 59 V6 60

W6 62

V7 65

W7 66

R8 67

W10 76

V10 77 U10 78 R10 79

W11 81

W9 71

N6 42 K6 28 N1 39 T1 52 P8 63 H3 16 R9 74 P6 48 U9 73 R1 47 R3 51 P3 46 V8 69 P5 50 N3 41 P1 43

R7 61 W5 58 W8 70

N5 45

V9 72

R2 49

U8 68

P7 56

K2 25

N2 40

P10 80

E2 5

A5 203

C8 192

A15 162

SIGNAL NAME

CLOCK DATA DEVSEL FRAME GND GND GND GND GND GND GND GND GND GND GND GNT IDSEL IRDY LATCH MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6/CLKRUN PAR PCLK PERR PRST REQ RI_OUT/PME SERR SPKROUT STOP SUSPEND TRDY V

CCA

CCB

CCI

CCP

PIN NO.

GHK PDV

E19 151 F14 152

C7 197 F8 193 E8 194

C5 207 F12 167 E18 153 B10 181

G2 13

J5 22

K18 129

P2 44 V14 96

P9 75 C13 168 C10 182

A7 195 F17 150 F15 154 E17 155 A16 157 C15 158 E14 159 F13 160 B15 161

C6 202 A10 180

A6 199 A14 166 B13 169 C14 163

B6 200 G15 149

F7 198 D19 156

B7 196

C9 187 A11 175 B14 164

F3 7

E7 201 G19 143

L3 31 N15 113

U7 64

W12 86

M17 120

M5 38 F18 148

D1 1 E11 178

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PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number

TERMINAL NO.

GHK PDV

D1 1 V A4 208 AD12 F2 8 AD6 K14 132 A_A1 E6 206 AD13 E7 201 V C6 202 PAR C7 197 DEVSEL K17 130 A_REG F7 198 STOP F8 193 FRAME L2 30 B_CE2 E8 194 GND E9 189 AD18 L3 31 V A8 190 AD17 A9 185 AD21 L6 32 B_OE B9 186 AD20 B10 181 GND L1 29 B_A10

C10 182 IDSEL C11 177 AD26 L17 125 A_A5

E11 178 V A12 174 AD28 B13 169 REQ L14 127 A_INPACK A13 170 AD31 E13 165 AD25 L15 126 A_A4 A14 166 PRST G15 149 SPKROUT M1 34 B_A11 A15 162 C/BE3 F14 152 DATA M2 35 B_IOWR E14 159 MFUNC4 E19 151 CLOCK M3 36 B_A9 C15 158 MFUNC3 F17 150 LATCH L5 33 B_IORD A16 157 MFUNC2 F1 10 AD4 M18 121 A_A25

E3 2 AD10 H6 11 AD3 L18 124 A_RESET C5 207 GND G3 12 AD2 L19 123 A_A6 B5 205 AD14 G5 9 AD5 M19 122 A_VS2 A5 203 C/BE1 G17 145 A_D9 M5 38 V A6 199 PERR F18 148 V A7 195 IRDY F19 147 A_D10 N2 40 B_A18 B8 191 AD16 G14 146 A_D2 M6 37 B_A17 C9 187 V

E10 183 AD23 H5 15 AD0 M17 120 V

F11 179 AD24 H3 16 B_CD1 M15 119 A_A7

A11 175 V E12 171 AD30 H14 141 A_D0 N6 42 B_A19 F12 167 GND G18 144 A_D1 P1 43 B_A14 C14 163 RI_OUT/PME G19 143 V F13 160 MFUNC5 H15 142 A_D8 N3 41 B_A13 E17 155 MFUNC1 H1 18 B_D11 N15 113 V D19 156 SUSPEND J1 19 B_D4 N17 116 A_A23

F5 3 AD9 J2 20 B_D12 M14 115 A_A15 G6 4 AD8 H2 17 B_D3 P19 114 A_A22 E2 5 C/BE0 J15 137 A_BVD2(SPKR) P3 46 B_WE F6 204 AD15 H17 140 A_CD2 R1 47 B_A21 B6 200 SERR H18 139 A_WP(IOIS16) P6 48 B_A16 B7 196 TRDY H19 138 A_BVD1(STSCHG/RI) N5 45 B_A20 C8 192 C/BE2 J5 22 GND R7 61 B_INPACK

F9 188 AD19 J6 23 B_D13 V7 65 B_A2 F10 184 AD22 K1 24 B_D6 V8 69 B_READY(IREQ) A10 180 PCLK J3 21 B_D5 U9 73 B_WP(IOIS16)

B11 176 AD27 J19 133 A_A0 V10 77 B_D8 C12 172 AD11 J14 136 A_WAIT W11 81 B_D10 C13 168 GNT J17 135 A_READY(IREQ) R11 85 A_D4 B14 164 V B15 161 MFUNC6 K3 26 B_D7 U13 93 A_D15 E18 153 GND K5 27 B_D15 R13 97 A_CE2 F15 154 MFUNC0 K6 28 B_CE1 P18 112 A_A16

SIGNAL NAME

CCP

TERMINAL NO.

GHK PDV

F3 7 V

B12 173 AD29 K19 128 A_A3

G1 14 AD1 N18 117 A_A12

G2 13 GND N19 118 A_A24

J18 134 A_VS1 P12 89 A_D13

SIGNAL NAME

CCI

TERMINAL NO.

GHK PDV

K18 129 GND

K15 131 A_A2

CCB

N1 39 B_A8

CCA

P2 44 GND

SIGNAL NAME

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PCI1225 GHK/PDV

SIGNAL NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number (Continued)

TERMINAL NO.

GHK PDV

E1 6

R19 110

P5 R2 V5 V6 U7 U8 V9

W10

P10 P11 U12 V13 V14 P14 R18 109 N14 108 P15 107

50 B_A15 49 B_A22 57 B_A6 60 B_A4 64 V 68 B_VS1 72 B_BVD1(STSCHG/RI) 76 B_D0 80 B_D2 84 A_D11 88 A_D5 92 A_D7 96 GND

100 A_A11

A_A0 A_A1 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 A_A9 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19

SIGNAL NAME

AD7 A_WE

A_A20 A_A14 A_A19

TERMINAL

NO.

GHK PDV

K2 25

T1 R3 P7 U6 P8 R8

P9 R10 U11 V12

W13 W14 W15

V15 U15 R17 106

52 B_A12 51 B_A23 56 B_VS2 59 B_A5 63 B_REG 67 B_A0 71 B_BVD2(SPKR) 75 GND 79 B_D9 83 A_D3 87 A_D12 91 A_D14 95 A_A10

99 A_IORD 101 A_IOWR 103 A_A17

53 B_A24

SIGNAL NAME

B_D14

A_A13

TERMINAL

NO.

GHK PDV

P17 111

R6 W5 W6 W7 W8

U10

V11

W12

R12 P13 U14 R14

W16

T19 105

54 B_A7 55 B_A25 58 B_RESET 62 B_A3 66 B_A1 70 B_WAIT 74 B_CD2 78 B_D1 82 A_CD1 86 V 90 A_D6 94 A_CE1

98 A_OE 102 A_A9 104 A_A8

Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically

TERMINAL NO.

GHK PDV

J19 133 K14 132 K15 131 K19 128 L15 126 L17 125

L19 123 M15 119 W16

R14

W14

P14 N18 117 R17 106 N14 108

M14 115

P18 112 U15 T19 105 P15 107

104 A_CD1 102 A_CD2

95 A_CE1

100 A_CE2

103 A_D5

A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 A_BVD1(STSCHG/RI) A_BVD2(SPKR)

A_D0 A_D1 A_D2 A_D3 A_D4

A_D6 A_D7

TERMINAL NO.

GHK PDV

R18 109 P17 111 P19 114 N17 116 N19 118

M18 121

H19 138

J15 137 V11 H17 140 P13 R13 H14 141 G18 144 G14 146 U11 R11 U12 R12 V13

82 A_INPACK

94 A_IOWR 97 A_OE

83 A_VS1 85 A_VS2 88 A_WAIT 90 A_WE 92 A_WP(IOIS16)

A_D8 A_D9 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15

A_IORD

A_READY(IREQ) A_REG A_RESET

SIGNAL NAME

A_A21

A_A18

TERMINAL NO.

GHK PDV

H15 142 G17 145 F19 147 P11 V12 P12

W13

U13 L14 127

W15

V15 U14

J17 135 K17 130 L18 124

J18 134

M19 122

J14 136 R19 110 H18 139

84 87 89 91 93

101

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PCI1225 GHK/PDV

SIGNAL NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 B_A0 B_A1 B_A2 B_A3 B_A4 B_A5 B_A6 B_A7 B_A8 B_A9 B_A10 B_A11 B_A12 B_A13 B_A14 B_A15 B_A16 B_A17

TERMINAL NO.

GHK PDV

H5 15 G1 14 G3 12 H6 11 F1 10 G5 9 F2 8 E1 6 G6 4 F5 3 E3 2

C12 172

A4 208 E6 206 B5 205 F6 204 B8 191 A8 190 E9 189 F9 188 B9 186

A9 185 F10 184 E10 183 F11 179 E13 165 C11 177 B11 176 A12 174 B12 173 E12 171 A13 170

67 B_IOWR 66 B_OE 65 B_READY(IREQ) 62 B_REG 60 B_RESET 59 B_VS1 57 B_VS2 54 B_WAIT 39 B_WE 36 B_WP(IOIS16) 29 C/BE0 34 C/BE1 52 C/BE2 41 C/BE3 43 CLOCK 50 DATA 48 DEVSEL 37 FRAME

B_A18 B_A19 B_A20 B_A21 B_A22 B_A23 B_A24 B_A25 B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_CD1 B_CD2 B_CE1 B_CE2 B_D0 B_D1 B_D2 B_D3 B_D4 B_D5 B_D6 B_D7 B_D8 B_D9 B_D10 B_D11 B_D12 B_D13 B_D14 B_D15 B_INPACK B_IORD

TERMINAL NO.

GHK PDV

N2 N6 N5 R1 R2 R3

R6 V9

H3 16 R9 K6 L2

W10

U10 P10

H2 17

J3 21 K1 K3

V10 R10

W11

H1 18

J6 K2 K5 R7 L5

L6 V8 P8

U8 P7

P3 U9 E2 5 A5 203 C8 192

A15 162 E19 151 F14 152

C7 197 F8 193

40 GND 42 GND 45 GND 47 GND 49 GND 51 GND 53 GND 55 GND 72 GND 71 GND

74 GNT 28 IDSEL 30 IRDY 76 LATCH 78 MFUNC0 80 MFUNC1

19 MFUNC3

24 MFUNC5 26 MFUNC6 77 PAR 79 PCLK 81 PERR

20 REQ 23 RI_OUT/PME 25 SERR 27 SPKROUT 61 STOP 33 SUSPEND 35 TRDY 32 V 69 V 63 V 58 V 68 V 56 V 70 V 46 V 73 V

GND

MFUNC2

MFUNC4

PRST

CC CC CC CC CC CC CC CC CC

CCA

CCB

CCI

CCP

TERMINAL NO.

GHK PDV

E8 194

C5 207 F12 167 E18 153 B10 181

G2 13

J5 K18 129

P2 V14

P9 C13 168 C10 182

A7 195 F17 150 F15 154 E17 155 A16 157 C15 158 E14 159 F13 160 B15 161

C6 202 A10 180

A6 199 A14 166 B13 169 C14 163

B6 200 G15 149

F7 198 D19 156

B7 196 A11 175

C9 187 B14 164

F3 7

E7 201 G19 143

L3 N15 113

W12

M17 120

M5 F18 148

D1 1 E11 178

44 96 75

64 86

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PCI1225 GHK/PDV

FUNCTION

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

power supply

TERMINAL

NAME PDV NUMBER GHK NUMBER

GND

CCA

CCB

CCI

CCP

13, 22, 44, 75, 96, 129, 153,

167, 181, 194, 207

7, 31, 64, 86, 113, 143, 164,

175, 187, 201

120 M17

38 M5

148 F18

1, 178 D1, E11 Rail voltage for PCI signaling (5 V or 3.3 V)

G2, J5, P2, P9, V14, K18, E18,

F12, B10, E8, C5

F3, L3, U7, W12, N15, G19,

B14, A11, C9, E7

Device ground terminals

Power supply terminal for core logic (3.3 V) Rail voltage for PC Card A interface. Indicates Card A

signaling environment (5 V or 3.3 V) Rail voltage for PC Card B interface. Indicates Card B

signaling environment (5 V or 3.3 V) Rail voltage for interrupt subsystem interface and

miscellaneous I/O (5 V or 3.3 V)

FUNCTION

PC Card power switch

TERMINAL

NAME

CLOCK 151 E19 I/O

DATA 152 F14 O

LATCH 150 F17 O

NUMBER

PDV GHK

TYPE

PCI system

TERMINAL

NAME

PCLK 180 A10 I

PRST

NUMBER

PDV GHK

166 A14 I

TYPE

I/O

Three-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1225 output by using the P2CCLK bit in the system control register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz.

If a system design defines this terminal as an output, then this terminal requires an external pull down resistor. The frequency of the PCI1225 output CLOCK is derived from dividing the PCI CLK by 36.

Three-line power switch data. DATA is used to serially communicate socket power control information to the power switch.

Three-line power switch latch. LATCH is asserted by the PCI1225 to indicate to the PC Card power switch that the data on the DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface.

I/O

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1225 to place all output buffers in a high-impedance state and reset all internal registers. When PRST completely nonfunctional. After PRST

When SUSPEND registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

and PRST are asserted, the device is protected from PRST clearing the internal

FUNCTION

is asserted, the device is

is deasserted, the PCI1225 is in its default state.

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PCI address and data

NAME

TYPE

TERMINAL

NUMBER

PDV GHK

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR 202 C6 I/O

170 171 173 174 176 177 165 179 183 184 185 186 188 189 190 191 204 205 206 208 172

2 3 4 6 8 9

11 12 14 15

162 192 203

A13 E12 B12 A12 B11 C11 E13 F11 E10 F10

A9 B9 F9 E9 A8 B8 F6 B5 E6 A4

C12

E3 F5

E1 F2

F1 H6 G3 G1 H5

A15

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other

I/O

destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. C/BE0 C/BE2

applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PCI bus parity. In all PCI bus read and write cycles, the PCI1225 calculates even parity across the AD31–AD0 and C/BE3 indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator . A compare error results in the assertion of a parity error (PERR

–C/BE0 buses. As an initiator during PCI cycles, the PCI1225 outputs this parity

FUNCTION

–C/BE0 define the bus command. During the data

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8),

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PCI1225 GHK/PDV

NAME

TYPE

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

PCI interface control

TERMINAL

NUMBER

PDV GHK

DEVSEL

FRAME

GNT

IDSEL 182 C10 I

IRDY

PERR REQ

SERR

STOP

TRDY

197 C7 I/O

193 F8 I/O

168 C13 I

195 A7 I/O

199 A6 I/O 169 B13 O PCI bus request. REQ is asserted by the PCI1225 to request access to the PCI bus as an initiator.

200 B6 O

198 F7 I/O

196 B7 I/O

I/O

Terminal Functions (Continued)

FUNCTION

PCI device select. The PCI1225 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1225 monitors DEVSEL before timeout occurs, the PCI1225 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When

is deasserted, the PCI bus transaction is in the final data phase.

FRAME PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1225 access to the PCI bus after

the current data transaction has completed. GNT depending on the PCI bus parking algorithm.

Initialization device select. IDSEL selects the PCI1225 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1225 when enabled through the command register indicating a system error has occurred. The PCI1225 need not be the target of the PCI cycle to assert this signal. When SERR indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

is enabled through bit 6 of the command register.

is enabled in the control register, this signal also pulses,

is used for target disconnects and is commonly asserted by target devices

until a target responds. If no target responds

may or may not follow a PCI bus request,

and TRDY

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Terminal Functions (Continued)

NAME

TYPE

multifunction and miscellaneous terminals

TERMINAL

NUMBER

PDV GHK

MFUNC0 154 F15 I/O

MFUNC1 155 E17 I/O

MFUNC2 157 A16 I/O

MFUNC3 158 C15 I/O

I/O

Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE parallel IRQ. See the details.

Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE parallel IRQ. See the details.

Serial data (SDA). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC1 terminal provides the SDA signaling. The two-terminal serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. See the other serial bus applications.

Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

See the Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized

interrupt signal IRQSER. See the configuration details.

Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

the

SCPS035B – MA Y 1998 – REVISED – MAY 2000

FUNCTION

multifunction routing register

serial bus interface implementation

description on page 64 for configuration details.

multifunction routing register

description on page 64 for configuration details.

description on page 64 for configuration

PCI1225 GHK/PDV

PC CARD CONTROLLERS

, or a

description on page 31 for details on

, or a parallel IRQ.

description on page 64 for

, or a parallel IRQ. See

MFUNC4 159 E14 I/O

MFUNC5 160 F13 I/O

MFUNC6 161 B15 I/O

RI_OUT/PME 163 C14 O

SPKROUT

SUSPEND 156 D19 I

149 G15 O

Serial clock (SCL). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC4 terminal provides the SCL signaling. The two-terminal serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. See the other serial bus applications.

Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

See the Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See

multifunction routing register

the Ring indicate out and power management event output. Terminal provides an output for

ring-indicate or PME Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO

through the PCI1225 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR

Suspend. SUSPEND is used to protect the internal registers from clearing when the PRST signal is asserted. See

serial bus interface implementation

description on page 64 for configuration details.

signals.

//CAUDIO inputs.

suspend mode

description on page 42 for details.

description on page 31 for details on

, or a parallel IRQ.

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PCI1225 GHK/PDV

I/O

NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

16-bit PC Card address and data (slots A and B)

TERMINAL

NUMBER †

NAME

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 121 and M18 is A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R6 is B_A25.

SLOT A

PDV

121

118 116 114

111 109 107 105 103

112

115 108 106

117 100

95 102 104

119 123 125 126 128 131 132 133

93 91 89 87

84 147 145 142

83 146 144 141

GHK

M18 N19 N17

P19 P17

R18

P15 T19

U15

P18 M14 N14 R17 N18

P14

W14

R14

W16

M15

L19

L17

L15

K19

K15

K14

J19 U13

W13

P12

V12

P11

F19 G17 H15

V13 R12 U12

R11

U11 G14 G18 H14

SLOT B

PDV

55 53 51 49 47 45 42 40 37 48 50 43 41 52 34 29 36 39 54 57 59 60 62 65 66 67

27 25 23 20 18 81 79 77 26 24 21 19 17 80 78 76

GHK

R3 R2 R1 N5 N6 N2 M6

M3 N1 U5

W11

R10 V10

H2 P10 U10

W10

I/O

‡

TYPE

P6 P5 P1

K5 K2 J6 J2

K3 K1 J3 J1

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

FUNCTION

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PC CARD CONTROLLERS

I/O

NAME

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B)

TERMINAL

NUMBER †

NAME

BVD1 (STSCHG

BVD2 (SPKR

)

CD1 CD2

CE1 CE2

INPACK 127 L14 61 R7 I

IORD

IOWR

OE 98 U14 32 L6 O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 is A_INPACK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 is B_INPACK

SLOT A

PDV GHK PDV GHK

138 H19 72 V9 I

/RI)

137 J15 71 W9 I

V11

140

H171674H3R9

9497P13

R132830

99 W15 33 L5 O

101 V15 35 M2 O

SLOT B

‡

K6 L2

I/O

TYPE

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See

configuration register

bits for this signal. Status change. STSCHG

write protect, or battery voltage detect condition of a 16-bit I/O PC Card. Ring indicate. RI

Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See

and the

signal. Speaker. SPKR

socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1225 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1

are pulled low. For signal status, see Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1

odd-numbered address bytes. Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an

I/O read cycle at the current address. DMA request. INPACK

operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1225 to enable 16-bit I/O PC Card data output during host I/O read cycles.

DMA write. IORD 16-bit PC Card that supports DMA. The PCI1225 asserts IORD transfers from the PC Card to host memory.

I/O write. IOWR is driven low by the PCI1225 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

DMA read. IOWR 16-bit PC Card that supports DMA. The PCI1225 asserts IOWR from host memory to the PC Card.

Output enable. OE is driven low by the PCI1225 to enable 16-bit memory PC Card data output during host memory read cycles.

DMA terminal count. OE a 16-bit PC Card that supports DMA. The PCI1225 asserts OE a DMA write operation.

on page 91 and the

on page 92 for enable bits. See

is used to alert the system to a change in the READY,

is used by 16-bit modem cards to indicate a ring detection.

ExCA interface status register

is an optional binary audio signal available only when the card and

enables even-numbered address bytes, and CE2 enables

can be used as the DMA request signal during DMA

is used as the DMA write strobe during DMA operations from a

is used as terminal count (TC) during DMA operations to

FUNCTION

ExCA card status-change interrupt

ExCA interface status register

ExCA card status-change interrupt configuration

ExCA card status-change register

on page 88 for the status bits for this

interface status register

PCI1225 GHK/PDV

ExCA card status-change

on page 88 for the status

on page

and CD2

on page 88.

during DMA

during transfers

to indicate TC for

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV

I/O

NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B) (continued)

TERMINAL

NUMBER †

NAME

READY (IREQ

)

REG

RESET 124 L18 58 W5 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. VS1

VS2 WAIT

WE 110 R19 46 P3 O

WP (IOIS16

)

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19 is A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3 is B_WE

SLOT A

PDV GHK PDV GHK

135 J17 69 V8 I

130 K17 63 P8 O

134

J18

122

M196856

136 J14 70 W8 I

139 H18 73 U9 I

SLOT B

U8 P7

I/O

‡

TYPE

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG to the I/O space (IORD section of card memory and is generally used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts REG indicate a DMA operation. REG or DMA write (IORD

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with

I/O

each other, determine the operating voltage of the 16-bit PC Card. Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e.,

extend) the memory or I/O cycle in progress. Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards.

WE is also used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE that supports DMA. The PCI1225 asserts WE to indicate TC for a DMA read operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.

I/O is 16 bits. IOIS16 PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.

is asserted, access is limited to attribute memory (OE or WE active) and

is asserted by a 16-bit I/O PC Card to indicate to the host

or IOWR active). Attribute memory is a separately accessed

is used as a DMA acknowledge (DACK) during DMA

) strobes to transfer data.

is used as TC during DMA operations to a 16-bit PC Card

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit

FUNCTION

is used in conjunction with the DMA read (IOWR)

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I/O

NAME

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

CardBus PC Card interface system (slots A and B)

TERMINAL

NUMBER †

NAME

CCLK 112 P18 48 P6 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 is A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 is B_CCLK.

SLOT A

PDV GHK PDV GHK

139 H18 73 U9 O

124 L18 58 W5 I/O

SLOT B

I/O

‡

TYPE

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST CAUDIO, CCD2 and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1225 to indicate that the CCLK frequency is going to be decreased.

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST Card signals must be 3-stated, and the PCI1225 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK,

FUNCTION

PCI1225 GHK/PDV

, CCLKRUN, CINT, CSTSCHG,

is asserted, all CardBus PC

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PCI1225 GHK/PDV

I/O

NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

CardBus PC Card address and data (slots A and B)

TERMINAL

PIN NUMBER

†

NAME

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR 106 R17 41 N3 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 is A_CPAR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 is B_CPAR.

SLOT A

PDV GHK PDV GHK

147 145 144 142 141 133 132 131 128 126 125 123 121

103 101 102

100

130

104

119 118

98 97 95 93 92 89 90 87 88 84 85 83

117

F19 G17 G18 H15 H14

J19

K14

K15

K19

L15

L17

L19 M18 M15 N19 U15

V15 R14 W15

P14 U14 R13 W14 U13

V13

P12 R12

V12 U12

P11

R11

U11

K17 N18 W16

P13

SLOT B

81 79 78 77 76 67 66 65 62 60 59 57 55 54 53 37 35 36 33 34 32 30 29 27 26 23 24 20 21 18 19 17

63 52 39 28

W11

R10 U10 V10

W10

W4 M6 M2 M3

V6 U6 V5 R6 U5

L6 L2

L1 K5 K3

J6 K1

J3 H1

J1 H2

T1 N1 K6

I/O

‡

TYPE

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle,

–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is

CC/BE3 used as byte enables. The byte enables determine which byte paths of the full 32-bit data

I/O

bus carry meaningful data. CC/BE0 to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1225 calculates even parity across the CAD and CC/BE outputs CPAR with a one-CCLK delay . As a target during CardBus cycles, the calculated parity is compared to the initiator parity indicator; a compare error results in a parity error assertion.

buses. As an initiator during CardBus cycles, the PCI1225

FUNCTION

applies to byte 0 (CAD7–CAD0), CC/BE1 applies

applies to byte 2 (CAD23–CAD8), and CC/BE3

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PC CARD CONTROLLERS

I/O

NAME

CCD1

V11

CVS1

134

J18

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

CardBus PC Card interface control (slots A and B)

TERMINAL

PIN NUMBER

†

NAME

CAUDIO 137 J15 71 W9 I

CBLOCK

CCD1 CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 134 J18 68 U8 CVS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 137 and J15 is A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 71 and W9 is B_CAUDIO.

SLOT A

PDV GHK PDV GHK

107 P15 42 N6 I/O

82 V11 16 H3

140

H171674

111 P17 47 R1 I/O

116 N17 51 R3 I/O

110 R19 46 P3 I

135 J17 69 V8 I

115 M14 50 P5 I/O

108 N14 43 P1 I/O

127 L14 61 R7 I

136 J14 70 W8 I

109 R18 45 N5 I/O

138 H19 72 V9 I

114 P19 49 R2 I/O

122

M196856

SLOT B

‡

I/O

TYPE

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1225 supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.

CardBus device select. The PCI1225 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1225 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, the PCI1225 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME transfers continue while this signal is asserted. When CFRAME CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI1225 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY CTRDY are both sampled asserted, wait states are inserted.

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1225 can report CSERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card status, and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

I/O

in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type.

is asserted to indicate that a bus transaction is beginning, and data

FUNCTION

and CTRDY are asserted. Until CIRDY and

is driven by the card synchronous to

to the system by assertion of SERR on the PCI interface.

is used for target disconnects, and is

and CTRDY are asserted; until this time, wait states are

PCI1225 GHK/PDV

is deasserted, the

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PCI1225 GHK/PDV PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

power supply sequencing

The PCI1225 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp power supplies. The core power supply is always 3.3 V . The clamp power supplies can be either 3.3 V or 5 V , depending on the interface. The following power-up and power-down sequences are recommended.

The power-up sequence is:

1. Apply 3.3-V power to the core.

2. Assert PRST

to the device to disable the outputs during power up. Output drivers must be powered up in

the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.

3. Apply the clamp power. The power-down sequence is:

1. Use PRST

to switch outputs to a high-impedance state.

2. Remove the clamp power.

3. Remove the 3.3-V power from the core.

I/O characteristics

Figure 1 shows a 3-state bidirectional buffer. The provides the electrical characteristics of the inputs and outputs.

NOTE:

The PCI1225 meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification Rev. 2.2.

Tied for Open Drain

recommended operating conditions

CCP

Pad

table, on page 120,

Figure 1. 3-State Bidirectional Buffer

NOTE:

Unused pins (input or I/O) must be held high or low to prevent them from floating.

clamping rail voltages

The clamping rail voltages are set to match whatever external environment the PCI1225 will be working with:

3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a power rail that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping rail voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1225 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping rail voltage applied. If a system designer desires a 5-V PCI bus, V

The PCI1225 requires four separate clamping rails because it supports a wide range of features. The four rails are listed and defined in the

recommended operating conditions

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can be connected to a 5-V power supply.

CCP

, on page 120.

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

peripheral component interconnect (PCI) interface

The PCI1225 is fully compliant with the PCI Local Bus Specification Rev. 2.2. The PCI1225 provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V PCI1225 provides the optional interrupt signals INTA

PCI bus lock (LOCK)

The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1225 as an additional compatibility feature. The PCI LOCK via the multifunction routing register; see the Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal for this protocol is CBLOCK

An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video.

terminals to the desired voltage level. In addition to the mandatory PCI signals, the

CCP

and INTB.

signal can be routed to the MFUNC4 terminal

multifunction routing register

description on page 64 for details.

to avoid confusion with the bus clock.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK scenario, the arbiter will not grant the bus to any other agent (other than the LOCK

master) while LOCK is

protocol. In this

asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress.

The PCI1225 supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the 2.2 PCI specification, and the issue is resolved by the PCI master using LOCK

loading subsystem identification

The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 95 requirement.

The PCI1225 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by setting the SUBSYSRW bit in the system control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).

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PCI1225 GHK/PDV PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

loading subsystem identification (continued)

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The PCI1225 loads the data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI1225 core, including the serial bus state machine (see SUSPEND).

The PCI1225 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM. See

serial bus interface

on page 31 for details on the two-wire serial bus controller and applications.

PC Card applications

This section describes the PC Card interfaces of the PCI1225:

 Card insertion/removal and recognition

 P

C power-switch interface

 Zoom video support  Speaker and audio applications  LED socket activity indicators  16-bit PC Card DMA support  CardBus socket registers

suspend mode

, on page 42, for details on using

PC Card insertion/removal and recognition

The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined.

The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1997 PC Card Standard and in Table 5.

Table 5. PC Card Card-Detect and Voltage-Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE

Ground Ground Open Open 5 V 16-bit PC Card 5 V Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Open Ground LV 16-bit PC Card 3.3 V Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V

Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V

Ground Ground Ground Open LV 16-bit PC Card Y.Y V Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved

Ground Connect to CVS2 Connect to CCD1 Ground Reserved

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PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

P2C power-switch interface (TPS2202A/2206)

The PCI1225 provides a P The CLOCK, DATA, and LATCH terminals interface with the TI TPS2202A/2206 dual-slot PC Card power interface switches to provide power switch support. Figure 2 shows the terminal assignments of the TPS2206, and Figure 3 illustrates a typical application where the PCI1225 represents the PCMCIA controller.

C (PCMCIA peripheral control) interface for control of the PC Card power switch.

5 V 5 V

DATA

CLOCK

LATCH

RESET

12 V A VPP A VCC A VCC A VCC

GND

RESET

3.3 V

NC – No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

5 V NC NC NC NC NC 12 V BVPP BVCC BVCC BVCC NC OC

3.3 V

Figure 2. TPS2206 Terminal Assignments

The CLOCK terminal on the PCI1225 can be an input or an output. The PCI1225 defaults the CLOCK terminal as an input to control the serial interface and the internal state machine. The P2CCLK bit in the system control register can be set by the platform BIOS to enable the PCI1225 to generate and drive the CLOCK internally from the PCI clock. When the system design implements CLOCK as an output from the PCI1225, an external pulldown is required.

Power Supply

12 V

5 V

3.3 V

Supervisor

PCI1225

(PCMCIA

Controller)

TPS2206

12 V 5 V

3.3 V

RESET RESET

CLOCK DATA LATCH

AVPP

AVCC AVCC AVCC

BVPP

BVCC BVCC BVCC

V V V V

PP1 PP2 CC CC

Figure 3. TPS2206 Typical Application

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PC Card

PCI1225 GHK/PDV PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

zoom video support

The PCI1225 allows for the implementation of zoom video for PC Cards. Zoom video is supported by setting the ZVENABLE bit in the card control register on a per-socket-function basis. Setting this bit puts 16-bit PC Card address lines A25–A4 of the PC Card interface in the high-impedance state. These lines can then be used to transfer video and audio data directly to the appropriate controller. Card address lines A3–A0 can still be used to access PC Card CIS registers for PC Card configuration. Figure 4 illustrates a PCI1225 ZV implementation.

Audio

Codec

PCM Audio Input

Speakers

PC Card

Interface

Video

Audio

CRT

Motherboard

PCI Bus

VGA

Controller

Zoom Video

Port

19 4

PCI1225

Figure 4. Zoom Video Implementation Using PCI1225

Not shown in Figure 4 is the multiplexing scheme used to route either socket 0 or socket 1 ZV source to the graphics controller. The PCI1225 provides ZVSTAT, ZVSEL0, and ZVSEL1 signals on the multifunction terminals to switch external bus drivers. Figure 5 shows an implementation for switching between three ZV streams using external logic.

PCI1225

ZVSTAT ZVSEL0 ZVSEL1

0 1

Figure 5. Zoom Video Switching Application

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zoom video support (continued)

Figure 5 illustrates an implementation using standard three-state bus drivers with active-low output enables. ZVSEL0 output indicating that socket 1 ZV is enabled. When both sockets have ZV mode enabled, the PCI1225 defaults to indicating socket 0 enabled through ZVSEL0 software to select the socket ZV source priority. Table 6 illustrates the functionality of the ZV output signals.

Also shown in Figure 5 is a third ZV source that may be provided from a source such as a high-speed serial bus like IEEE 1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an active-high output indicating that one of the PCI1225 sockets is enabled for ZV mode. The implementation shown in Figure 5 can be used if PC Card ZV is prioritized over other sources.

is an active-low output indicating that the socket 0 ZV mode is enabled, and ZVSEL1 is an active-low

; however, the POR TSEL bit in the card control register allows

Table 6. PC Card Card-Detect and Voltage-Sense Connections

INPUTS OUTPUTS

PORTSEL SOCKET 0 ENABLE SOCKET 1 ENABLE ZVSEL0 ZVSEL1 ZVSTAT

X 0 0 1 1 0 0 1 X 0 1 1 0 0 1 1 0 1 1 X 1 1 0 1 1 1 0 0 1 1

SPKROUT and CAUDPWM usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 terminal becomes SPKR

. This terminal is also used in CardBus binary audio applications, and is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1225. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the two PC Card sockets are XORed in the PCI1225 to produce SPKROUT. This output is enabled by the SPKROUTEN bit in the card control register.

Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCI1225 implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. The AUD2MUX bit located in the card control register is programmed on a per-socket-function basis to route a CardBus CAUDIO PWM terminal to CAUDPWM. If both CardBus functions enable CAUDIO PWM routing to CAUDPWM, then socket 0 audio takes precedence. See the

multifunction routing register

description on page

64 for details on configuring the MFUNC terminals. Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM.

System

Core Logic

BINARY_SPKR

Speaker

Subsystem

PWM_SPKR

PCI1225

SPKROUT

CAUDPWM

Figure 6. Sample Application of SPKROUT and CAUDPWM

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LED socket activity indicators

The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LEDA1 and LEDA2 signals can be routed to the multifunction terminals. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity. The LED_SKT output indicates socket activity to either socket 0 or socket 1. See the

multifunction routing register

The LED signal is active high and is driven for 64-ms durations. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling, and it is left for the board designer to implement the circuit that best fits the application.

The LED activity signals are valid when a card is inserted, powered, and not in reset. For a 16-bit PC Card, the LED activity signals are pulsed when READY/IREQ is low. For CardBus cards, the LED activity signals are pulsed if CFRAME, IRDY, or CREQ is active.

description on page 64 for details on configuring the multifunction terminals.

Current Limiting

R ≈ 500 Ω

PCI1225

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

LED

Figure 7. T wo Sample LED Circuits

As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut-off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.

If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), the LED signals remain driven.

16-bit PC Card Distributed DMA support

The PCI1225 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. The DDMA register configuration is provided in Table 7.

Two socket function dependent PCI configuration header registers that are critical for DDMA are the socket DMA register 0 and the socket DMA register 1. Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure the 16-bit PC Card terminal (SPKR

, IOIS16, or INPACK) which is used for the DMA request signal, DREQ. The base address of the DDMA slave registers and the transfer size (bytes or words) are programmed through the socket DMA register 1. See the programming model and register descriptions for details.

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16-bit PC Card distributed DMA support (continued)

Table 7. Distributed DMA Registers

TYPE REGISTER NAME

R W R W R N/A W Mode R Multichannel W Mask

Reserved Page

Reserved Reserved

Reserved

Request Command

Master clear

Current address 00h

Base address Current count 04h

Base count

N/A Status 08h

N/A

Reserved

The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the register locations are reordered and expanded in some cases. While the DDMA register definitions are identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1225 implements these obsolete register bits as read-only , nonfunctional bits. The reserved registers shown in T able 7 are implemented as read-only and return zeros when read. Write transactions to reserved registers have no effect.

BASE ADDRESS

OFFSET

DMA

0Ch

The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ

signal assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an 8237 controller, and the PCI1225 awaits a DREQ assertion from the PC Card requesting a DMA transfer.

DMA writes transfer data from the PC Card to PCI memory addresses. The PCI1225 accepts data 8 or 16 bits at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ signal. Once the PCI bus is granted in an idle state, the PCI1225 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1225 accepts the next byte(s) from the PC Card until the transfer count expires.

DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ the PCI1225 asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1225 initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After terminating the PC Card cycle, the PCI1225 requests access to the PCI bus again until the transfer count has expired.

The PCI1225 target interface acts normally during this procedure and accepts I/O reads and writes to the DDMA registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1225 asserts TC and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the PCI1225 supports demand mode transfers. The PCI1225 asserts DACK during the transfer unless DREQ

is deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all transfers, and the DREQ terminal is routed to one of three options which is programmed through socket DMA register 0.

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16-bit PC Card PC/PCI DMA

Some chip sets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol, the PCI1225 acts as a PCI target device to certain DMA related I/O addresses. The PCI1225 PCREQ and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. See the

multifunction routing register

Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1225) requests a DMA transfer on a particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus, and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory cycles are then presented on the PCI bus, which performs the DMA transfers similarly to legacy DMA master devices.

PC/PCI DMA is enabled for each 16-bit PC Card slot by setting bit 19 in the respective system control register . On power up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 of the system control register is a global enable for PC/PCI DMA, and is set at power-up and never cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for each 16-bit PC Card slot must be configured through bits 18–16 in the system control register. The channels are configured as indicated in Table 8.

description on page 64 for details on configuring the multifunction terminals.

Table 8. PC/PCI Channel Assignments

SYSTEM CONTROL REGISTER

BIT 18 BIT 17 BIT16

0 0 0 Channel 0 8-bit DMA transfers 0 0 1 Channel 1 8-bit DMA transfers 0 1 0 Channel 2 8-bit DMA transfers 0 1 1 Channel 3 8-bit DMA transfers 1 0 0 Channel 4 Not used 1 0 1 Channel 5 16-bit DMA transfers 1 1 0 Channel 6 16-bit DMA transfers 1 1 1 Channel 7 16-bit DMA transfers

DMA CHANNEL CHANNEL TRANSFER DATA WIDTH

As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0. The data transfer width is a function of channel number , and the DDMA slave registers are not used. When a DREQ

is received from a PC Card and the channel has been granted, the PCI1225 decodes the I/O

addresses listed in Table 9 and performs actions dependent upon the address.

Table 9. I/O Addresses Used for PC/PCI DMA

DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE

00h Normal 0 I/O read/write

04h Normal TC 1 I/O read/write C0h Verify 0 I/O read C4h Verify TC 1 I/O read

When the PC/PCI DMA is used as a 16-bit PC Card DMA mechanism, it may not provide the performance levels of DDMA; however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master state machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset. This DMA scheme is often referred to as centralized DMA for this reason.

CardBus socket registers

The PCI1225 contains all registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge specification. These registers exist as the CardBus socket registers, and are listed in Table 10.

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Table 10. CardBus Socket Registers

Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch

Socket power management 20h

serial bus interface

The PCI1225 provides a serial bus interface to load subsystem identification and select register defaults through a serial EEPROM and to provide a PC Card power switch interface alternative to P2C. See

interface (TPS2202A/2206)

C and SMBus components.

on page 25 for details. The PCI1225 serial bus interface is compatible with various

P2C power-switch

serial bus interface implementation

The PCI1225 defaults to serial bus interface are disabled. To enable the serial interface, a pulldown resistor must be implemented on the LATCH terminal and the appropriate pullup must be implemented on the SDA and SCL signals, i.e. the MFUNC1 and MFUNC4 terminals. When the interface is detected, the SBDETECT bit in the system control register is set. The SBDETECT bit is cleared by a writeback of 1.

The PCI1225 implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA). When a pulldown is provided on the LATCH terminal, the SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal. The PCI1225 drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I2C. An example application implementing the two-wire serial bus is illustrated in Figure 8.

Serial

EEPROM

A0 A1 A2

SCL

SDA

PCI1225

LATCH

MFUNC4 MFUNC1

Figure 8. Serial EEPROM Application

Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow.

serial bus interface protocol

The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure Figure 8. The PCI1225 supports up to 100 Kb/s data transfer rate and is compatible with standard mode I2C using seven-bit addressing.

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serial bus interface protocol (continued)

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signalled when the SDA line transitions to low state while SCL is in the high state, as illustrated in Figure 9. The end of a requested data transfer is indicated by a stop condition, which is signalled by a low to high transition of SDA while SCL is in the high state, as shown in Figure 9. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or a stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 9. Serial Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited, however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. The acknowledge protocol is illustrated in Figure 10.

SCL From

Master

SDA Output

By Transmitter

SDA Output

By Receiver

123 789

Figure 10. Serial Bus Protocol Acknowledge

The PCI1225 is a serial bus master; all other devices connected to the serial bus external to the PCI1225 are slave devices. As the bus master, the PCI1225 drives the SCL clock at nearly 100 kHz during bus cycles and three-states SCL (zero frequency) during idle states.

Typically, the PCI1225 masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See

serial bus EEPROM application

on page 34 for details on how the PCI1225 automatically

loads the subsystem identification and other register defaults through a serial bus EEPROM. A byte write is illustrated in Figure 11. The PCI1225 issues a start condition and sends the seven-bit slave device

address and the command bit zero. A zero in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1225, then an appropriate status bit is set in the serial bus control and status register. The word address byte is then sent by the PCI1225 and another slave acknowledgment is expected. Then the PCI1225 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition.

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serial bus interface protocol (continued)

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Slave Address Word Address

Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

Start

R/W

S/P = Start/Stop ConditionA = Slave Acknowledgement

b7 b6 b4b5 b3 b2 b1 b0 A P

Data Byte

Figure 11. Serial Bus Protocol – Byte Write

A byte read is illustrated in Figure 12. The read protocol is very similar to the write protocol except the R/W command bit must be set to one to indicate a read-data transfer. In addition, the PCI1225 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCI1225 master.

Slave Address Word Address

Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

Start

A = Slave Acknowledgement

R/W

Sb6 b4b5 b3 b2 b1 b0 1 A

Restart R/W

b7 b6 b4b5 b3 b2 b1 b0 M P

S/P = Start/Stop ConditionM = Master Acknowledgement

Slave Address

Data Byte

Stop

Figure 12. Serial Bus Protocol – Byte Read

Figure 13 illustrates EEPROM interface doubleword data collection protocol.

Slave Address Word Address

S1 10 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

Start

R/W

Data Byte 3 M

Data Byte 2 Data Byte 1 Data Byte 0 M PMM

M = Master Acknowledgement

S1 10 00001A

Restart

Slave Address

S/P = Start/Stop ConditionA = Slave Acknowledgement

Figure 13. EEPROM Interface Doubleword Data Collection

R/W

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serial bus EEPROM application

When the PCI bus is reset and the serial bus interface is detected, the PCI1225 attempts to read the subsystem identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be loaded with defaults through the EEPROM are provided in Table 11.

Table 11. Registers and Bits Loadable Through Serial EEPROM

PCI OFFSET

40h 01h Subsystem identification 31–0 80h 02h System control register 31–29, 27, 26, 24, 15, 14, 6–3, 1 8Ch 03h Multifunction routing register 27–0 90h 04h Retry status, card control, device control, diagnostic 31, 28–24, 22, 19–16, 15, 13, 7, 6

OFFSET

REFERENCE

The EEPROM data format is detailed in Figure 14. This format must be followed for the PCI1225 to properly load initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the ROM_ERR bit in the serial bus control and status register.

Slave Address = 1010 000

Reference(0) Word Address 00h

Byte 3 (0) Word Address 01h Byte 2 (0) Word Address 02h Byte 1 (0) Word Address 03h Byte 0 (0) Word Address 04h

RSVD RSVD RSVD

Reference(1) Word Address 08h

Reference(n) Word Address 8 × (n–1)

Byte 3 (n) Word Address 8 × (n–1) + 1 Byte 2 (n) Word Address 8 × (n–1) + 2 Byte 1 (n) Word Address 8 × (n–1) + 3 Byte 0 (n) Word Address 8 × (n–1) + 4

RSVD RSVD RSVD

EOL Word Address 8 × (n)

Figure 14. EEPROM Data Format

The byte at the EEPROM word address 00h must either contain a valid PCI offset, as listed in Table 11, or an end-of-list (EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when programming the EEPROM.

The serial EEPROM is addressed at slave address 1010 000b by the PCI1225. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 8) assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 13. The address autoincrements after every byte transfer according to the doubleword read protocol. Note that the word addresses align with the data format illustrated in Figure 14. The PCI1225 continues to load data from the serial EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures.

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serial bus EEPROM application (continued)

Note, the eight-byte data structure is important to provide correct addressing per the doubleword read format shown in Figure 13. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is 01h, 02h, 03h, 04h. If the offsets are not sequential, the registers may be loaded incorrectly.

serial bus power switch application

The PCI1225 does not automatically control a serial bus power switch transparently to host software as it does

C power switches. But, the PCI1225 serial bus interface can be used in conjunction with the power status,

for P GPE, output, and support software to control a serial bus power switch. If a serial bus power switch interface is implemented, a pulldown resistor must be provided on the PCI1225 CLOCK terminal to reduce power consumption.

The PCI1225 supports two common SMBus data write protocols, write byte and send byte formats. The write byte protocol using a word address of 00h is discussed in byte protocol is shown in Figure 15 using a slave address 101 001Xb. The PROT_SEL bit in the serial bus control and status register, see Table 42 on page 82, allows the serial bus interface to operate with the send byte protocol. For more information on programming the serial bus interface, see

through software

Slave Address Command Code

serial bus interface protocol

accessing serial bus devices

on page 32. The send

S1 10 0 0 1 X 0 b7 b6 b5 b4 b3 b2 b1 b0AA

R/W

S/P = Start/Stop ConditionA = Slave Acknowledgement

Figure 15. Send Byte Protocol

The power switch may support an interrupt mode to indicate overcurrent or other power switch related events. The PCI1225 does not implement logic to respond to these events, but does implement a flexible general purpose interface to control these events through ACPI and other handlers. See

Power Interface Specification

for details on implementing the PCI1225 in an ACPI system.

Advanced Configuration and

accessing serial bus devices through software

The PCI1225 provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. T able 12 lists the registers used to program a serial bus device through software.

Table 12. PCI1225 Registers Used to Program Serial Bus Devices

PCI OFFSET REGISTER NAME DESCRIPTION

B0h Serial bus data

B1h Serial bus index

B2h

B3h

Serial bus slave address

Serial bus control and status

Contains the data byte to send on write commands or the received data byte on read commands.

The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol.

Write transactions to this register initiate a serial bus transaction. The slave device address and the R/W

Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol select bit is programmed through this register.

command selector are programmed through this register.

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programmable interrupt subsystem

Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1225. The PCI1225 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1225 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required.

The PCI1225 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1225, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts.

The method by which any type of PCI1225 interrupt is communicated to the host interrupt controller varies from system to system. The PCI1225 offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0–MFUNC6.

PC Card functional and card status change interrupts

PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards.

Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCI1225 and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.

Table 13 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are:

 16-bit memory card  16-bit I/O card  CardBus cards

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Table 13. Interrupt Mask and Flag Registers

CARD TYPE EVENT MASK FLAG

16-bit memory

16-bit I/O All 16-bit PC Cards Power cycle complete ExCA of fset 05h/45h/805h bit 3 ExCA offset 04h/44h/804h bit 3

CardBus

Battery conditions (BVD1, BVD2)

Wait states (READY) ExCA offset 05h/45h/805h bit 2 ExCA offset 04h/44h/804h bit 2

Change in card status (STSCHG) ExCA offset 05h/45h/805h bit 0 ExCA offset 04h/44h/804h bit 0

Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0

Change in card status

(CSTSCHG)

Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0

Power cycle complete Socket mask bit 3 Socket event bit 3

Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1

Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type.

Table 14. PC Card Interrupt Events and Description

ExCA offset 05h/45h/805h

bits 1 and 0

Socket mask bit 0 Socket event bit 0

ExCA offset 04h/44h/804h bits 1 and 0

CARD TYPE EVENT TYPE SIGNAL DESCRIPTION

A transition on BVD1 indicates a change in the PC Card battery conditions.

A transition on BVD2 indicates a change in the PC Card battery conditions.

A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data.

The assertion of STSCHG indicates a status change on the PC Card.

The assertion of IREQ indicates an interrupt request from the PC Card.

The assertion of CSTSCHG indicates a status change on the PC Card.

The assertion of CINT indicates an interrupt request from the PC Card.

A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit or CardBus PC Card.

An interrupt is generated when a PC Card power-up cycle has completed.

16-bit memory

16-bit I/O

CardBus

All PC Cards

Battery conditions

(BVD1, BVD2)

Wait states

(READY)

Change in card

status (STSCHG)

Interrupt request

(IREQ)

Change in card

status (CSTSCHG)

Interrupt request

(CINT

)

Card insertion or

removal

Power cycle

complete

BVD1(STSCHG)//CSTSCHG

CSC

BVD2(SPKR)//CAUDIO

CSC READY(IREQ)//CINT

CSC BVD1(STSCHG)//CSTSCHG

Functional READY(IREQ)//CINT

CSC BVD1(STSCHG)//CSTSCHG

Functional READY(IREQ)//CINT

CSC CD1//CCD1, CD2//CCD2

CSC N/A

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PC Card functional and CSC interrupts (continued)

The naming convention for PC Card signals describes the function for 16-bit memory , I/O cards, and CardBus. For example, READY(IREQ CINT

for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second,

enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI1225 when an

insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1225 interrupt scheme can be used to notify the host system (see Table 14), denoted by the power cycle complete event. This interrupt source is considered a PCI1225 internal event because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface.

interrupt masks and flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 14 by setting the appropriate bits in the PCI1225. By individually masking the interrupt sources listed, software can control those events that cause a PCI1225 interrupt. Host software has some control over the system interrupt the PCI1225 asserts by programming the appropriate routing registers. The PCI1225 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections.

)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and

When an interrupt is signaled by the PCI1225, the interrupt service routine must determine which of the events listed in Table 13 caused the interrupt. Internal registers in the PCI1225 provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.

T able 13 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Notice that there is not a mask bit to stop the PCI1225 from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization.

V arious methods of clearing the interrupt flag bits are listed in T able 13. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register . The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the

read

method.

flag cleared on

The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning.

using parallel IRQ interrupts

The seven multifunction terminals, MFUNC6:0, implemented in the PCI1225 may be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA type IRQ interrupt signaling, software must program the device control register, located at PCI of fset 92h, to select the parallel IRQ signaling scheme. See the

multifunction routing register

description on page 64 for

details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This

requirement is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal for INT A signaling. The INTRTIE bit is used, in this case, to route socket 1 interrupt events to INTA. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.

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using parallel IRQ interrupts (continued)

As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11, and IRQ15. The multifunction control register must be programmed to a value of 0x0FBA5432. This value routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 16. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel PCI interrupts to the host.

PCI1225 PIC

MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

Figure 16. IRQ Implementation

Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the PCI1225. The multifunction routing register is shared between the two PCI1225 functions, and only one write to function 0 or 1 is necessary to configure the MFUNC6:0 signals. Writing to only function 0 is recommended. See the

multifunction routing register

details on configuring the multifunction terminals.

IRQ3 IRQ4 IRQ5 IRQ10 IRQ11 IRQ15

description on page 64 for

The parallel ISA type IRQ signaling from the MFUNC6:0 terminals is compatible with those input directly into the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints may demand more MFUNC6:0 IRQ terminals than the PCI1225 makes available. A system designer may choose to implement an IRQSER deserializer companion chip, such as the Texas Instruments PCI950. T o use a deserializer , the MFUNC3 terminal must be configured as IRQSER and connected to the deserializer , which outputs all 15 ISA IRQs and four PCI interrupts as decoded from the IRQSER stream.

using parallel PCI interrupts

Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. Both INTA

and INTB can be routed to MFUNC terminals (MFUNC0 and MFUNC1). However, interrupts of both socket functions can be routed to INT A (MFUNC0) if the INTRTIE bit is set in the system control register.

The INTRTIE bit effects the read-only value provided through accesses to the interrupt pin register. When INTRTIE bit is set, both functions return a value of 0x01 on reads from the interrupt pin register for both parallel and serial PCI interrupts. The interrupt signalling modes are summarized in Table 15.

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using parallel PCI interrupts (continued)

Table 15. Interrupt Pin Register Cross Reference

INTERRUPT SIGNALING MODE

Parallel PCI interrupts only 0 01h (INTA) 02h (INTB) Parallel IRQ and parallel PCI interrupts 0 01h (INTA) 02h (INTB) IRQ serialized (IRQSER) and parallel PCI interrupts 0 01h (INTA) 02h (INTB) IRQ and PCI serialized (IRQSER) interrupts (default) 0 01h (INTA) 02h (INTB) Parallel PCI interrupts only 1 01h (INTA) 01h (INTA) Parallel IRQ and parallel PCI interrupts 1 01h (INTA) 01h (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts IRQ and PCI serialized (IRQSER) interrupts

†

When configuring the PCI1225 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit.

†

INTRTIE

BIT

†

1 01h (INTA) 01h (INTA) 1 01h (INTA) 01h (INTA)

INTPIN

FUNCTION 0

INTPIN

FUNCTION 1

using serialized IRQSER interrupts

The serialized interrupt protocol implemented in the PCI1225 uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes sixteen parallel ISA IRQ signals and the optional four PCI interrupts INTA, INTB, INTC, and INTD

. For details on the IRQSER protocol see the document

Serialized IRQ Support for PCI Systems

SMI support in the PCI1225

The PCI1225 provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the PCI1225, when enabled, after a write cycle to either the socket control register of the CardBus register set or the power control register of the ExCA register set causes a power cycle change sequence sent on the power switch interface.

The SMI control is programmed through three bits (bits 26–24) in the system control register. These bits are SMIROUTE, SMISTATUS, and SMIENB. The SMI control bits function as described in Table 16.

Table 16. SMI Control

BIT NAME FUNCTION

SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. SMIENB When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.

If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register.

If IRQ2 is selected by SMIROUTE, the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC3 or MFUNC6 through the multifunction routing register.

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power management overview

TI has expended great effort to provide a high-performance device with low power consumption. In addition to the low-power CMOS technology process used for the PCI1225, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section.

clock run protocol

The PCI CLKRUN CLKRUN signalling is provided through the MFUNC6 terminal. Since some chipsets do not implement CLKRUN, this is not always available to the system designer , and alternate power-saving features are provided. For details on the CLKRUN protocol see the

The PCI1225 does not permit the central resource to stop the PCI clock under any of the following conditions:

feature is the primary method of power management on the PCI interface of the PCI1225.

PCI Mobile Design Guide

 The KEEPCLK bit in the system control register is set.  The 16-bit PC Card resource manager is busy.  The PCI1225 CardBus master state machine is busy. A cycle may be in progress on CardBus.  The PCI1225 master is busy. There may be posted data from CardBus to PCI in the PCI1225.  There are pending interrupts.  The CardBus CCLK for either socket has not been stopped by the PCI1225 CLKRUN manager.

The PCI1225 restarts the PCI clock using the CLKRUN protocol under any of the following conditions:

 A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.  A CardBus wake-up (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in either socket.  A CardBus attempts to start CCLK using CCLKRUN.  A CardBus card arbitrates for the CardBus bus using CREQ.  A 16-bit DMA PC Card asserts DREQ.

CardBus PC card power management

The PCI1225 implements its own card power management engine that can be used to turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface to control this clock management.

16-Bit PC card power management

The COE and PWRDOWN bits in the ExCA registers are provided for 16-bit PC Card power management. The COE bit three states the card interface to save power. The power savings when using this feature are minimal. The COE bit will reset the PC Card when used, and the PWRDOWN bit will not. Furthermore, the PWRDOWN bit is an automatic COE, that is, the PWRDOWN performs the COE function when there is no card activity.

NOTE:

The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDOWN modes.

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suspend mode

The SUSPEND

signal provides backward compatibility and gates the PCI reset (PRST) signal from the PCI1225. However, additional functionality has been defined for SUSPEND to provide additional power-management options.

SUSPEND provides a mechanism to gate PCLK from the PCI1225, as well as gate PRST. This can potentially save power while in an idle state; however, it requires substantial design effort to implement. Some issues to consider are:

 What if cards are present in the sockets?  What if the cards in the sockets are powered?  How to pass CSC (insertion/removal) events.

Even without the PCI clock to the PCI1225 core, asynchronous-type functions (such as RI_OUT) can pass CSC events, wake-up events, etc., back to the system. If a system designer chooses to not pass card removal events through to the system, then the PCI1225 would not be able to power down the empty socket without the power switch clock (CLOCK) generated externally. See the P functional implementation diagram.

PRST

SUSPEND

GNT

C power switch interface for details. Figure 17 is a

PCI1225

Core

PCLK

Figure 17. SUSPEND Functional Implementation

Figure 18 is a signal diagram of the suspend function.

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suspend mode (continued)

PRST

GNT

SUSPEND

PCLK

PRSTIN

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External T erminals

Internal Signals

SUSPENDIN

PCLKIN

Figure 18. Signal Diagram of Suspend Function

ring indicate

The RI_OUT

output is an important feature in power management, allowing a system to go into a suspended mode and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform requirements. RI_OUT

on the PCI1225 can be asserted under any of the following conditions:

 A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an

incoming call.

 A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.  A CSC event occurs, such as insertion/removal of cards, battery voltage levels.

CSTSCHG from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT events are enabled separately . Figure 19 shows various enable bits for the PCI1225 RI_OUT function; however, it does not show the masking of CSC events. See Table 13 for a detailed description of CSC interrupt masks and flags.

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ring indicate (continued)

PC Card

Socket 0

PC Card

Socket 1

Card

I/F

Card

I/F

RI_OUT Function

CSTSMASK

CSC

RINGEN

CDRESUME

CSC

CSTSMASK

CSC

RINGEN

CDRESUME

RIENB

RI_OUT

CSC

Figure 19. RI_OUT Functional Diagram

RI from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the interrupt and general control register. This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket.

The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers.

PCI power management (PCIPM)

The PCI power-management (PCIPM) specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software-visible power-management states that result in varying levels of power savings.

The four power-management states of PCI functions are:

 D0 – Fully-on state  D1 and D2 – Intermediate states  D3 – Off state

Similarly , bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the originating bridge device.

For the operating system (OS) to power manage the device power states on the PCI bus, the PCI function should support four power-management operations. These operations are:

 Capabilities reporting  Power status reporting  Setting the power state  System wake up

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PCI power management (PCIPM) (continued)

The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1 in the capabilities list (CAPLIST) bit in the status register (bit 4) and providing access to a capabilities list.

The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1225, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, the next item pointer should be set to 0. The registers following the next item pointer are specific to the function capability . The PCIPM capability implements the register block outlined in Table 17.

Table 17. Power-Management Registers

Power-management capabilities Next item pointer Capability ID 0

Data PMCSR bridge support extensions Power-management control status (CSR) 4

The power management capabilities register is a static read-only register that provides information on the capabilities of the function related to power management. The PMCSR register enables control of power-management states and enables/monitors power-management events. The data register is an optional register that can provide dynamic data.

For more information on PCI power management see the

PCI Bus Power Management Interface Specification

ACPI support

The ACPI specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI1225 offers a generic interface that is compliant with ACPI design rules.

Two doublewords of general purpose ACPI programming bits reside in PCI1225 PCI configuration space at offset A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in GPE_STS and GPE_EN registers. The status and enable bits are implemented as defined by ACPI, and illustrated in Figure 20.

Status Bit

Event Input

Enable Bit

Event Output

Figure 20. Block Diagram of a Status/Enable Cell

The status and enable bits are used to generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events.

For more information of ACPI see the

Advanced Configuration and Power Interface Specification.

PC Card controller programming model

This section describes the PCI1225 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1225 function. As noted, some bits are global in nature and should be accessed only through function 0.

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PCI configuration registers (functions 0 and 1)

The PCI1225 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The configuration header is compliant with the PCI specification as a CardBus bridge header and is PC98 compliant as well. Table 18 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers.

Table 18. PCI Configuration Registers (Functions 0 and 1)

Device ID Vendor ID 00h

Status Command 04h

Class code Revision ID 08h

BIST Header type Latency timer Cache line size 0Ch

CardBus socket/ExCA base address 10h

Secondary status Reserved Capability pointer 14h

CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h

CardBus memory base register 0 1Ch

CardBus memory limit register 0 20h

CardBus memory base register 1 24h

CardBus memory limit register 1 28h

CardBus I/O base register 0 2Ch

CardBus I/O limit register 0 30h

CardBus I/O base register 1 34h

CardBus I/O limit register 1 38h Bridge control Interrupt pin Interrupt line 3Ch Subsystem ID Subsystem vendor ID 40h

PC Card 16-bit I/F legacy-mode base address 44h

Reserved 48h–7Ch

System control 80h

Reserved 84h–88h

Multifunction routing 8Ch

Diagnostic Device control Card control Retry status 90h

Socket DMA register 0 94h Socket DMA register 1 98h

Reserved 9Ch

Power-management capabilities Next-item pointer Capability ID A0h

PM data

General-purpose event enable General-purpose event status A8h

General-purpose output General-purpose input ACh

Serial bus control/status Serial bus slave address Serial bus index Serial bus data B0h

PMCSR bridge support

extensions

Power-management control/status A4h

Reserved B4h–FCh

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vendor ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

Register: Vendor ID Type: Read-only Offset: 00h (functions 0, 1) Default: 104Ch Description: This 16-bit read-only register contains a value allocated by the PCI Special Interest Group

(SIG) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch.

device ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0

Register: Device ID Type: Read-only Offset: 02h (functions 0, 1) Default: AC1Ch Description: This 16-bit read-only register contains a value assigned to the PCI1225 by TI. The device

identification for the PCI1225 is AC1Ch.

command register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R R R R/W R R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Command Type: Read-only, read/write (see individual bit descriptions) Offset: 04h Default: 0000h Description: The command register provides control over the PCI1225 interface to the PCI bus. All bit

functions adhere to the definitions in

PCI Local Bus Specification 2.2

. None of the bit functions in this register are shared between the two PCI1225 PCI functions. Two command registers exist in the PCI1225, one for each function. Software must manipulate the two PCI1225 functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired-OR between the two functions, and these control bits appear separately according to their software function. See Table 19 for the complete description of the register contents.

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T able 19. Command Register

BIT SIGNAL TYPE FUNCTION

15–10 RSVD R Reserved. Bits 15–10 are read-only and return 0s when read. Write transactions have no effect.

9 FBB_EN R

8 SERR_EN R/W

7 STEP_EN R

6 PERR_EN R/W

5 VGA_EN R

4 MWI_EN R

3 SPECIAL R

2 MAST_EN R/W

1 MEM_EN R/W

0 IO_EN R/W

Fast back-to-back enable. The PCI1225 does not generate fast back-to-back transactions; therefore, bit 9 is read-only and returns 0s when read.

System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set for the PCI1225 to report address parity errors.

Address/data stepping control. The PCI1225 does not support address/data stepping, and bit 7 is hardwired to 0. Write transactions to this bit have no effect.

Parity error response enable. Bit 6 controls the PCI1225 response to parity errors through PERR. Data parity errors are indicated by asserting PERR SERR

VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette registers. The PCI1225 does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit 5 is read-only and returns 0 when read. Write transactions to this bit have no effect.

Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and Invalidate commands. The PCI1225 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 is read-only and returns 0 when read. Write transactions to this bit have no effect.

Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1225 does not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 is read-only and returns 0 when read. Write transactions to this bit have no effect.

Bus master control. Bit 2 controls whether or not the PCI1225 can act as a PCI bus initiator (master). The PCI1225 can take control of the PCI bus only when this bit is set.

Memory space enable. Bit 1 controls whether or not the PCI1225 can claim cycles in PCI memory space.

I/O space control. Bit 0 controls whether or not the PCI1225 can claim cycles in PCI I/O space.

0 = Disable SERR 1 = Enable SERR

0 = PCI1225 ignores detected parity error (default) 1 = PCI1225 responds to detected parity errors

0 = Disables the PCI1225 ability to generate PCI bus accesses (default) 1 = Enables the PCI1225 ability to generate PCI bus accesses

0 = Disables the PCI1225 response to memory space accesses (default) 1 = Enables the PCI1225 response to memory space accesses

0 = Disables the PCI1225 from responding to I/O space accesses (default) 1 = Enables the PCI1225 to respond to I/O space accesses

output driver (default)

output driver

, whereas address parity errors are indicated by asserting

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status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Status Type R/C R/C R/C R/C R/C R R R/C R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Register: Status Type: Read-only, read/clear (see individual bit descriptions) Offset: 06h (functions 0, 1) Default: 0210h Description: The status register provides device information to the host system. Bits in this register may be

read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the

Bus Specification 2.2

. PCI bus status is shown through each function. See Table 20 for the

complete description of the register contents.

Table 20. Status Register

BIT SIGNAL TYPE FUNCTION

15 PAR_ERR R/C Detected parity error. Bit 15 is set when a parity error is detected (either address or data). 14 SYS_ERR R/C

13 MABORT R/C

12 TABT_REC R/C

11 TABT_SIG R/C

10–9 PCI_SPEED R

8 DATAPAR R/C

7 FBB_CAP R

6 UDF R

5 66MHZ R

4 CAPLIST R

3–0 RSVD R Reserved. Bits 3–0 return 0s when read.

Signaled system error. Bit 14 is set when SERR is enabled and the PCI1225 signals a system error to the host.

Received master abort. Bit 13 is set when a cycle initiated by the PCI1225 on the PCI bus has been terminated by a master abort.

Received target abort. Bit 12 is set when a cycle initiated by the PCI1225 on the PCI bus was terminated by a target abort.

Signaled target abort. Bit 11 is set by the PCI1225 when it terminates a transaction on the PCI bus with a target abort.

DEVSEL timing. These read-only bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1225 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.

Data parity error detected.

Fast back-to-back capable. The PCI1225 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0.

User-definable feature support. The PCI1225 does not support the user-definable features; thus, bit 6 is hardwired to 0.

66-MHz capable. The PCI1225 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

Capabilities list. Bit 4 is read-only and returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function.

0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred, and the following conditions were met:

a. PERR b. The PCI1225 was the bus master during the data parity error. c. The PERR_EN bit is set in the command register.

was asserted by any PCI device including the PCI1225.

PCI Local

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revision ID register

Bit 7 6 5 4 3 2 1 0 Name Revision ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1

Register: Revision ID Type: Read-only Offset: 08h (functions 0, 1) Default: 01h Description: This read-only register indicates the silicon revision of the PCI1225.

PCI class code register

Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code

Base class Sub class Programming interface

Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

Register: PCI Class code Type: Read-only Offset: 09h (functions 0, 1) Default: 060700h Description: The class code register recognizes the PCI1225 functions 0 and 1 as a bridge device (06h),

and CardBus bridge device (07h) with a 00h programming interface.

cache line size register

Bit 7 6 5 4 3 2 1 0 Name Cache line size Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Cache line size Type: Read/write Offset: 0Ch (functions 0, 1) Default: 00h Description: The cache line size register is programmed by host software to indicate the system cache line

size.

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latency timer register

Bit 7 6 5 4 3 2 1 0 Name Latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Latency timer Type: Read/write Offset: 0Dh Default: 00h Description: The latency timer register specifies the latency timer for the PCI1225 in units of PCI clock

cycles. When the PCI1225 is a PCI bus initiator and asserts FRAME counting from zero. If the latency timer expires before the PCI1225 transaction has terminated, the PCI1225 terminates the transaction when its GNT is deasserted. This register is separate for each of the two PCI1225 functions. This allows platforms to prioritize the two PCI1225 functions’ use of the PCI bus.

header type register

Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 1 0 0 0 0 0 1 0

, the latency timer begins

Register: Header type Type: Read-only Offset: 0Eh (functions 0, 1) Default: 82h Description: This read-only register returns 82h when read, indicating that the PCI1225 functions 0 and 1

configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 00h to 7Fh, and 80h–FFh is user-definable extension registers.

BIST register

Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: BIST Type: Read-only Offset: 0Fh (functions 0, 1) Default: 00h Description: Because the PCI1225 does not support a built-in self-test (BIST), this register is read-only and

returns the value of 00h when read.

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CardBus socket registers/ExCA base-address register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: CardBus socket/ExCA base address Type: Read-only, read/write Offset: 10h Default: 0000 0000h Description: The CardBus socket registers/ExCA base-address register is programmed with a base

address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4 Kbytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. Since this register is not shared by functions 0 and 1, mapping of each socket control is performed separately.

capability pointer register

Bit 7 6 5 4 3 2 1 0 Name Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0

Register: Capability pointer Type: Read-only Offset: 14h Default: A0h Description: The capability pointer register provides a pointer into the PCI configuration header where the

PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read-only and returns A0h when read.

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secondary status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Secondary status Type R/C R/C R/C R/C R/C R R R/C R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Register: Secondary status Type: Read-only, read/clear (see individual bit descriptions) Offset: 16h Default: 0200h Description: The secondary status register is compatible with the PCI-to-PCI bridge secondary status

register, and indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (offset 06h); status bits are cleared by writing a 1. See Table 21 for a complete description of the register contents.

Table 21. Secondary Status Register

BIT SIGNAL TYPE FUNCTION

15 CBPARITY R/C Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). 14 CBSERR R/C

13 CBMABORT R/C

12 REC_CBTA R/C

11 SIG_CBT A R/C

10–9 CB_SPEED R

8 CB_DPAR R/C

7 CBFBB_CAP R

6 CB_UDF R

5 CB66MHZ R

4–0 RSVD R Reserved. Bits 4–0 return 0s when read.

Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1225 does not assert CSERR

Received master abort. Bit 13 is set when a cycle initiated by the PCI1225 on the CardBus bus has been terminated by a master abort.

Received target abort. Bit 12 is set when a cycle initiated by the PCI1225 on the CardBus bus is terminated by a target abort.

Signaled target abort. Bit 1 1 is set by the PCI1225 when it terminates a transaction on the CardBus bus with a target abort.

CDEVSEL timing. These read-only bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the PCI1225 asserts CB_SPEED at a medium speed.

CardBus data parity error detected.

Fast back-to-back capable. The PCI1225 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0.

User-definable feature support. The PCI1225 does not support the user-definable features; thus, bit 6 is hardwired to 0.

66-MHz capable. The PCI1225 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred and the following conditions were met:

a. CPERR b. The PCI1225 was the bus master during the data parity error. c. The PERR_EN bit is set in the bridge control register.

was asserted on the CardBus interface.

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PCI bus number register

Bit 7 6 5 4 3 2 1 0 Name PCI bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: PCI bus number Type: Read/write Offset: 18h (functions 0, 1) Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the

PCI bus to which the PCI1225 is connected. The PCI1225 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

CardBus bus number register

Bit 7 6 5 4 3 2 1 0 Name CardBus bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: CardBus bus number Type: Read/write Offset: 19h Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the

CardBus bus to which the PCI1225 is connected. The PCI1225 uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI1225 controller function.

subordinate bus number register

Bit 7 6 5 4 3 2 1 0 Name Subordinate bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Subordinate bus number Type: Read/write Offset: 1Ah Default: 00h Description: This read/write register is programmed by the host system to indicate the highest-numbered

bus below the CardBus bus. The PCI1225 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function.

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CardBus latency timer register

Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: CardBus latency timer Type: Read/write Offset: 1Bh (functions 0, 1) Default: 00h Description: This read/write register is programmed by the host system to specify the latency timer for the

PCI1225 CardBus interface in units of CCLK cycles. When the PCI1225 is a CardBus initiator and asserts CFRAME before the PCI1225 transaction has terminated, then the PCI1225 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed.

memory base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

, the CardBus latency timer begins counting. If the latency timer expires

Register: Memory base registers 0, 1 Type: Read-only, read/write Offset: 1Ch, 24h Default: 0000 0000h Description: The memory base registers indicate the lower address of a PCI memory address range.

These registers are used by the PCI1225 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1225 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 Kbytes of memory to CardBus).

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memory limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Memory limit registers 0, 1 Type: Read-only, read/write Offset: 20h, 28h Default: 0000 0000h Description: The memory limit registers indicate the upper address of a PCI memory address range. These

registers are used by the PCI1225 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1225 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 Kbytes of memory to CardBus).

I/O base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O base registers 0, 1 Type: Read-only, read/write Offset: 2Ch, 34h Default: 0000 0000h Description: The I/O base registers indicate the lower address of a PCI I/O address range. These registers

are used by the PCI1225 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K byte page, and the upper sixteen bits (31–16) are a page register which locates this 64K byte page in 32-bit PCI I/O address space. Bits 31–2 are read/write. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary.

NOTE:

Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.

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I/O limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O limit registers 0, 1 Type: Read-only, read/write Offset: 30h, 38h Default: 0000 0000h Description: The I/O limit registers indicate the upper address of a PCI I/O address range. These registers

are used by the PCI1225 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the appropriate I/O base) on doubleword boundaries.

Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write transactions to read-only bits have no effect. The PCI1225 assumes that the lower two bits of the limit address are 1s.

NOTE:

The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.

interrupt line register

Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1

Register: Interrupt line Type: Read/write Offset: 3Ch Default: FFh Description: The interrupt line register is read/write and is used to communicate interrupt line routing

information. Each PCI1225 function has an interrupt line register.

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interrupt pin register

Bit 7 6 5 4 3 2 1 0 Name Interrupt pin Type R R R R R R R R Default 0 0 0 0 0 0 1 1

Register: Interrupt pin Type: Read-only Offset: 3Dh Default: Depends on the interrupt signaling mode (sample shown is 03h) Description The value read from the interrupt pin register is function dependent and depends on the

interrupt signaling mode, selected through the device control register and the state of the INTRTIE bit in the system control register. When the INTRTIE bit is set, this register reads 0x01 (INTA contents.

) for both functions. See Table 22 for the complete description of the register

Table 22. Interrupt Pin Register Cross Reference

INTERRUPT SIGNALING MODE

Parallel PCI interrupts only 1 01h (INTA) 01h (INTA) Parallel IRQ and parallel PCI interrupts 1 01h (INTA) 01h (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts IRQ and PCI serialized (IRQSER) interrupts

†

When configuring the PCI1225 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit.

†

INTRTIE

BIT

†

1 01h (INTA) 01h (INTA) 1 01h (INTA) 01h (INTA)

INTPIN

FUNCTION 0

INTPIN

FUNCTION 1

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bridge control register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Bridge control Type R R R R R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R Default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0

Register: Bridge control Type: Read-only, read/write (see individual bit descriptions) Offset: 3Eh (functions 0, 1) Default: 0340h Description: The bridge control register provides control over various PCI1225 bridging functions. Some

bits in this register are global and should be accessed only through function 0. See Table 23 for a complete description of the register contents.

Table 23. Bridge Control Register

BIT SIGNAL TYPE FUNCTION

15–1 1 RSVD R Reserved. Bits 15–11 return 0s when read.

Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables

10 POSTEN R/W

9 PREFETCH1 R/W

8 PREFETCH0 R/W

7 INTR R/W

6 CRST R/W

†

MABTMODE R/W

4 RSVD R Reserved. Bit 4 returns 0 when read. 3 VGAEN R/W

2 ISAEN R/W

†

These bits are global and should be accessed only through function 0.

CSERREN R/W

†

CPERREN R

posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles. Note that burst write data can be posted, but various write transactions may not. Bit 10 is socket dependent and is not shared between functions 0 and 1.

Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. Bit 9 is encoded as:

Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is encoded as:

PCI interrupt – IREQ routing enable. Bit 7 is used to select whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers.

CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted by passing a PRST assertion to CardBus.

Master abort mode. Bit 5 controls how the PCI1225 responds to a master abort when the PCI1225 is an initiator on the CardBus interface. This bit is common between each socket.

VGA enable. Bit 3 affects how the PCI1225 responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded.

ISA mode enable. Bit 2 affects how the PCI1225 passes I/O cycles within the 64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI1225 does not forward the last 768 bytes of each 1K I/O range to CardBus.

CSERR enable. Bit 1 controls the response of the PCI1225 to CSERR signals on the CardBus bus. This bit is common between the two sockets.

CardBus parity error response enable. Bit 0 controls the response of the PCI1225 to CardBus parity errors. This bit is common between the two sockets.

0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default).

0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default).

0 = Functional interrupts routed to PCI interrupts (default) 1 = Functional interrupts routed by ExCAs

0 = CRST 1 = CRST asserted (default)

0 = Master aborts not reported (default) 1 = Signal target abort on PCI and SERR

0 = CSERR 1 = CSERR is forwarded to PCI SERR.

0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR

deasserted

(if enabled)

is not forwarded to PCI SERR.

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subsystem vendor ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Subsystem vendor ID Type: Read-only (read/write when bit 5 in the system control register is 0) Offset: 40h (functions 0, 1) Default: 0000h Description: The subsystem vendor ID register is used for system and option-card identification purposes

and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only.

subsystem ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Subsystem ID Type: Read-only (read/write when bit 5 in the system control register is 0) Offset: 42h (functions 0, 1) Default: 0000h Description: The subsystem ID register is used for system and option-card identification purposes and may

be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only.

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PC Card 16-bit I/F legacy-mode base address register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Register: PC Card 16-bit I/F legacy-mode base address Type: Read-only, read/write (see individual bit descriptions) Offset: 44h (functions 0, 1) Default: 0000 0001h Description: The PCI1225 supports the index/data scheme of accessing the ExCA registers, which are

mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. As specified in the shared by functions 0 and 1. See

PCI to PCMCIA CardBus Bridge Register Description

ExCA compatibility registers

on page 83 for register offsets.

(Yenta), this register is

system control register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System control Type R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name System control Type R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0

Register: System control Type: Read-only, read/write (see individual bit descriptions) Offset: 80h (functions 0, 1) Default: 0044 9060h Description: System-level initializations are performed through programming this doubleword register.

Some of the bits are global and should be written only through function 0. See Table 24 for a complete description of the register contents.

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Table 24. System Control Register

BIT SIGNAL TYPE FUNCTION

Serialized PCI interrupt routing step. Bits 31–30 are used to configure the serialized PCI interrupt stream signaling, and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31–30 are global to all PCI1225 functions.

31–30†SER_STEP R/W

Tie internal PCI interrupts. When this bit is set, the INT A and INTB signals are tied together internally

†

28 RSVD R Reserved. Bit 28 is read-only and returns 0 when read.

†

25 SMISTATUS R/W

†

23 RSVD R Reserved. This bit is read-only and returns 0 when read.

22 CBRSVD R/W

21 VCCPROT R/W

20 REDUCEZV R/W

19 CDREQEN R/W

18–16 CDMACHAN R/W

†

These bits are global and should be accessed only through function 0.

INTRTIE R/W

P2CCLK R/W

SMIROUTE R/W

SMIENB R/W

and are signaled as INTA all PCI1225 functions. When configuring the PCI1225 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit.

P2C power switch clock. The PCI1225 defaults CLOCK as an input clock to control the serial interface and the internal state machine. Bit 27 can be set to enable the PCI1225 to generate and drive the CLOCK from the PCI clock. When in a SUSPEND PCI1225 to successfully power down sockets after card removal without indicating to the system the removal event.

SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket.

SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to bit 25 clears the status.

SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling is enabled and generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).

CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated.

VCC protection enable. Bit 21 is socket dependent.

Reduced zoom video enable. When this bit is enabled, A25–A22 of the card interface for 16-bit PC Cards is placed in the high impedance state. This bit should not be set for normal ZV operation. This bit is encoded as:

PC/PCI DMA card enable. When bit 19 is set, the PCI1225 allows 16-bit PC Cards to request PC/PCI DMA using the DREQ

PC/PCI DMA channel assignment. Bits 18–16 are encoded as:

00 = INTA 01 = INTA 10 = INTA 11 = INTA

0 = CLOCK provided externally, input to PCI1225 (default) 1 = CLOCK generated by PCI clock and driven by PCI1225

0 = PC Card power change interrupts routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes.

0= SMI interrupt signaled (default) 1 = SMI interrupt not signaled

0 = 3-state CardBus RSVD 1 = Drive Cardbus RSVD low (default)

0 = VCC protection enabled for 16-bit cards (default) 1 = VCC protection disabled for 16-bit cards

0 = Reduced zoom video disabled (default) 1 = Reduced zoom video enabled

0 = Ignore DREQ 1 = Signal DMA request on DREQ

0–3 = 8-bit DMA channels 4 = PCI master; not used (default). 5–7 = 16-bit DMA channels

/INTB signal in INTA/INTB IRQSER slots /INTB signal in INTB/INTC IRQSER slots /INTB signal in INTC/INTD IRQSER slots

/INTB signal in INTD/INTA IRQSER slots

. INTA can then be shifted by using the SER_STEP bits. This bit is global to

signaling. DREQ is selected through the socket DMA register 0.

signaling from PC Cards (default)

state, however, CLOCK must be input to the

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Table 24. System Control Register (Continued)

BIT SIGNAL TYPE FUNCTION

Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to

†

These bits are global and should be accessed only through function 0.

MRBURSTDN R/W

†

MRBURSTUP R/W

13 SOCACTIVE R

12 RSVD R Reserved. Bit 12 is read-only and returns 1 when read.

†

PWRSTREAM R

†

8 INTERROGATE R

7 RSVD R Reserved. Bit 7 is read-only and returns 0 when read. 6 PWRSAVINGS R/W

†

2 RSVD R Reserved

†

0 RIMUX R/W

DELAYUP R

DELAYDOWN R

SUBSYSRW R/W

CB_DPAR R/W

CDMA_EN R/W

KEEPCLK R/W

burst downstream.

Memory read burst enable upstream. When bit 14 is set, the PCI1225 allows memory read transactions to burst upstream.

Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and is cleared upon read of this status bit. This bit is socket dependent.

Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. This bit is cleared when the power stream is complete.

Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has expired.

Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay has expired.

Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. This bit is socket dependent.

Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock, the applicable CB state machine will not be clocked.

Subsystem ID (SSID), subsystem vendor ID (SSVID), ExCA ID, and revision register read/write enable. Bit 5 is shared by functions 0 and 1.

CardBus data parity SERR signaling enable

PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set if MFUNC0–MFUNC6 are configured for centralized DMA.

Keep clock. This bit works with PCI and CB CLKRUN protocols.

RI_OUT/PME multiplex enable.

0 = Downstream memory read burst is disabled. 1 = Downstream memory read burst is enabled (default).

0 = Upstream memory read burst is disabled (default). 1 = Upstream memory read burst is enabled.

0 = No socket activity (default) 1 = Socket activity

0 = Power stream is complete and delay has expired. 1 = Power stream is in progress.

0 = Interrogation not in progress (default) 1 = Interrogation in progress

0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read-only (default).

0 = CardBus data parity not signaled on PCI SERR 1 = CardBus data parity signaled on PCI SERR

0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled

0 = Allows normal functioning of both CLKRUN 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN

0 = RI_OUT and PME are both routed to the RI_OUT/PME

at the same time, RI_OUT

1 = Only PME

is routed to the RI_OUT/PME terminal.

has precedence over PME.

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

protocols.(default)

protocols.

terminal. If both are enabled

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multifunction routing register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Multifunction routing Type R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Multifunction routing Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Multifunction routing Type: Read-only, read/write (see individual bit descriptions) Offset: 8Ch (functions 0, 1) Default: 0000 0000h Description: The multifunction routing register is used to configure the MFUNC0–MFUNC6 terminals.

These terminals may be configured for various functions. All multifunction terminals default to the general-purpose input configuration. Pullup resistors are required for terminals configured as outputs. This register is intended to be programmed once at power-on initialization. The default value for this register may also be loaded through a serial bus EEPROM. See Table 25 for a complete description of the register contents.

Table 25. Multifunction Routing Register

BIT SIGNAL TYPE FUNCTION

31–28 RSVD R Bits 31–28 are read/only and return 0s when read.

Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal as follows:

27–24 MFUNC6 R/W

0000 – RSVD = Reserved input – high impedance (default) 0001 – CLKRUN 0010 – IRQ2 = Parallel ISA type IRQ2 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – IRQ6 = Parallel ISA type IRQ6 0111 – IRQ7 = Parallel ISA type IRQ7 1000 – IRQ8 = Parallel ISA type IRQ8 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – IRQ12 = Parallel ISA type IRQ12 1101 – IRQ13 = Parallel ISA type IRQ13 1110 – IRQ14 = Parallel ISA type IRQ14 1111 – IRQ15 = Parallel ISA type IRQ15

= PCI clock control signal

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Table 25. Multifunction Routing Register (Continued)

BIT SIGNAL TYPE FUNCTION

Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal as follows:

23–20 MFUNC5 R/W

Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal as follows:

0000 – GPI4 = General-purpose input (default) 0001 – GPO4 = General-purpose output 0010 – PCGNT 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL1 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – LEDA1 = Socket 0 activity LED 1101 – LED_SKT = Socket 0 or socket 1 activity LED 1110 – GPE 1111 – IRQ15 = Parallel ISA type IRQ15

= PC/PCI (centralized) DMA grant

= Zoom video function 1 select output

= General-Purpose event signal

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

19–16 MFUNC4 R/W

15–12 MFUNC3 R/W

NOTE: When the serial bus mode is implemented by pulling down the LATCH terminal, the MFUNC4 terminal provides the SCL signaling.

0000 – GPI3 = General-purpose input (default) 0001 – GPO3 = General-purpose output 0010 – LOCK 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL1 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – RI_OUT 1101 – LED_SKT = Socket 0 or socket 1 activity LED 1110 – GPE 1111 – IRQ15 = Parallel ISA type IRQ15

Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal as follows:

0000 – RSVD = Reserved input – high impedance (default) 0001 – IRQSER = Serial interrupt stream, IRQ and optional PCI 0010 – IRQ2 = Parallel ISA type IRQ2 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – IRQ6 = Parallel ISA type IRQ6 0111 – IRQ7 = Parallel ISA type IRQ7 1000 – IRQ8 = Parallel ISA type IRQ8 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – IRQ12 = Parallel ISA type IRQ12 1101 – IRQ13 = Parallel ISA type IRQ13 1110 – IRQ14 = Parallel ISA type IRQ14 1111 – IRQ15 = Parallel ISA type IRQ15

PCI = Atomic transfer support mechanism

= Zoom video function 1 select output

= Ring-indicate output

= General-purpose event signal

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Table 25. Multifunction Routing Register (Continued)

BIT SIGNAL TYPE FUNCTION

Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal as follows:

11–8 MFUNC2 R/W

Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows:

0000 – GPI2 = General-purpose input (default) 0001 – GPO2 = General-purpose output 0010 – PCREQ 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL0 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – RI_OUT 1101 – LEDA2 = Socket 1 activity LED 1110 – GPE 1111 – IRQ7 = Parallel ISA type IRQ7

= PC/PCI (centralized) DMA request

= Zoom video function 0 select output

= Ring-indicate output

= General-purpose event signal

7–4 MFUNC1 R/W

3–0 MFUNC0 R/W

NOTE: When the serial bus mode is implemented by pulling down the LATCH terminal, the MFUNC1 terminal provides the SDA signaling.

0000 – GPI1 = General-purpose input (default) 0001 – GPO1 = General-purpose output 0010 – INTB 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL0 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – LEDA1 = Socket 0 activity LED 1101 – LEDA2 = Socket 1 activity LED 1110 – GPE 1111 – IRQ15 = Parallel ISA type IRQ15

Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal as follows:

0000 – GPI0 = General-purpose input (default) 0001 – GPO0 = General-purpose output 0010 – INTA 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL0 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – LEDA1 = Socket 0 activity LED 1101 – LEDA2 = Socket 1 activity LED 1110 – GPE 1111 – IRQ15 = Parallel ISA type IRQ15

= PCI interrupt signal, INTB

= Zoom video function 0 select output

= General-purpose event signal

= PCI interrupt signal, INTA

= Zoom video function 0 select output

= General-purpose event signal

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retry status register

Bit 7 6 5 4 3 2 1 0 Name Retry status Type R/W R/W R/C R R/C R R/C R Default 1 1 0 0 0 0 0 0

Register: Retry status Type: Read-only, read/write, read/clear (see individual bit descriptions) Offset: 90h (functions 0, 1) Default: C0h Description: The retry status register enables the retry timeout counters and displays the retry expiration

status. The flags are set when the PCI1225 retries a PCI or CardBus master request, and the master does not return within 2 bit. These bits are expected to be incorporated into the PCI command, PCI status, and bridge control registers by the PCI SIG. Access this register only through function 0. See Table 26 for a complete description of the register contents.

Table 26. Retry Status Register

BIT SIGNAL TYPE FUNCTION

PCI retry time-out counter enable. Bit 7 is encoded:

7 PCIRETRY R/W

†

CBRETRY R/W

5 TEXP_CBB R/C

4 RSVD R Reserved. Bit 4 returns 0 when read.

†

TEXP_CBA R/C

2 RSVD R Reserved. Bit 2 returns 0 when read.

1 TEXP_PCI R/C

0 RSVD R Reserved. Bit 0 returns 0 when read.

†

These bits are global and should be accessed only through function 0.

CardBus retry time-out counter enable. Bit 6 is encoded:

CardBus target B retry expired. Write a 1 to clear bit 5.

CardBus target A retry expired. Write a 1 to clear bit 3.

PCI target retry expired. Write a 1 to clear bit 1.

0 = PCI retry counter disabled 1 = PCI retry counter enabled (default)

0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default)

0 = Inactive (default) 1 = Retry has expired

0 = Inactive (default) 1 = Retry has expired.

PCI clock cycles. The flags are cleared by writing a 1 to the

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card control register

Bit 7 6 5 4 3 2 1 0 Name Card control Type R/W R/W R/W R R R/W R/W R/C Default 0 0 0 0 0 0 0 0

Register: Card control Type: Read-only, read/write, read/clear (see individual bit descriptions) Offset: 91h Default: 00h Description: The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through

this register, and the enable bit is shared between functions 0 and 1. See Table 27 for a complete description of the register contents.

Table 27. Card Control Register

BIT SIGNAL TYPE FUNCTION

Ring indicate output enable.

†

6 ZVENABLE R/W

5 PORT_SEL R/W

4–3 RSVD R Reserved. Bits 4–3 are read-only and default to 0.

2 AUD2MUX R/W

1 SPKROUTEN R/W

0 IFG R/C

†

This bit is global and should be accessed only through function 0.

RIENB R/W

Compatibility ZV mode enable. When set, the corresponding PC Card socket interface ZV terminals enter a high-impedance state. This bit defaults to 0.

Port select. This bit controls the priority for the ZVSEL0 and ZVSEL1 signaling if ZVENABLE is set in both functions.

CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding multifunction terminal which may be configured for CAUDPWM. When both socket 0 and 1 functions have AUD2MUX set, socket 0 takes precedence.

Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT . The SPKR The SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set. This bit is encoded as:

Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a functional interrupt is signaled from a PC Card interface and is socket dependent (i.e., not global). Write back a 1 to clear this bit.

0 = Disables any routing of RI_OUT 1 = Enables RI_OUT RIMUX is set to 0, and for routing to MFUNC2/4.

0 = Socket 0 takes priority, as signaled through ZVSEL0 1 = Socket 1 takes priority, as signaled through ZVSEL1

signal from socket 0 is exclusive ORed with the SPKR signal from socket 1 and sent to SPKROUT .

0 = SPKR 1 = SPKR

0 = No PC Card functional interrupt detected (default). 1 = PC Card functional interrupt detected.

to SPKROUT not enabled to SPKROUT enabled

signal for routing to the RI_OUT/PME terminal when

signal (default).

, when both sockets are in ZV mode. , when both sockets are in ZV mode.

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device control register

Bit 7 6 5 4 3 2 1 0 Name Device control Type R R/W R/W R R/W R/W R/W R/W Default 0 1 1 0 0 1 1 0

Register: Device control Type: Read-only, read/write (see individual bit descriptions) Offset: 92h (functions 0, 1) Default: 66h Description: The device control register is provided for PCI1130 compatibility and contains bits that are

shared between functions 0 and 1. The interrupt mode select is programmed through this register which is composed of PCI1225 global bits. The socket-capable force bits are also programmed through this register. See Table 28 for a complete description of the register contents.

Table 28. Device Control Register

BIT SIGNAL TYPE FUNCTION

7 RSVD R Reserved. Bit 7 Returns 0 when read.

†

3VCAPABLE R/W

5 IO16R2 R/W Diagnostic bit. This bit defaults to 1. 4 RSVD R Reserved. Bit 4 returns 0 when read. Write transactions have no effect.

†

2–1 INTMODE R/W

†

These bits are global and should be accessed only through function 0.

TEST R/W TI test. Only a 0 should be written to bit 3.

RSVD R/W Reserved. This read/write bit is reserved for test purposes. Only 0 should be written to this bit.

3-V socket capable force

0 = Not 3-V capable 1 = 3-V capable (default)

Interrupt mode. Bits 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded:

00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupt 11 = IRQ and PCI serialized interrupts (default)

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diagnostic register

Bit 7 6 5 4 3 2 1 0 Name Diagnostic Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 0 0 0 0 1

Register: Diagnostic Type: Read/write Offset: 93h (functions 0, 1) Default: 61h Description: The diagnostic register is provided for internal TI test purposes. It is a read/write register, but

only 0s should be written to this register. See Table 29 for a complete description of the register contents.

Table 29. Diagnostic Register

BIT SIGNAL TYPE FUNCTION

†

6 RSVD R/W Reserved. These bits are R/W with no function.

5 CSC R/W

4 3 2 1

0 ASYNC R/W

†

These bits are global and should be accessed only through function 0.

TRUE_VAL R/W

† † † †

DIAG4 R/W Diagnostic RETRY_DIS. Delayed transaction disable. DIAG3 R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. DIAG2 R/W Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. DIAG1 R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.

This bit defaults to 0. This bit is encoded as:

0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in reads from the PCI vendor ID and PCI device ID registers

CSC interrupt routing control

0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 bits 7:4 = 0000b (default). In this case, the setting of ExCA 803 bit 4 is a don’t care.

Asynchronous interrupt enable.

0 = CSC interrupt is not generated asynchronously 1 = CSC interrupt is generated asynchronously (default)

socket DMA register 0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Socket DMA register 0 Type: Read-only, read/write (see individual bit descriptions) Offset: 94h (functions 0, 1) Default: 0000 0000h Description: The socket DMA register 0 provides control over the PC Card DMA request (DREQ

) signaling.

See Table 30 for a complete description of the register contents.

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Table 30. Socket DMA Register 0

BIT SIGNAL TYPE FUNCTION

31–2 RSVD R Reserved. Bits 31–2 are read-only and return 0s when read.

DMA request (DREQ). Bits 1–0 indicate which terminal on the 16-bit PC Card interface acts as DREQ during DMA transfers. This field is encoded as:

1–0 DREQPIN R/W

socket DMA register 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket DMA register 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket DMA register 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00 = Socket not configured for DMA (default). 01 = DREQ 10 = DREQ 11 = DREQ

uses SPKR. uses IOIS16.

uses INPACK.

Register: Socket DMA register 1 Type: Read-only, read/write (see individual bit descriptions) Offset: 98h (functions 0, 1) Default: 0000 0000h Description: The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and

the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64 Kbytes of PCI I/O address space. See Table 31 for a complete description of the register contents.

NOTE:

32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits.

Table 31. Socket DMA Register 1

BIT SIGNAL TYPE FUNCTION

31–16 RSVD R Reserved. Bits 31–16 are read-only and return 0s when read.

DMA base address. Locates the socket DMA registers in PCI I/O space. This field represents a 16-bit PCI

15–4 DMABASE R/W

3 EXTMODE R Extended addressing. This feature is not supported by the PCI1225 and and always returns a 0.

2–1 XFERSIZE R/W

0 DDMAEN R/W

I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K-bytes of I/O address space. The lower four bits are hardwired to 0 and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary.

Transfer size. Bits 2–1 specify the width of the DMA transfer on the PC Card interface and are encoded as:

00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved

DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value of DMABASE.

0 = Disabled (default) 1 = Enabled

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capability ID register

Bit 7 6 5 4 3 2 1 0 Name Capability ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1

Register: Capability ID Type: Read-only Offset: A0h Default: 01h Description: The capability ID register identifies the linked list item as the register for PCI power

management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value.

next-item pointer register

Bit 7 6 5 4 3 2 1 0 Name Next-item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Next-item pointer Type: Read-only Offset: A1h Default: 00h Description: The next-item pointer register is used to indicate the next item in the linked list of the PCI power

management capabilities. Because the PCI1225 functions include only one capabilities item, this register returns 0s when read.

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power-management capabilities register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management capabilities Type R R R R R R R R R R R R R R R R Default 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1

Register: Power-management capabilities Type: Read-only (see individual bit descriptions) Offset: A2h (functions 0, 1) Default: 7E21h Description: The power-management capabilities register contains information on the capabilities of the

PC Card function related to power management. Both PCI1225 CardBus bridge functions support D0, D2, and D3 power states. See Table 32 for a complete description of the register contents.

Table 32. Power-Management Capabilities Register

BIT SIGNAL TYPE FUNCTION

PME support. This 5-bit field indicates the power states from which the PCI1225 supports asserting PME. A 0 for any bit indicates that the CardBus function cannot assert PME bits return 01111b when read. Each of these bits is described below:

15–1 1 PME_CAP R

10 D2_CAP R

9 D1_CAP R

8 DYN_DATA R

7–6 RSVD R Reserved. These bits are reserved and return 00b when read.

5 DSI R

4 AUX_PWR R

3 PMECLK R

2–0 VERSION R

D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device power state.

D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device power state.

Dynamic data support. Bit 8 returns a 0 when read, indicating that the CardBus function does not report dynamic power consumption data.

Device-specific initialization. Bit 5 is read-only and returns 1 when read, indicating that the CardBus controller functions require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it.

Auxiliary power source. Bit 4 is meaningful only if bit 15 (D3 indicates that the function supplies its own auxiliary power source.

PME clock. Bit 3 is read-only and returns 0 when read, indicating that no host bus clock is required for the PCI1225 to generate PME

Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power management (PM) registers as described in the Revision 1.0.

Bit 15 contains the value 0, indicating that PME Bit 14 contains the value 1, indicating that PME Bit 13 contains the value 1, indicating that PME Bit 12 contains the value 1, indicating that PME Bit 11 contains the value 1, indicating that PME

PCI Bus Power Management Interface Specification

can be asserted from the D0 state.

cold

from that power state. These five

cannot be asserted from D3 can be asserted from D3 can be asserted from D2 state. can be asserted from D1 state.

supporting PME) is set. When set, bit 4

hot

cold state.

state.

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power-management control/status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management control/status Type R/C R R R R R R R/W R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Power-management control/status Type: Read-only, read/write, read/clear (see individual bit descriptions) Offset: A4h (functions 0, 1) Default: 0000h Description: The power-management control/status register determines and changes the current power

state of the PCI1225 CardBus function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3 complete description of the register contents.

Table 33. Power-Management Control/Status Register

BIT SIGNAL TYPE FUNCTION

PME status. Bit 15 is set when the CardBus function would normally assert PME, independent

15 PMESTAT R/C

14–13 DATASCALE R

12–9 DATASEL R

8 R/W

7–2 RSVD R Reserved. Bits 7–2 are read-only and return 0s when read.

1–0 PWR_STATE R/W

of the state of the PME_EN bit. Bit 15 is cleared by a writeback of 1, and this also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect.

Data scale. This 2-bit field is read-only, returning 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit.

Data select. This 4-bit field is read-only and returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit.

PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, assertion of PME is disabled.

Power state. This 2-bit field is used both to determine the current power state of a function, and to set the function into a new power state. This field is encoded as:

00 = D0 01 = D1 10 = D2 11 = D3

hot

to D0 state. See Table 33 for a

hot

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power-management control/status register bridge support extensions

Bit 7 6 5 4 3 2 1 0 Name Power-management control/status register bridge support extensions Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Power-management control/status register bridge support extensions Type: Read-only Offset: A6h (functions 0, 1) Default: 00h Description: The power-management control/status register bridge support extensions support PCI bridge

specific functionality. See Table 34 for a complete description of the register contents.

Table 34. Power-Management Control/Status Register Bridge Support Extensions

BIT SIGNAL TYPE FUNCTION

7 BPCC_EN R Bus power/clock control. When read, bit 7 returns 1b. 6 B2_B3 R B2/B3 support for D3

5–0 RSVD R Reserved. These bits are read-only and return 0s when read.

. ThIs bit is read-only and returns a 0 when read.

hot

power management data register

Bit 7 6 5 4 3 2 1 0 Name Power management data Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Power management data Type: Read-only Offset: A7h (functions 0, 1) Default: 00h Description: The power management data register is read-only and returns zeros when read, since the

CardBus functions do not report dynamic data.

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general-purpose event status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management control/status Type R/C R/C R R R/C R R R/C R R R R/C R/C R/C R/C R/C Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: General-purpose event status Type: Read-only, read/clear (see individual bit descriptions) Offset: A8h (function 0) Default: 0000h Description: The general-purpose event status register contains status bits that are set when events occur

that are controlled by the general-purpose control register. The bits in this register and the corresponding GPE in this register do not depend upon the state of a corresponding bit in the general-purpose enable register. Access this register only through function 0. See Table 35 for a complete description of the register contents.

Table 35. General-Purpose Event Status Register

BIT SIGNAL TYPE FUNCTION

15 ZV0_STS R/C

14 ZV1_STS R/C

13–12 RSVD R Reserved. These bits are read-only and return zero when read.

11 PWR_STS R/C

10–9 RSVD R Reserved. These bits are read-only and return zero when read.

8 VPP12_STS R/C

7–5 RSVD R Reserved. These bits are read-only and return zero when read.

4 GP4_STS R/C GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level. 3 GP3_STS R/C GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level . 2 GP2_STS R/C GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level. 1 GP1_STS R/C GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level. 0 GP0_STS R/C GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.

are cleared by writing a 1 to the corresponding bit location. The status bits

PC card socket 0 ZV Status. Bit 15 is set on a change in status of the ZVENABLE bit in the function 0 PC card controller function of the PCI1225.

PC card socket 1 ZV Status. Bit 14 is set on a change in status of the ZVENABLE bit in the function 1 PC card controller function of the PCI1225.

Power change status. Bit 11 is set when software has changed the power state of either socket. A change in either VCC or VPP for either socket causes this bit to be set.

12-V VPP request status. Bit 8 is set when software has changed the requested VPP level to or from 12 V for either of the two PC Card sockets.

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general-purpose event enable register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name General-purpose event enable Type R/W R/W R R R/W R R R/W R R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: General-purpose event enable Type: Read-only, read/write (see individual bit descriptions) Offset: AAh (function 0) Default: 0000h Description: The general-purpose event enable register contains bits that are set to enable a GPE signal.

The GPE The GPE can only be signaled if one of the multifunction terminals, MFUNC6:0, is configured for GPE signaling. Access this register only through function 0. See Table 36 for a complete description of the register contents.

BIT SIGNAL TYPE FUNCTION

15 ZV0_EN R/W

14 ZV1_EN R/W

13–12 RSVD R Reserved. These bits are read-only and return zero when read.

11 PWR_EN R/W

10–9 RSVD R Reserved. These bits are read-only and return zero when read.

8 VPP12_EN R/W

7–5 RSVD R Reserved. These bits are read-only and return zero when read.

4 GP4_EN R/W

3 GP3_EN R/W

2 GP2_EN R/W

1 GP1_EN R/W

0 GP0_EN R/W

signal is driven until the corresponding status bit is cleared and the event is serviced.

Table 36. General-Purpose Event Enable Register

PC card socket 0 ZV enable. When bit 15 is set, a GPE is signaled on a change in status of ZVENABLE in the function 0 PC Card controller function of the PCI1225.

PC card socket 1 ZV enable. When bit 14 is set, a GPE is signaled on a change in status of ZVENABLE in the function 1 PC Card controller function of the PCI1225.

Power change enable. When bit 11 is set, a GPE is signaled on when software has changed the power state of either socket.

12-V VPP request enable. When bit 8 is set, a GPE is signaled when software has changed the requested VPP level to or from 12 V for either card socket.

GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5 terminal input level if configured as GPI4.

GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4 terminal input level if configured as GPI3.

GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2 terminal input if configured as GPI2.

GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1 terminal input if configured as GPI1.

GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0 terminal input if configured as GPI0.

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general-purpose input register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name General-purpose input Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 X X X X X

Register: General-purpose input Type: Read-only (see individual bit descriptions) Offset: ACh (function 0) Default: 00XXh Description: The general-purpose input register provides the logical value of the data input from the GPI

terminals, MFUNC5–MFUNC4 and MFUNC2–MFUNC0. Access this register only through function 0. See Table 37 for a complete description of the register contents.

Table 37. General-Purpose Input Register

BIT SIGNAL TYPE FUNCTION

15–5 RSVD R Reserved. Bits 15–5 are read-only and return 0 when read. Write transactions have no effect.

4 GPI4_DATA R

3 GPI3_DATA R

2 GPI2_DATA R

1 GPI1_DATA R

0 GPI0_DATA R

GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal. Write transactions have no effect.

GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal. Write transactions have no effect.

GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal. Write transactions have no effect.

GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal. Write transactions have no effect.

GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal. Write transactions have no effect.

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general-purpose output register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name General-purpose output Type R R R R R R R R R R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: General-purpose output Type: Read-only, read/write (see individual bit descriptions) Offset: AEh (function 0) Default: 0000h Description: The general-purpose output register is used for control of the general-purpose outputs.

Access this register only through function 0. See Table 38 for a complete description of the register contents.

Table 38. General-Purpose Output Register

BIT SIGNAL TYPE FUNCTION

15–5 RSVD R Reserved. Bits 15–5 are read-only and return 0 when read. Write transactions have no effect.

4 GPO4_DATA R/W

3 GPO3_DATA R/W

2 GPO2_DATA R/W

1 GPO1_DATA R/W

0 GPO0_DATA R/W

GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5 terminal if configured as GPO4. Read transactions return the last data value written.

GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4 terminal if configured as GPO3. Read transactions return the last data value written.

GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2 terminal if configured as GPO2. Read transactions return the last data value written.

GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1 terminal if configured as GPO1. Read transactions return the last data value written.

GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0 terminal if configured as GPO0. Read transactions return the last data value written.

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serial bus data register

Bit 7 6 5 4 3 2 1 0 Name Serial bus data Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Serial bus data Type: Read/write Offset: B0h (function 0) Default: 00h Description: The serial bus data register is for programmable serial bus byte reads and writes. This register

represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial bus slave address must be programmed with the 7-bit slave address, and the read/write indicator bit must be reset.

On byte reads, the byte address is programmed into the serial bus index register

the serial bus slave address must be programmed with the 7-bit slave address, the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register polled until clear. Then the contents of this register are valid read data from the serial bus interface. See Table 39 for a complete description of the register contents.

Table 39. Serial Bus Data Register

BIT SIGNAL TYPE FUNCTION

7–0 SBDATA R/W

Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid.

serial bus index register

Bit 7 6 5 4 3 2 1 0 Name Serial bus index Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Serial bus index Type: Read/write Offset: B1h (function 0) Default: 00h Description: The serial bus index register is for programmable serial bus byte reads and writes. This

register represents the byte address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator.

must be

On byte reads, the word address is programmed into this register

the serial bus slave address must be programmed with the 7-bit slave address, the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 40 for a complete description of the register contents.

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Table 40. Serial Bus Index Register

BIT SIGNAL TYPE FUNCTION

7–0 SBINDEX R/W

serial bus slave address register

Bit 7 6 5 4 3 2 1 0 Name Serial bus slave address Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Serial bus slave address Type: Read/write Offset: B2h (function 0) Default: 00h Description: The serial bus slave address register is for programmable serial bus byte read and write

transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit.

Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface.

On byte reads, the byte address is programmed into the serial bus index register must be programmed with the 7-bit slave address, the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 41 for a complete description of the register contents.

Table 41. Serial Bus Slave Address Register

BIT SIGNAL TYPE FUNCTION

7–1 SLAVADDR R/W

0 RWCMD R/W

Serial bus slave address. This bit field represents the slave address of a read or write transaction on the serial interface.

Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses.

0 = A byte write access is requested to the serial bus interface. 1 = A byte read access is requested to the serial bus interface.

this register

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serial bus control and status register

Bit 7 6 5 4 3 2 1 0 Name Serial bus control and status Type R/W R R R R/C R/W R/C R/C Default 0 0 0 0 0 0 0 0

Register: Serial bus control and status Type: Read-only, read/write, read/clear (see individual bit descriptions) Offset: B3h (function 0) Default: 00h Description: The serial bus control and status register is used to communicate serial bus status information

and select the quick command protocol. The REQBUSY bit in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 42 for a complete description of the register contents.

Table 42. Serial Bus Control and Status Register

BIT SIGNAL TYPE FUNCTION

Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte

7 PROT_SEL R/W

6 RSVD R Reserved. Bit 6 is read-only and returns zero when read.

5 REQBUSY R

4 ROMBUSY R

3 SBDETECT R/C

2 SBTEST R/W

1 REQ_ERR R/C

0 ROM_ERR R/C

protocol is used on read commands. The word address byte in the serial bus index register is not output by the PCI1225 when bit 7 is set.

Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write) is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register. Bit 5 must be polled on reads from the serial interface. After the byte read access has been requested, the read data is valid in the serial bus data register.

Serial EEPROM busy status. Bit 4 indicates the status of the PCI1225 serial EEPROM circuitry. Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM.

Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected. A pulldown resistor must be implemented on the LATCH terminal for bit 3 to be set. If bit 3 is reset, then the MFUNC4 and MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs.

Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.

Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1.

EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on invalid EEPROM data formats. See EEPROM data format. Bit 0 is cleared by a writeback of 1.

0 = Serial EEPROM circuitry is not busy 1 = Serial EEPROM circuitry is busy

0 = Serial bus interface not detected 1 = Serial bus interface detected

0 = Serial bus clock at normal operating frequency,  100 kHz (default) 1 = Serial bus clock frequency increased for test purposes

0 = No error detected during user requested byte read or write cycle 1 = Data error detected during user requested byte read or write cycle

serial bus interface implementation

0 = No error detected during auto-load from serial bus EEPROM 1 = Data error detected during auto-load from serial bus EEPROM

on page 31 for details on

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ExCA compatibility registers (functions 0 and 1)

The ExCA registers implemented in the PCI1225 are register-compatible with the Intel 82365SL–DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base +

1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base address register, which is shared by both card sockets. The of fsets from this base address run contiguous from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. See Figure 21 for an ExCA I/O mapping illustration.

Host I/O Space

PCI1225 Configuration Registers

PC Card A

ExCA

10hCard Bus Socket / ExCA Base Address

Index

Registers

Offset

00h

16–bit Legacy Mode Base Address

Note: The 16–bit legacy mode base address register is shared by function 0 and 1 as indicated by the shading.

44h

Figure 21. ExCA Register Access Through I/O

Data

PC Card B

ExCA

Registers

Offset of desired register is placed in the index register and the data from that location is returned in the data register.

3Fh

40h

7Fh

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ExCA compatibility registers (functions 0 and 1) (continued)

The TI PCI1225 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register (PCI offset 10h) at memory offset 800h. Each socket has a separate base address programmable by function. See Figure 22 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both functions 0 and 1. This illustration also identifies the CardBus socket register mapping, which are mapped into the same 4-Kbyte window at memory offset 0h.

PCI1225 Configuration Registers

Host

Memory Space

Host

Memory Space

. . .

CardBus Socket/ExCA Base Address

. .

16-bit Legacy-Mode Base Address

. . .

Note: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1.

10h

44h

CardBus Socket A Registers

ExCA Registers Card A

Offset 00h

20h

800h

844h

Offset 00h

CardBus Socket B Registers

20h

800h

ExCA Registers Card B

844h

Figure 22. ExCA Register Access Through Memory

The interrupt registers in the ExCA register set, as defined by the 82365SL–DL Specification, control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1225 to ensure that all possible PCI1225 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h.

Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity .

Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. (Table 43 identifies each ExCA register and its respective ExCA offset.) Memory windows have 4-Kbyte granularity.

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Table 43. ExCA Registers and Offsets

PCI MEMORY ADDRESS

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EXCA REGISTER NAME

Identification and revision 800 00 40 Interface status 801 01 41 Power control 802 02 42 Interrupt and general control 803 03 43 Card status change 804 04 44 Card status-change-interrupt configuration 805 05 45 Address window enable 806 06 46 I / O window control 807 07 47 I / O window 0 start-address low byte 808 08 48 I / O window 0 start-address high byte 809 09 49 I / O window 0 end-address low byte 80A 0A 4A I / O window 0 end-address high byte 80B 0B 4B I / O window 1 start-address low byte 80C 0C 4C I / O window 1 start-address high byte 80D 0D 4D I / O window 1 end-address low byte 80E 0E 4E I / O window 1 end-address high byte 80F 0F 4F Memory window 0 start-address low byte 810 10 50 Memory window 0 start-address high byte 811 11 51 Memory window 0 end-address low byte 812 12 52 Memory window 0 end-address high byte 813 13 53 Memory window 0 offset-address low byte 814 14 54 Memory window 0 offset-address high byte 815 15 55 Card detect and general control 816 16 56 Reserved 817 17 57 Memory window 1 start-address low byte 818 18 58 Memory window 1 start-address high byte 819 19 59 Memory window 1 end-address low byte 81A 1A 5A

Memory window 1 end-address high byte 81B 1B 5B Memory window 1 offset-address low byte 81C 1C 5C Memory window 1 offset-address high byte 81D 1D 5D Global control 81E 1E 5E Reserved 81F 1F 5F

PCI MEMORY ADDRESS

OFFSET (HEX)

ExCA OFFSET (HEX)

CARD A CARD B

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Table 43. ExCA Registers and Offsets (Continued)

EXCA REGISTER NAME

Memory window 2 start-address low byte 820 20 60 Memory window 2 start-address high byte 821 21 61 Memory window 2 end-address low byte 822 22 62 Memory window 2 end-address high byte 823 23 63 Memory window 2 offset-address low byte 824 24 64 Memory window 2 offset-address high byte 825 25 65 Reserved 826 26 66 Reserved 827 27 67 Memory window 3 start-address low byte 828 28 68 Memory window 3 start-address high byte 829 29 69 Memory window 3 end-address low byte 82A 2A 6A Memory window 3 end-address high byte 82B 2B 6B Memory window 3 offset-address low byte 82C 2C 6C Memory window 3 offset-address high byte 82D 2D 6D Reserved 82E 2E 6E Reserved 82F 2F 6F Memory window 4 start-address low byte 830 30 70 Memory window 4 start-address high byte 831 31 71 Memory window 4 end-address low byte 832 32 72 Memory window 4 end-address high byte 833 33 73 Memory window 4 offset-address low byte 834 34 74 Memory window 4 offset-address high byte 835 35 75 I/O window 0 offset-address low byte 836 36 76 I/O window 0 offset-address high byte 837 37 77 I/O window 1 offset-address low byte 838 38 78 I/O window 1 offset-address high byte 839 39 79 Reserved 83A 3A 7A Reserved 83B 3B 7B Reserved 83C 3C 7C Reserved 83D 3D 7D Reserved 83E 3E 7E Reserved 83F 3F 7F Memory window page 0 840 – – Memory window page 1 841 – – Memory window page 2 842 – – Memory window page 3 843 – – Memory window page 4 844 – –

PCI MEMORY ADDRESS

OFFSET (HEX)

ExCA OFFSET (HEX)

CARD A CARD B

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ExCA identification and revision register

Bit 7 6 5 4 3 2 1 0 Name ExCA identification and revision Type R R R/W R/W R/W R/W R/W R/W Default 1 0 0 0 0 1 0 0

Register: ExCA identification and revision Type: Read-only, read/write (see individual bit descriptions) Offset: CardBus socket address + 800h; Card A ExCA offset 00h

Card B ExCA offset 40h Default: 84h Description: This register provides host software with information on 16-bit PC Card support and Intel

82365SL-DF compatibility . See Table 44 for a complete description of the register contents.

Table 44. ExCA Identification and Revision Register

BIT SIGNAL TYPE FUNCTION

7–6 IFTYPE R 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation.

3–0 365REV R/W

Interface type. These read-only bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI1225. The PCI1225 supports both I/O and memory 16-bit PC cards.

Intel 82365SL-DF revision. This read/write field stores the Intel 82365SL-DF revision supported by the PCI1225. Host software can read this field to determine compatibility to the Intel This field defaults to 0100b upon PCI1225 reset.

82365SL-DF register set.

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ExCA interface status register

Bit 7 6 5 4 3 2 1 0 Name ExCA interface status Type R R R R R R R R Default 0 0 X X X X X X

Register: ExCA interface status Type: Read-only (see individual bit descriptions) Offset: CardBus socket address + 801h; Card A ExCA offset 01h

Card B ExCA offset 41h Default: 00XX XXXXb Description: This register provides information on the current status of the PC Card interface. An X in the

default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 45 for a complete description of the register contents.

Table 45. ExCA Interface Status Register

BIT SIGNAL TYPE FUNCTION

7 RSVD R Reserved. Bit 7 is read-only and returns 0 when read. Write transactions have no effect.

Card power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the power

6 CARDPWR R

5 READY R

4 CARDWP R

3 CDETECT2 R

2 CDETECT1 R

1–0 BVDSTAT R

control register is programmed. Bit 6 is encoded as:

Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.

Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to the PCI1225 whether or not the memory card is write protected. Furthermore, write protection for an entire PCI1225 16-bit memory window is available by setting the appropriate bit in the memory window offset high-byte register.

Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket.

Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket.

Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0 reflects BVD1.

When a 16-bit I/O card is inserted, this field indicates the status of SPKR the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.

0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on

0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer

0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read-only.

0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted.

0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted.

00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good

(bit 1) and STSCHG (bit 0) at

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ExCA power-control register

Bit 7 6 5 4 3 2 1 0 Name ExCA power control Type R/W R R R/W R/W R R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA power control Type: Read-only, read/write (see individual bit descriptions) Offset: CardBus socket address + 802h; Card A ExCA offset 02h

Card B ExCA offset 42h Default: 00h Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit outputs

on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 46 for a complete description of the register contents.

Table 46. ExCA Power-Control Register

BIT SIGNAL TYPE FUNCTION

Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1225. This bit is encoded as:

7 COE R/W

6–5 RSVD R Reserved. Bits 6–5 are read-only and return 0s when read. Write transactions have no effect.

VCC. Bits 4–3 are used to request changes to card VCC. This field is encoded as:

4–3 EXCAVCC R/W

2 RSVD R Reserved. Bit 2 is read-only and returns 0 when read. Write transactions have no effect.

VPP. Bits 1–0 are used to request changes to card VPP. The PCI1225 ignores this field unless VCC to the socket is enabled (i.e., 5 V or 3.3 V). This field is encoded as:

1–0 EXCAVPP R/W

0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled

00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3 .3V

00 = 0 V (default) 01 = V

10 = 12 V 11 = 0 V reserved

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ExCA interrupt and general-control register

Bit 7 6 5 4 3 2 1 0 Name ExCA interrupt and general control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA interrupt and general control Type: Read/write (see individual bit descriptions) Offset: CardBus socket address + 803h; Card A ExCA offset 03h

Card B ExCA offset 43h Default: 00h Description: This register controls interrupt routing for I/O interrupts, as well as other critical 16-bit

PC Card functions. See Table 47 for a complete description of the register contents.

Table 47. ExCA Interrupt and General-Control Register

BIT SIGNAL TYPE FUNCTION

7 RINGEN R/W

6 RESET R/W

5 CARDTYPE R/W

4 CSCROUTE R/W

3–0 INTSELECT R/W

Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:

Card reset. Bit 6 controls the 16-bit PC Card PRST, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as

Card type. Bit 5 indicates the PC card type. This bit is encoded as:

PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 in the ExCA card status change interrupt configuration register. This bit is encoded as:

Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as:

is ORed with ExCA bit 4 for backwards compatibility.

0 = Ring indicate disabled (default) 1 = Ring indicate enabled

0 = RESET signal asserted (default) 1 = RESET signal deasserted

0 = Memory PC Card installed (default) 1 = I/O PC Card installed

0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts.

0000 = No interrupt routing (default) . CSC interrupts routed to PCI interrupts. This bit setting

0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

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ExCA card status-change register

Bit 7 6 5 4 3 2 1 0 Name ExCA card status change Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: ExCA card status change Type: Read-only (see individual bit descriptions) Offset: CardBus socket address + 804h; Card A ExCA offset 04h

Card B ExCA offset 44h Default: 00h Description: The card status-change register controls interrupt routing for I/O interrupts as well as other

critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit writeback of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the global control register. See Table 48 for a complete description of the register contents.

Table 48. ExCA Card Status-Change Register

BIT SIGNAL TYPE FUNCTION

7–4 RSVD R Reserved. Bits 7–4 are read-only and return 0s when read. Write transactions have no effect.

Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card

3 CDCHANGE R

2 READYCHANGE R

1 BATWARN R

0 BATDEAD R

interface. This bit is encoded as:

0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2

Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1225 interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. This bit is encoded as:

0 = No low-to-high transition detected on READY (default)

1 = Detected low-to-high transition on READY When a 16-bit I/O card is installed, bit 2 is always 0. Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether

the source of a PCI1225 interrupt was due to a battery-low warning condition. This bit is encoded as:

0 = No battery warning condition (default)

1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0. Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates

whether the source of a PCI1225 interrupt was due to a battery dead condition. This bit is encoded as:

0 = STSCHG deasserted (default)

1 = STSCHG asserted Ring indicate. When the PCI1225 is configured for ring indicate operation, bit 0 indicates the status

of RI.

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ExCA card status-change-interrupt configuration register

Bit 7 6 5 4 3 2 1 0 Name ExCA status-change-interrupt configuration Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA card status-change-interrupt configuration Type: Read/write (see individual bit descriptions) Offset: CardBus socket address + 805h; Card A ExCA offset 05h

Card B ExCA offset 45h Default: 00h Description: This register controls interrupt routing for card status-change interrupts, as well as masking

CSC interrupt sources. See Table 49 for a complete description of the register contents.

Table 49. ExCA Card Status-Change-Interrupt Configuration Register

BIT SIGNAL TYPE FUNCTION

Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change interrupts. 0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set to 1b. In this case bit 4 of ExCA 803 is a don’t care. This is the default setting. 0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) is set to 0b. In this case,

7–4 CSCSELECT R/W

3 CDEN R/W

2 READYEN R/W

1 BATWARNEN R/W

0 BATDEADEN R/W

CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803 to 1b. This field is encoded as:

Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:

Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as:

Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as:

Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt.

0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes

0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation

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ExCA address window enable register

Bit 7 6 5 4 3 2 1 0 Name ExCA address window enable Type R/W R/W R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA address window enable Type: Read-only, read/write (see individual bit descriptions) Offset: CardBus socket address + 806h; Card A ExCA offset 06h

Card B ExCA offset 46h Default: 00h Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default,

all windows to the card are disabled. The PCI1225 does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 50 for a complete description of the register contents.

Table 50. ExCA Address Window Enable Register

BIT SIGNAL TYPE FUNCTION

I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:

7 IOWIN1EN R/W

I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:

6 IOWIN0EN R/W

5 RSVD R Reserved. Bit 5 is read-only and returns 0 when read. Write transactions have no effect.

Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is

4 MEMWIN4EN R/W

3 MEMWIN3EN R/W

2 MEMWIN2EN R/W

1 MEMWIN1EN R/W

0 MEMWIN0EN R/W

encoded as:

Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is encoded as:

Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is encoded as:

Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is encoded as:

Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is encoded as:

0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled

0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled

0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled

0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled

0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled

0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled

0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled

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ExCA I/O window control register

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window control Type: Read/write (see individual bit descriptions) Offset: CardBus socket address + 807h; Card A ExCA offset 07h

Card B ExCA offset 47h Default: 00h Description: This register contains parameters related to I/O window sizing and cycle timing. See Table 51

for a complete description of the register contents.

Table 51. ExCA

BIT SIGNAL TYPE FUNCTION

I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel

7 WAITSTATE1 R/W

6 ZEROWS1 R/W

5 IOSIS16W1 R/W

4 DATASIZE1 R/W

3 WAITSTATE0 R/W

2 ZEROWS0 R/W

1 IOSIS16W0 R/W

0 DATASIZE0 R/W

This bit is encoded as:

I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:

I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16

I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if the I/O window 1 IOIS16

I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel This bit is encoded as:

I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:

I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16

I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if the I/O window 0 IOIS16

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:

0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16

source bit (bit 5) is set. This bit is encoded as:

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:

0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16

source bit (bit 1) is set. This bit is encoded as:

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

I/O Window Control Register

82365SL-DF.

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ExCA I/O window 0 and 1 start-address low-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 48h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch; Card A ExCA offset 0Ch

Card B ExCA offset 4Ch Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0

and 1. The eight bits of these registers correspond to the lower eight bits of the start address.

ExCA I/O window 0 and 1 start-address high-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 49h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh; Card A ExCA offset 0Dh

Card B ExCA offset 4Dh Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

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ExCA I/O window 0 and 1 end-address low-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 4Ah

Card B ExCA offset 4Eh Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0

and 1. The eight bits of these registers correspond to the lower eight bits of the end address.

ExCA I/O window 0 and 1 end-address high-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 4Bh Register: ExCA

I/O window 1 end-address high byte

Offset: CardBus socket address + 80Fh; Card A ExCA offset 0Fh

Card B ExCA offset 4Fh Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

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ExCA memory window 0–4 start-address low-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 50h Register: ExCA memory window 1 start-address low byte Offset: CardBus socket address + 818h; Card A ExCA offset 18h

Card B ExCA offset 58h Register: ExCA memory window 2 start-address low byte Offset: CardBus socket address + 820h; Card A ExCA offset 20h

Card B ExCA offset 60h Register: ExCA memory window 3 start-address low byte

Offset: CardBus socket address + 828h; Card A ExCA offset 28h

Card B ExCA offset 68h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h; Card A ExCA offset 30h

Card B ExCA offset 70h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window start address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address.

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ExCA memory window 0–4 start-address high-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 51h Register: ExCA memory window 1 start-address high byte Offset: CardBus socket address + 819h; Card A ExCA offset 19h

Card B ExCA offset 59h Register: ExCA memory window 2 start-address high byte Offset: CardBus socket address + 821h; Card A ExCA offset 21h

Card B ExCA offset 61h Register: ExCA memory window 3 start-address high byte Offset: CardBus socket address + 829h; Card A ExCA offset 29h

Card B ExCA offset 69h Register: ExCA memory window 4 start-address high byte Offset: CardBus socket address + 831h; Card A ExCA offset 31h

Card B ExCA offset 71h Type: Read/write Default: 00h Description: These registers contain the high nibble of the 16-bit memory window start address for memory

windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 52 for a complete description of the register contents.

Table 52. ExCA Memory Window 0–4 Start-Address High-Byte Register

BIT SIGNAL TYPE FUNCTION

Data size. Bit 7 controls the memory window data width. This bit is encoded as:

7 DATASIZE R/W

Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel

6 ZEROWAIT R/W

5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 are read/write and have no effect on memory window operation. 3–0 STAHN R/W

Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window start address.

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

82365SL-DF. This bit is encoded as:

0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

16-bit cycles are reduced to equivalent of two ISA cycles.

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ExCA memory window 0–4 end-address low-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 52h Register: ExCA memory window 1 end-address low byte Offset: CardBus socket address + 81Ah; Card A ExCA offset 1Ah

Card B ExCA offset 5Ah Register: ExCA memory window 2 end-address low byte Offset: CardBus socket address + 822h; Card A ExCA offset 22h

Card B ExCA offset 62h Register: ExCA memory window 3 end-address low byte Offset: CardBus socket address + 82Ah; Card A ExCA offset 2Ah

Card B ExCA offset 6Ah Register: ExCA memory window 4 end-address low byte Offset: CardBus socket address + 832h; Card A ExCA offset 32h

Card B ExCA offset 72h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address.

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ExCA memory window 0–4 end-address high-byte register

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address high byte Type R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA offset 53h Register: ExCA memory window 1 end-address high byte Offset: CardBus socket address + 81Bh; Card A ExCA offset 1Bh

Card B ExCA offset 5Bh Register: ExCA memory window 2 end-address high byte Offset: CardBus socket address + 823h; Card A ExCA offset 23h

Card B ExCA offset 63h Register: ExCA memory window 3 end-address high byte Offset: CardBus socket address + 82Bh; Card A ExCA offset 2Bh

Card B ExCA offset 6Bh Register: ExCA memory window 4 end-address high byte Offset: CardBus socket address + 833h; Card A ExCA offset 33h

Card B ExCA offset 73h Type: Read-only, read/write (see individual bit descriptions) Default: 00h Description: These registers contain the high nibble of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register. See Table 53 for a complete description of the register contents.

Table 53. ExCA Memory Window 0–4 End-Address High-Byte Register

BIT SIGNAL TYPE FUNCTION

7–6 MEMWS R/W 5–4 RSVD R Reserved. Bits 5–4 are read-only and return 0s when read. Write transactions have no effect. 3–0 ENDHN R/W

Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits.

End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address.

100

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TEXAS INSTRUMENTS PCI1225 Technical data

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