TEXAS INSTRUMENTS PCI1225 Technical data

查询PCI1225供应商

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

 PCI Bus Power Management Interface

Specification 1.0 Compliant

 ACPI 1.0 Compliant
 Fully Compatible With the Intel 430TX

(Mobile Triton II) Chipset

 Packaged in a 208-Pin Low-Profile QFP

(PDV) or GHK High Density Ball Grid Array
(BGA)

 PCI Local Bus Specification Revision 2.2

Compliant

 1997 PC Card Standard Compliant
 PC 99 Compliant
 3.3-V Core Logic With Universal PCI

Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments

 Mix-and-Match 5-V/3.3-V 16-bit PC Cards

and 3.3-V CardBus Cards

 Supports Two PC Card or CardBus Slots

With Hot Insertion and Removal

 Uses Serial Interface to TI TPS2202/2206

Dual-Slot PC Card Power Switch

 Supports Burst Transfers to Maximize Data

Throughput on the PCI Bus and CardBus
Bus

 Supports Parallel PCI Interrupts, Parallel

ISA IRQ and Parallel PCI Interrupts, Serial
ISA IRQ With Parallel PCI Interrupts, and
Serial ISA IRQ and PCI Interrupts

 Serial EEPROM Interface for Loading

Subsystem ID and Subsystem Vendor ID

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T erminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Name/Terminal Number Sort Tables 6. . . . . . . . . . . . . . . . . . . . . . . . . .

T erminal Functions 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Sequencing 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Rail Voltages 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Component Interconnect (PCI) Interface 23. . . . . . . . . . . . . . . .

PC Card Applications 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Bus Interface 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Controller Programming Model 45. . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Configuration Registers (Functions 0 and 1) 46. . . . . . . . . . . . . . . . . . .

ExCA Compatibility Registers (Functions 0 and 1) 83. . . . . . . . . . . . . . . . . .

 Pipelined Architecture Allows Greater Than

130-MBps Throughput From
CardBus-to-PCI and From PCI-to-CardBus

 Supports up to Five General-Purpose I/Os
 Programmable Output Select for CLKRUN
 Multifunction PCI Device With Separate

Configuration Space for Each Socket

 Five PCI Memory Windows and T wo I/O

Windows Available for Each R2 Socket

 Two I/O Windows and Two Memory

Windows Available to Each CardBus
Socket

 Exchangeable Card Architecture (ExCA)

Compatible Regesters Are Mapped in
Memory and I/O Space

 Intel 82365SL-DF Register Compatible
 Supports Distributed DMA (DDMA) and

PC/PCI DMA

 Supports 16-Bit DMA on Both PC Card

Sockets

 Supports Ring Indicate, SUSPEND, PCI

CLKRUN, and CardBus CCLKRUN

 LED Activity Pins
 Supports PCI Bus Lock (LOCK)
 Advanced Submicron, Low-Power CMOS

T echnology

CardBus Socket Registers (Functions 0 and 1) 106. . . . . . . . . . . . . . . . . . . . . .

Distributed DMA (DDMA) Registers 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 124. . . . . . . . . . . . . . . . . . . . . . .

PC Card Cycle Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements (Memory Cycles) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements (I/O Cycles) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics (Miscellaneous 127. . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Parameter Measurement Information 128. . . . . . . . . . . . . . . . . . . . . . .

Mechanical Data 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

description

The TI PCI1225 is a high-performance PCI-to-PC Card controller that supports two independent card sockets
compliant with the 1997 PC Card Standard. The PCI1225 provides a rich feature set that makes it the best
choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card
Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2 and defines the new 32-bit
PC Card (CardBus), capable of full 32-bit data transfers at 33 MHz. The PCI1225 supports any combination
of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1225 is compliant with the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI
master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers
or CardBus PC Card bridging transactions. The PCI1225 is also compliant with the latest

Management Interface Specification

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1225
is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1225 internal data path logic allows
the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architacture provide an unsurpassed performance level with sustained bursting. The
PCI1225 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to
implement sideband functions. Many other features designed into the PCI1225, such as socket activity
light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.

.

PCI Bus Power

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low
system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable
the host power management system to further reduce power consumption.

Unused PCI1225 inputs must be pulled up using a 43-k resistor.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

system block diagram

A simplified block diagram of the PCI1225 is provided below. The PCI interface includes all address/data and
control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and
serialized PCI and ISA signaling. Miscellaneous system interface terminals include multifunction terminals:
SUSPEND

, RI_OUT/PME (power management control signal), and SPKROUT.

PCI Bus

INTA

Activity LEDs

INTB

Interrupt

Controller

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed

video signals to the VGA controller and audio subsystem.

3

PCI1225

68 68

23

23

IRQSER

3

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

19

Zoom Video

4

IRQ2–15

VGA

Controller

Audio

Subsystem

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

terminal assignments

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

C/BE3

RI_OUT/PME

V

CC

AD25

PRST

GND

GNT

REQ
AD31
AD30
AD11
AD29
AD28

V

CC
AD27
AD26

V

CCP

AD24

PCLK

GND

IDSEL

AD23
AD22
AD21
AD20

V

CC
AD19
AD18
AD17
AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP
PERR
SERR

V

CC

PAR

C/BE1

AD15
AD14
AD13

GND

AD12

SUSPEND

GND

MFUNC0

DATA

SPKROUT

LATCH

CLOCK

152

151

150

149

VCCI

148

MFUNC1

154

153

156

155

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_CAD31

A_CAD30

A_RSVD

146

145

147

V

A_CAD28

A_CAD29

142

144

143

A_CCD2

A_CAD27

A_CCLKRUN

140

139

141

A_CAUDIO

A_CSTSCHG

138

137

CC

A_CINT

A_CSERR

A_CVS1

134

136

135

A_CAD25

A_CAD26

A_CAD24

132

131

133

PCI1225 CorePCI

A_CC/BE3

A_CAD23

GND

128

130

129

Card A

A_CAD21

A_CAD22

A_CREQ

126

125

127

A_CRST

124

A_CAD20

A_CAD19

A_CVS2

122

121

123

Card B

CCA

V

A_CAD18

119

120

A_CC/BE2

A_CAD17

118

117

CC

A_CFRAME

A_CTRDY

A_CIRDY

114

113

116

115

A_CCLKVA_CDEVSEL

112

A_CGNT

111

110

A_CSTOP

A_CBLOCK

A_CPERR

108

107

109

A_RSVD

A_CPAR

105
104

103
102
101
100

51 106

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53

A_CC/BE1
A_CAD16
A_CAD14
A_CAD15
A_CAD12
A_CAD13
A_CAD11
A_CAD10
GND
A_CAD9
A_CC/BE0
A_CAD8
A_CAD7
A_RSVD
A_CAD5
A_CAD6
A_CAD3
A_CAD4

V

CC
A_CAD1
A_CAD2
A_CAD0
A_CCD1
B_CAD31
B_RSVD
B_CAD30
B_CAD29
B_CAD28
B_CAD27
GND
B_CCD2
B_CCLKRUN
B_CSTSCHG
B_CAUDIO
B_CSERR
B_CINT
B_CVS1
B_CAD26
B_CAD25
B_CAD24
V

CC
B_CC/BE3

B_CAD23
B_CREQ
B_CAD22
B_CAD21
B_CRST
B_CAD20
B_CVS2
B_CAD19
B_CAD18
B_CAD17

CCP

V

AD10

AD9

AD8

AD7

C/BE0

CC

AD6

AD5

AD3

AD1

AD0

AD2

AD4

V

GND

B_CAD0

B_CAD2

B_CCD1

B_CAD1

B_CAD4

B_CAD3

GND

B_CAD6

B_CAD5

B_CAD7

B_RSVD

B_CAD8

B_CAD9

B_CAD10

B_CC/BE0

CC

V

B_CAD11

B_CAD13

B_CAD14

B_CAD12

B_CAD15

CCB

V

B_CAD16

B_CC/BE1

B_CPAR

B_RSVD

B_CBLOCK

GND

B_CSTOP

B_CPERR

B_CCLK

B_CGNT

B_CDEVSEL

B_CIRDY

B_CTRDY

B_CFRAME

B_CC/BE2

PCI-to-CardBus Terminal Diagram

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

terminal assignments (continued)

PDV LOW-PROFILE QUAD FLAT PACKAGE

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

TOP VIEW

MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

C/BE3

RI_OUT/PME

V

CC

AD25

PRST

GND

GNT

REQ
AD31
AD30
AD11
AD29
AD28

V

CC
AD27
AD26

V

CCP

AD24

PCLK

GND

IDSEL

AD23
AD22
AD21
AD20

V

CC
AD19
AD18
AD17

AD16

C/BE2

FRAME

GND
IRDY

TRDY

DEVSEL

STOP
PERR
SERR

V

CC

PAR

C/BE1

AD15
AD14
AD13

GND

AD12

A_D10

A_D2

146

147

A_D9

A_D1

144

145

CC

V

143

A_D8

A_D0

142

141

A_CD2

A_WP(IOIS16)

140

139

A_BVD1(STSCHG/RI)

A_READY(IREQ)

A_WAIT

A_A0

A_VS1

A_A2

136

135

134

133

A_A1

132

131

A_BVD2(SPKR)

138

137

PCI1225 CorePCI

A_REG

GND

130

129

Card A

A_A3

128

A_INPACK

127

A_A4

126

A_A5

125

CCI

SPKROUT

GND

MFUNC0

DATA

LATCH

CLOCK

152

151

150

149

V

148

SUSPEND

MFUNC1

154

153

156

155

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_A6

A_RESET

A_VS2

122

124

123

Card B

CCA

A_A25

V

120

121

A_A7

119

A_A24

118

A_A23

A_A12

116

117

A_A22

A_A15

114

115

CC

A_A16VA_A21

112

113

111

A_A20

A_WE

110

109

A_A19

A_A14

108

107

A_A18

A_A13

105

104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53

51 106

A_A8
A_A17
A_A9
A_IOWR
A_A11
A_IORD
A_OE
A_CE2
GND
A_A10
A_CE1
A_D15
A_D7
A_D14
A_D6
A_D13
A_D5
A_D12

V

CC
A_D4
A_D11
A_D3
A_CD1
B_D10
B_D2
B_D9
B_D1
B_D8
B_D0
GND
B_CD2
B_WP(IOIS16)
B_BVD1(STSCHG/RI)
B_BVD2(SPKR)
B_WAIT
B_READY(IREQ)
B_VS1
B_A0
B_A1
B_A2
V

CC
B_REG
B_A3
B_INPACK
B_A4
B_A5
B_RESET
B_A6

B_VS2
B_A25
B_A7
B_A24

CCP

V

AD9

AD10

AD8

AD7

C/BE0

CC

AD4

AD6

AD5

AD3

AD1

AD0

V

AD2

GND

B_D3

B_CD1

B_D11

B_D4

B_D5

B_D12

GND

B_D6

B_D13

B_D7

B_D14

B_D15

B_CE1

B_A10

B_CE2

V

CC

B_OE

B_IORD

B_A11

B_IOWR

B_A9

CCB

V

B_A17

B_A8

B_A18

B_A13

B_A19

GND

B_A14

B_WE

B_A20

B_A21

B_A16

B_A15

B_A22

B_A23

B_A12

PCI-to-PC Card (16-Bit) Terminal Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

terminal assignments (continued)

W

V
U
T
R
P
N

M

L
K
J
H
G
F
E
D
C
B
A

GHK PLASTIC BALL GRID ARRAY

BOTTOM VIEW

1

3

2

75

9

6

4

810

12

13141511

16

18

1917

signal names and terminal assignments

Table 1 and Table 2 show the terminal assignments for the CardBus PC Card; Table 3 and Table 4 show the
terminal assignments for the 16-bit PC Card; Table 1 and Table 3 show the CardBus PC Card and the 16-bit
PC Card terminals sorted alphanumerically by the associated GHK package terminal number; and Table 2 and
Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal
name and its associated terminal numbers.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TERM. NO.

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

GHK PDV

D1 1
A4 208
E6 206
C6 202

F7 198
E8 194
A8 190
B9 186

C10 182
E11 178
A12 174
A13 170
A14 166
A15 162
E14 159
C15 158
A16 157

E3 2
C5 207
B5 205
A5 203
A6 199
A7 195
B8 191
C9 187

E10 183
F11 179
A11 175
E12 171
F12 167
C14 163
F13 160
E17 155
D19 156

F5 3
G6 4
E2 5

F6 204
B6 200
B7 196
C8 192

F9 188

F10 184
A10 180
B11 176
C12 172
C13 168
B14 164
B15 161
E18 153
F15 154

E1 6

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

T able 1. CardBus PC Card Signal Names by GHK/PDV Terminal Number

V

CCP

AD12
AD13
PAR
STOP
GND
AD17
AD20
IDSEL
V

CCP

AD28
AD31
PRST
C/BE3
MFUNC4
MFUNC3
MFUNC2
AD10
GND
AD14
C/BE1
PERR
IRDY
AD16
V

CC

AD23
AD24
V

CC

AD30
GND
RI_OUT/PME
MFUNC5
MFUNC1
SUSPEND
AD9
AD8
C/BE0
AD15
SERR
TRDY
C/BE2
AD19
AD22
PCLK
AD27
AD11
GNT
V

CC

MFUNC6/CLKRUN
GND
MFUNC0
AD7

TERM. NO.

GHK PDV

F3 7
F2 8
E7 201
C7 197
F8 193
E9 189

A9 185
B10 181
C11 177
B12 173
B13 169
E13 165
G15 149
F14 152
E19 151
F17 150

F1 10

H6 11

G3 12

G5 9
G17 145
F18 148
F19 147
G14 146

G1 14

H5 15
H3 16

G2 13
H14 141
G18 144
G19 143
H15 142

H1 18
J1 19
J2 20

H2 17
J15 137
H17 140
H18 139
H19 138

J5 22

J6 23

K1 24

J3 21
J19 133
J14 136
J17 135
J18 134

K3 26

K5 27

K6 28

K2 25

V

CC

AD6
V

CC

DEVSEL
FRAME
AD18
AD21
GND
AD26
AD29
REQ
AD25
SPKROUT
DATA
CLOCK
LATCH
AD4
AD3
AD2
AD5
A_CAD30
V

CCI

A_CAD31
A_RSVD
AD1
AD0
B_CCD1
GND
A_CAD27
A_CAD29
V

CC

A_CAD28
B_CAD2
B_CAD1
B_CAD4
B_CAD0
A_CAUDIO
A_CCD2
A_CCLKRUN
A_CSTSCHG
GND
B_CAD6
B_CAD5
B_CAD3
A_CAD26
A_CSERR
A_CINT
A_CVS1
B_CAD7
B_CAD8
B_CC/BE0
B_RSVD

TERM. NO.

GHK PDV

K18 129
K14 132
K15 131
K17 130

L2 30
L3 31
L6 32

L1 29
L17 125
K19 128
L14 127
L15 126

M1 34
M2 35
M3 36

L5 33

M18 121

L18 124
L19 123

M19 122

M5 38

N1 39

N2 40

M6 37

N18 117
M17 120
M15 119

N19 118

N6 42
P1 43
P2 44

N3 41
N15 113
N17 116

M14 115

P19 114

P3 46

R1 47

P6 48

N5 45

R7 61

V7 65

V8 69

U9 73
V10 77

W11 81

R11 85
P12 89
U13 93
R13 97
P18 112
P17 111

GND
A_CAD25
A_CAD24
A_CC/BE3
B_CAD10
V

CC

B_CAD11
B_CAD9
A_CAD21
A_CAD23
A_CREQ
A_CAD22
B_CAD12
B_CAD15
B_CAD14
B_CAD13
A_CAD19
A_CRST
A_CAD20
A_CVS2
V

CCB

B_CC/BE1
B_RSVD
B_CAD16
A_CC/BE2
V

CCA

A_CAD18
A_CAD17
B_CBLOCK
B_CPERR
GND
B_CPAR
V

CC

A_CFRAME
A_CIRDY
A_CTRDY
B_CGNT
B_CDEVSEL
B_CCLK
B_CSTOP
B_CREQ
B_CAD24
B_CINT
B_CCLKRUN
B_CAD28
B_CAD31
A_CAD1
A_CAD6
A_CAD8
A_CAD10
A_CCLK
A_CDEVSEL

PCI1225 GHK/PDV

TERM. NO.

GHK PDV

R19 110

P5 50

R2 49

V5 57

V6 60
U7 64
U8 68

V9 72

W10 76

P10 80
P11 84
U12 88
V13 92
V14 96
P14 100
R18 109
N14 108
P15 107

T1 52
R3 51

P7 56
U6 59

P8 63
R8 67
W9 71

P9 75

R10 79
U11 83

V12 87
W13 91
W14 95
W15 99

V15 101

U15 103

R17 106

W4 53
U5 54
R6 55
W5 58
W6 62
W7 66
W8 70

R9 74
U10 78
V11 82

W12 86

R12 90
P13 94
U14 98
R14 102

W16 104

T19 105

A_CGNT
B_CIRDY
B_CTRDY
B_CAD20
B_CAD22
V

CC

B_CVS1
B_CSTSCHG
B_CAD27
B_RSVD
A_CAD2
A_CAD3
A_CAD7
GND
A_CAD12
A_CSTOP
A_CPERR
A_CBLOCK
B_CC/BE2
B_CFRAME
B_CVS2
B_CAD21
B_CC/BE3
B_CAD26
B_CAUDIO
GND
B_CAD30
A_CAD0
A_CAD4
A_RSVD
A_CAD9
A_CAD13
A_CAD15
A_CAD16
A_CPAR
B_CAD17
B_CAD18
B_CAD19
B_CRST
B_CAD23
B_CAD25
B_CSERR
B_CCD2
B_CAD29
A_CCD1
V

CC

A_CAD5
A_CC/BE0
A_CAD11
A_CAD14
A_CC/BE1
A_RSVD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 2. CardBus PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

A_CAD0
A_CAD1
A_CAD2
A_CAD3
A_CAD4
A_CAD5
A_CAD6
A_CAD7
A_CAD8
A_CAD9
A_CAD10
A_CAD11
A_CAD12
A_CAD13
A_CAD14
A_CAD15
A_CAD16
A_CAD17
A_CAD18
A_CAD19
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A_CAD28
A_CAD29
A_CAD30
A_CAD31
A_CAUDIO
A_CBLOCK
A_CC/BE0
A_CC/BE1
A_CC/BE2
A_CC/BE3
A_CCD1
A_CCD2
A_CCLK
A_CCLKRUN
A_CDEVSEL
A_CFRAME
A_CGNT
A_CINT
A_CIRDY
A_CPAR
A_CPERR
A_CREQ
A_CRST
A_CSERR

TERM. NO.

GHK PDV

U11 83
R11 85
P11 84
U12 88
V12 87
R12 90
P12 89
V13 92
U13 93

W14 95

R13 97
U14 98
P14 100

W15 99

R14 102
V15 101
U15 103

N19 118
M15 119
M18 121

L19 123

L17 125

L15 126
K19 128
K15 131
K14 132

J19 133
H14 141
H15 142
G18 144
G17 145

F19 147

J15 137
P15 107
P13 94

W16 104

N18 117
K17 130

V11 82
H17 140
P18 112
H18 139
P17 111
N17 116
R19 110

J17 135
M14 115
R17 106
N14 108

L14 127

L18 124

J14 136

SIGNAL NAME

A_CSTOP
A_CSTSCHG
A_CTRDY
A_CVS1
A_CVS2
A_RSVD
A_RSVD
A_RSVD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
B_CAD0
B_CAD1
B_CAD2
B_CAD3
B_CAD4
B_CAD5
B_CAD6
B_CAD7
B_CAD8
B_CAD9
B_CAD10
B_CAD11

TERM. NO.

GHK PDV

R18 109
H19 138
P19 114

J18 134

M19 122

G14 146

W13 91

T19 105

H5 15
G1 14
G3 12

H6 11

F1 10
G5 9

F2 8

E1 6
G6 4

F5 3

E3 2

C12 172

A4 208

E6 206

B5 205

F6 204

B8 191

A8 190

E9 189

F9 188

B9 186

A9 185

F10 184
E10 183

F11 179
E13 165
C11 177
B11 176
A12 174
B12 173
E12 171
A13 170

H2 17

J1 19

H1 18

J3 21
J2 20

K1 24

J6 23
K3 26
K5 27
L1 29
L2 30
L6 32

SIGNAL NAME

B_CAD12
B_CAD13
B_CAD14
B_CAD15
B_CAD16
B_CAD17
B_CAD18
B_CAD19
B_CAD20
B_CAD21
B_CAD22
B_CAD23
B_CAD24
B_CAD25
B_CAD26
B_CAD27
B_CAD28
B_CAD29
B_CAD30
B_CAD31
B_CAUDIO
B_CBLOCK
B_CC/BE0
B_CC/BE1
B_CC/BE2
B_CC/BE3
B_CCD1
B_CCD2
B_CCLK
B_CCLKRUN
B_CDEVSEL
B_CFRAME
B_CGNT
B_CINT
B_CIRDY
B_CPAR
B_CPERR
B_CREQ
B_CRST
B_CSERR
B_CSTOP
B_CSTSCHG
B_CTRDY
B_CVS1
B_CVS2
B_RSVD
B_RSVD
B_RSVD
C/BE0
C/BE1
C/BE2
C/BE3

TERM. NO.

GHK PDV

M1 34

L5 33
M3 36
M2 35
M6 37
W4 53

U5 54
R6 55
V5 57
U6 59
V6 60

W6 62

V7 65

W7 66

R8 67

W10 76

V10 77
U10 78
R10 79

W11 81

W9 71

N6 42
K6 28
N1 39
T1 52
P8 63
H3 16
R9 74
P6 48
U9 73
R1 47
R3 51
P3 46
V8 69
P5 50
N3 41
P1 43

R7 61
W5 58
W8 70

N5 45

V9 72

R2 49

U8 68

P7 56

K2 25

N2 40

P10 80

E2 5

A5 203

C8 192

A15 162

SIGNAL NAME

CLOCK
DATA
DEVSEL
FRAME
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNT
IDSEL
IRDY
LATCH
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6/CLKRUN
PAR
PCLK
PERR
PRST
REQ
RI_OUT/PME
SERR
SPKROUT
STOP
SUSPEND
TRDY
V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CCA

V

CCB

V

CCI

V

CCP

V

CCP

PIN NO.

GHK PDV

E19 151
F14 152

C7 197
F8 193
E8 194

C5 207
F12 167
E18 153
B10 181

G2 13

J5 22

K18 129

P2 44
V14 96

P9 75
C13 168
C10 182

A7 195
F17 150
F15 154
E17 155
A16 157
C15 158
E14 159
F13 160
B15 161

C6 202
A10 180

A6 199
A14 166
B13 169
C14 163

B6 200
G15 149

F7 198
D19 156

B7 196

C9 187
A11 175
B14 164

F3 7

E7 201
G19 143

L3 31
N15 113

U7 64

W12 86

M17 120

M5 38
F18 148

D1 1
E11 178

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number

TERMINAL NO.

GHK PDV

D1 1 V
A4 208 AD12 F2 8 AD6 K14 132 A_A1
E6 206 AD13 E7 201 V
C6 202 PAR C7 197 DEVSEL K17 130 A_REG
F7 198 STOP F8 193 FRAME L2 30 B_CE2
E8 194 GND E9 189 AD18 L3 31 V
A8 190 AD17 A9 185 AD21 L6 32 B_OE
B9 186 AD20 B10 181 GND L1 29 B_A10

C10 182 IDSEL C11 177 AD26 L17 125 A_A5

E11 178 V
A12 174 AD28 B13 169 REQ L14 127 A_INPACK
A13 170 AD31 E13 165 AD25 L15 126 A_A4
A14 166 PRST G15 149 SPKROUT M1 34 B_A11
A15 162 C/BE3 F14 152 DATA M2 35 B_IOWR
E14 159 MFUNC4 E19 151 CLOCK M3 36 B_A9
C15 158 MFUNC3 F17 150 LATCH L5 33 B_IORD
A16 157 MFUNC2 F1 10 AD4 M18 121 A_A25

E3 2 AD10 H6 11 AD3 L18 124 A_RESET
C5 207 GND G3 12 AD2 L19 123 A_A6
B5 205 AD14 G5 9 AD5 M19 122 A_VS2
A5 203 C/BE1 G17 145 A_D9 M5 38 V
A6 199 PERR F18 148 V
A7 195 IRDY F19 147 A_D10 N2 40 B_A18
B8 191 AD16 G14 146 A_D2 M6 37 B_A17
C9 187 V

E10 183 AD23 H5 15 AD0 M17 120 V

F11 179 AD24 H3 16 B_CD1 M15 119 A_A7

A11 175 V
E12 171 AD30 H14 141 A_D0 N6 42 B_A19
F12 167 GND G18 144 A_D1 P1 43 B_A14
C14 163 RI_OUT/PME G19 143 V
F13 160 MFUNC5 H15 142 A_D8 N3 41 B_A13
E17 155 MFUNC1 H1 18 B_D11 N15 113 V
D19 156 SUSPEND J1 19 B_D4 N17 116 A_A23

F5 3 AD9 J2 20 B_D12 M14 115 A_A15
G6 4 AD8 H2 17 B_D3 P19 114 A_A22
E2 5 C/BE0 J15 137 A_BVD2(SPKR) P3 46 B_WE
F6 204 AD15 H17 140 A_CD2 R1 47 B_A21
B6 200 SERR H18 139 A_WP(IOIS16) P6 48 B_A16
B7 196 TRDY H19 138 A_BVD1(STSCHG/RI) N5 45 B_A20
C8 192 C/BE2 J5 22 GND R7 61 B_INPACK

F9 188 AD19 J6 23 B_D13 V7 65 B_A2
F10 184 AD22 K1 24 B_D6 V8 69 B_READY(IREQ)
A10 180 PCLK J3 21 B_D5 U9 73 B_WP(IOIS16)

B11 176 AD27 J19 133 A_A0 V10 77 B_D8
C12 172 AD11 J14 136 A_WAIT W11 81 B_D10
C13 168 GNT J17 135 A_READY(IREQ) R11 85 A_D4
B14 164 V
B15 161 MFUNC6 K3 26 B_D7 U13 93 A_D15
E18 153 GND K5 27 B_D15 R13 97 A_CE2
F15 154 MFUNC0 K6 28 B_CE1 P18 112 A_A16

SIGNAL NAME

CCP

CCP

CC

CC

CC

TERMINAL NO.

GHK PDV

F3 7 V

B12 173 AD29 K19 128 A_A3

G1 14 AD1 N18 117 A_A12

G2 13 GND N19 118 A_A24

J18 134 A_VS1 P12 89 A_D13

SIGNAL NAME

CC

CC

CCI

CC

TERMINAL NO.

GHK PDV

K18 129 GND

K15 131 A_A2

CC

CCB

N1 39 B_A8

CCA

P2 44 GND

CC

SIGNAL NAME

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

PCI1225 GHK/PDV

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number (Continued)

TERMINAL NO.

GHK PDV

E1 6

R19 110

P5
R2
V5
V6
U7
U8
V9

W10

P10
P11
U12
V13
V14
P14
R18 109
N14 108
P15 107

50 B_A15
49 B_A22
57 B_A6
60 B_A4
64 V
68 B_VS1
72 B_BVD1(STSCHG/RI)
76 B_D0
80 B_D2
84 A_D11
88 A_D5
92 A_D7
96 GND

100 A_A11

A_A0
A_A1
A_A2
A_A3
A_A4
A_A5
A_A6
A_A7
A_A8
A_A9
A_A10
A_A11
A_A12
A_A13
A_A14
A_A15
A_A16
A_A17
A_A18
A_A19

SIGNAL NAME

AD7
A_WE

CC

A_A20
A_A14
A_A19

TERMINAL

NO.

GHK PDV

K2 25

T1
R3
P7
U6
P8
R8

W9

P9
R10
U11
V12

W13
W14
W15

V15
U15
R17 106

W4

52 B_A12
51 B_A23
56 B_VS2
59 B_A5
63 B_REG
67 B_A0
71 B_BVD2(SPKR)
75 GND
79 B_D9
83 A_D3
87 A_D12
91 A_D14
95 A_A10

99 A_IORD
101 A_IOWR
103 A_A17

53 B_A24

SIGNAL NAME

B_D14

A_A13

TERMINAL

NO.

GHK PDV

P17 111

U5

R6
W5
W6
W7
W8

R9

U10

V11

W12

R12
P13
U14
R14

W16

T19 105

54 B_A7
55 B_A25
58 B_RESET
62 B_A3
66 B_A1
70 B_WAIT
74 B_CD2
78 B_D1
82 A_CD1
86 V
90 A_D6
94 A_CE1

98 A_OE
102 A_A9
104 A_A8

Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically

TERMINAL NO.

GHK PDV

J19 133
K14 132
K15 131
K19 128
L15 126
L17 125

L19 123
M15 119
W16

R14

W14

P14
N18 117
R17 106
N14 108

M14 115

P18 112
U15
T19 105
P15 107

104 A_CD1
102 A_CD2

95 A_CE1

100 A_CE2

103 A_D5

A_A20
A_A21
A_A22
A_A23
A_A24
A_A25
A_BVD1(STSCHG/RI)
A_BVD2(SPKR)

A_D0
A_D1
A_D2
A_D3
A_D4

A_D6
A_D7

TERMINAL NO.

GHK PDV

R18 109
P17 111
P19 114
N17 116
N19 118

M18 121

H19 138

J15 137
V11
H17 140
P13
R13
H14 141
G18 144
G14 146
U11
R11
U12
R12
V13

82 A_INPACK

94 A_IOWR
97 A_OE

83 A_VS1
85 A_VS2
88 A_WAIT
90 A_WE
92 A_WP(IOIS16)

A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15

A_IORD

A_READY(IREQ)
A_REG
A_RESET

SIGNAL NAME

A_A21

CC

A_A18

TERMINAL NO.

GHK PDV

H15 142
G17 145
F19 147
P11
V12
P12

W13

U13
L14 127

W15

V15
U14

J17 135
K17 130
L18 124

J18 134

M19 122

J14 136
R19 110
H18 139

84
87
89
91
93

99

101

98

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1225 GHK/PDV

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
B_A0
B_A1
B_A2
B_A3
B_A4
B_A5
B_A6
B_A7
B_A8
B_A9
B_A10
B_A11
B_A12
B_A13
B_A14
B_A15
B_A16
B_A17

TERMINAL NO.

GHK PDV

H5 15
G1 14
G3 12
H6 11
F1 10
G5 9
F2 8
E1 6
G6 4
F5 3
E3 2

C12 172

A4 208
E6 206
B5 205
F6 204
B8 191
A8 190
E9 189
F9 188
B9 186

A9 185
F10 184
E10 183
F11 179
E13 165
C11 177
B11 176
A12 174
B12 173
E12 171
A13 170

R8

W7

V7

W6

V6

U6

V5

U5

N1

M3

L1

M1

T1

N3

P1

P5

P6

M6

67 B_IOWR
66 B_OE
65 B_READY(IREQ)
62 B_REG
60 B_RESET
59 B_VS1
57 B_VS2
54 B_WAIT
39 B_WE
36 B_WP(IOIS16)
29 C/BE0
34 C/BE1
52 C/BE2
41 C/BE3
43 CLOCK
50 DATA
48 DEVSEL
37 FRAME

B_A18
B_A19
B_A20
B_A21
B_A22
B_A23
B_A24
B_A25
B_BVD1(STSCHG/RI)
B_BVD2(SPKR)
B_CD1
B_CD2
B_CE1
B_CE2
B_D0
B_D1
B_D2
B_D3
B_D4
B_D5
B_D6
B_D7
B_D8
B_D9
B_D10
B_D11
B_D12
B_D13
B_D14
B_D15
B_INPACK
B_IORD

TERMINAL NO.

GHK PDV

N2
N6
N5
R1
R2
R3

W4

R6
V9

W9

H3 16
R9
K6
L2

W10

U10
P10

H2 17

J1

J3 21
K1
K3

V10
R10

W11

H1 18

J2

J6
K2
K5
R7
L5

M2

L6
V8
P8

W5

U8
P7

W8

P3
U9
E2 5
A5 203
C8 192

A15 162
E19 151
F14 152

C7 197
F8 193

40 GND
42 GND
45 GND
47 GND
49 GND
51 GND
53 GND
55 GND
72 GND
71 GND

74 GNT
28 IDSEL
30 IRDY
76 LATCH
78 MFUNC0
80 MFUNC1

19 MFUNC3

24 MFUNC5
26 MFUNC6
77 PAR
79 PCLK
81 PERR

20 REQ
23 RI_OUT/PME
25 SERR
27 SPKROUT
61 STOP
33 SUSPEND
35 TRDY
32 V
69 V
63 V
58 V
68 V
56 V
70 V
46 V
73 V

GND

MFUNC2

MFUNC4

PRST

CC
CC
CC
CC
CC
CC
CC
CC
CC

V

CC

V

CCA

V

CCB

V

CCI

V

CCP

V

CCP

TERMINAL NO.

GHK PDV

E8 194

C5 207
F12 167
E18 153
B10 181

G2 13

J5
K18 129

P2
V14

P9
C13 168
C10 182

A7 195
F17 150
F15 154
E17 155
A16 157
C15 158
E14 159
F13 160
B15 161

C6 202
A10 180

A6 199
A14 166
B13 169
C14 163

B6 200
G15 149

F7 198
D19 156

B7 196
A11 175

C9 187
B14 164

F3 7

E7 201
G19 143

L3
N15 113

U7

W12

M17 120

M5
F18 148

D1 1
E11 178

22

44
96
75

31

64
86

38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

PCI1225 GHK/PDV

FUNCTION

FUNCTION

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.

power supply

TERMINAL

NAME PDV NUMBER GHK NUMBER

GND

V

CC

V

CCA

V

CCB

V

CCI

V

CCP

13, 22, 44, 75, 96, 129, 153,

167, 181, 194, 207

7, 31, 64, 86, 113, 143, 164,

175, 187, 201

120 M17

38 M5

148 F18

1, 178 D1, E11 Rail voltage for PCI signaling (5 V or 3.3 V)

G2, J5, P2, P9, V14, K18, E18,

F12, B10, E8, C5

F3, L3, U7, W12, N15, G19,

B14, A11, C9, E7

Device ground terminals

Power supply terminal for core logic (3.3 V)
Rail voltage for PC Card A interface. Indicates Card A

signaling environment (5 V or 3.3 V)
Rail voltage for PC Card B interface. Indicates Card B

signaling environment (5 V or 3.3 V)
Rail voltage for interrupt subsystem interface and

miscellaneous I/O (5 V or 3.3 V)

FUNCTION

PC Card power switch

TERMINAL

NAME

CLOCK 151 E19 I/O

DATA 152 F14 O

LATCH 150 F17 O

NUMBER

PDV GHK

TYPE

PCI system

TERMINAL

NAME

PCLK 180 A10 I

PRST

NUMBER

PDV GHK

166 A14 I

TYPE

I/O

Three-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK.
CLOCK defaults to an input, but can be changed to a PCI1225 output by using the P2CCLK bit in the
system control register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz.

If a system design defines this terminal as an output, then this terminal requires an external pull down
resistor. The frequency of the PCI1225 output CLOCK is derived from dividing the PCI CLK by 36.

Three-line power switch data. DATA is used to serially communicate socket power control information
to the power switch.

Three-line power switch latch. LATCH is asserted by the PCI1225 to indicate to the PC Card power
switch that the data on the DATA line is valid. When a pulldown resistor is implemented on this
terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface.

I/O

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at
the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1225 to place all output buffers
in a high-impedance state and reset all internal registers. When PRST
completely nonfunctional. After PRST

When SUSPEND
registers. All outputs are placed in a high-impedance state, but the contents of the registers are
preserved.

and PRST are asserted, the device is protected from PRST clearing the internal

FUNCTION

FUNCTION

is asserted, the device is

is deasserted, the PCI1225 is in its default state.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI address and data

NAME

TYPE

TERMINAL

NUMBER

PDV GHK

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3
C/BE2
C/BE1
C/BE0

PAR 202 C6 I/O

170
171
173
174
176
177
165
179
183
184
185
186
188
189
190
191
204
205
206
208
172

2
3
4
6
8
9

10

11
12
14
15

162
192
203

5

A13
E12
B12
A12
B11
C11
E13
F11
E10
F10

A9
B9
F9
E9
A8
B8
F6
B5
E6
A4

C12

E3
F5

G6

E1
F2

G5

F1
H6
G3
G1
H5

A15

C8

A5

E2

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other

I/O

destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary bus PCI cycle, C/BE3
phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. C/BE0
C/BE2

applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PCI bus parity. In all PCI bus read and write cycles, the PCI1225 calculates even parity across the
AD31–AD0 and C/BE3
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the
initiator parity indicator . A compare error results in the assertion of a parity error (PERR

–C/BE0 buses. As an initiator during PCI cycles, the PCI1225 outputs this parity

FUNCTION

–C/BE0 define the bus command. During the data

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8),

).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

PCI1225 GHK/PDV

NAME

TYPE

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

PCI interface control

TERMINAL

NUMBER

PDV GHK

DEVSEL

FRAME

GNT

IDSEL 182 C10 I

IRDY

PERR
REQ

SERR

STOP

TRDY

197 C7 I/O

193 F8 I/O

168 C13 I

195 A7 I/O

199 A6 I/O
169 B13 O PCI bus request. REQ is asserted by the PCI1225 to request access to the PCI bus as an initiator.

200 B6 O

198 F7 I/O

196 B7 I/O

I/O

Terminal Functions (Continued)

FUNCTION

PCI device select. The PCI1225 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the bus, the PCI1225 monitors DEVSEL
before timeout occurs, the PCI1225 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that
a bus transaction is beginning, and data transfers continue while this signal is asserted. When

is deasserted, the PCI bus transaction is in the final data phase.

FRAME
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1225 access to the PCI bus after

the current data transaction has completed. GNT
depending on the PCI bus parking algorithm.

Initialization device select. IDSEL selects the PCI1225 during configuration space accesses. IDSEL
can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY
are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not
match PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1225 when enabled through the
command register indicating a system error has occurred. The PCI1225 need not be the target of the
PCI cycle to assert this signal. When SERR
indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI
bus transaction. STOP
that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY
are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

is enabled through bit 6 of the command register.

is enabled in the control register, this signal also pulses,

is used for target disconnects and is commonly asserted by target devices

until a target responds. If no target responds

may or may not follow a PCI bus request,

and TRDY

and TRDY

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

NAME

TYPE

multifunction and miscellaneous terminals

TERMINAL

NUMBER

PDV GHK

MFUNC0 154 F15 I/O

MFUNC1 155 E17 I/O

MFUNC2 157 A16 I/O

MFUNC3 158 C15 I/O

I/O

Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0,
GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE
parallel IRQ. See the
details.

Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1,
GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE
parallel IRQ. See the
details.

Serial data (SDA). When the serial bus mode is implemented by pulling the LATCH terminal
low, the MFUNC1 terminal provides the SDA signaling. The two-terminal serial interface is
used to load the subsystem identification and other register defaults from an EEPROM after a
PCI reset. See the
other serial bus applications.

Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2,
socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

See the
Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized

interrupt signal IRQSER. See the
configuration details.

Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket
activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

the

SCPS035B – MA Y 1998 – REVISED – MAY 2000

FUNCTION

multifunction routing register

multifunction routing register

serial bus interface implementation

description on page 64 for configuration details.

multifunction routing register

description on page 64 for configuration details.

description on page 64 for configuration

description on page 64 for configuration

PCI1225 GHK/PDV

PC CARD CONTROLLERS

, or a

, or a

description on page 31 for details on

, or a parallel IRQ.

description on page 64 for

, or a parallel IRQ. See

MFUNC4 159 E14 I/O

MFUNC5 160 F13 I/O

MFUNC6 161 B15 I/O

RI_OUT/PME 163 C14 O

SPKROUT

SUSPEND 156 D19 I

149 G15 O

Serial clock (SCL). When the serial bus mode is implemented by pulling the LATCH terminal
low, the MFUNC4 terminal provides the SCL signaling. The two-terminal serial interface is
used to load the subsystem identification and other register defaults from an EEPROM after a
PCI reset. See the
other serial bus applications.

Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant GPI4, GPO4,
socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

See the
Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See

multifunction routing register

the
Ring indicate out and power management event output. Terminal provides an output for

ring-indicate or PME
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO

through the PCI1225 from the PC Card interface. SPKROUT is driven as the exclusive-OR
combination of card SPKR

Suspend. SUSPEND is used to protect the internal registers from clearing when the PRST
signal is asserted. See

serial bus interface implementation

description on page 64 for configuration details.

description on page 64 for configuration details.

signals.

//CAUDIO inputs.

suspend mode

description on page 42 for details.

description on page 31 for details on

, or a parallel IRQ.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

PCI1225 GHK/PDV

I/O

NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

16-bit PC Card address and data (slots A and B)

TERMINAL

NUMBER
†

NAME

A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 121 and M18 is A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R6 is B_A25.

SLOT A

PDV

121

118
116
114

111
109
107
105
103

112

115
108
106

117
100

95
102
104

119
123
125
126
128
131
132
133

93
91
89
87

84
147
145
142

92

90

88

85

83
146
144
141

GHK

M18
N19
N17

P19
P17

R18

P15
T19

U15

P18
M14
N14
R17
N18

P14

W14

R14

W16

M15

L19

L17

L15

K19

K15

K14

J19
U13

W13

P12

V12

P11

F19
G17
H15

V13
R12
U12

R11

U11
G14
G18
H14

SLOT B

PDV

55
53
51
49
47
45
42
40
37
48
50
43
41
52
34
29
36
39
54
57
59
60
62
65
66
67

27
25
23
20
18
81
79
77
26
24
21
19
17
80
78
76

GHK

R6

W4

R3
R2
R1
N5
N6
N2
M6

N3

M1

M3
N1
U5

U6

W6

W7

R8

H1

W11

R10
V10

H2
P10
U10

W10

I/O

‡

TYPE

P6
P5
P1

T1

L1

V5

V6

V7

K5
K2
J6
J2

K3
K1
J3
J1

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

FUNCTION

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC CARD CONTROLLERS

I/O

NAME

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B)

TERMINAL

NUMBER
†

NAME

BVD1
(STSCHG

BVD2
(SPKR

)

CD1
CD2

CE1
CE2

INPACK 127 L14 61 R7 I

IORD

IOWR

OE 98 U14 32 L6 O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 is A_INPACK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 is B_INPACK

SLOT A

PDV GHK PDV GHK

138 H19 72 V9 I

/RI)

137 J15 71 W9 I

82

V11

140

H171674H3R9

9497P13

R132830

99 W15 33 L5 O

101 V15 35 M2 O

SLOT B

‡

K6
L2

I/O

TYPE

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that
include batteries. BVD1 is used with BVD2 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the
battery is good. When BVD2 is low and BVD1 is high, the battery is weak and
should be replaced. When BVD1 is low, the battery is no longer serviceable and
the data in the memory PC Card is lost. See

configuration
register

bits for this signal.
Status change. STSCHG

write protect, or battery voltage detect condition of a 16-bit I/O PC Card.
Ring indicate. RI

Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that
include batteries. BVD2 is used with BVD1 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and should be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See

register

91

and the

signal.
Speaker. SPKR

socket have been configured for the 16-bit I/O interface. The audio signals from
cards A and B are combined by the PCI1225 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA
operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to
indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected
to ground on the PC Card. When a PC Card is inserted into a socket, CD1

I

are pulled low. For signal status, see
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1

O

odd-numbered address bytes.
Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an

I/O read cycle at the current address.
DMA request. INPACK

operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC
Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1225 to enable 16-bit I/O PC Card data output
during host I/O read cycles.

DMA write. IORD
16-bit PC Card that supports DMA. The PCI1225 asserts IORD
transfers from the PC Card to host memory.

I/O write. IOWR is driven low by the PCI1225 to strobe write data into 16-bit I/O PC
Cards during host I/O write cycles.

DMA read. IOWR
16-bit PC Card that supports DMA. The PCI1225 asserts IOWR
from host memory to the PC Card.

Output enable. OE is driven low by the PCI1225 to enable 16-bit memory PC Card
data output during host memory read cycles.

DMA terminal count. OE
a 16-bit PC Card that supports DMA. The PCI1225 asserts OE
a DMA write operation.

register

on page 91 and the

on page 92 for enable bits. See

on page 92 for enable bits. See

is used to alert the system to a change in the READY,

is used by 16-bit modem cards to indicate a ring detection.

ExCA interface status register

is an optional binary audio signal available only when the card and

enables even-numbered address bytes, and CE2 enables

can be used as the DMA request signal during DMA

is used as the DMA write strobe during DMA operations from a

is used as the DMA write strobe during DMA operations from a

is used as terminal count (TC) during DMA operations to

FUNCTION

ExCA card status-change interrupt

ExCA interface status register

ExCA card status-change interrupt configuration

ExCA card status-change register

on page 88 for the status bits for this

interface status register

PCI1225 GHK/PDV

ExCA card status-change

on page 88 for the status

on page

and CD2

on page 88.

during DMA

during transfers

to indicate TC for

.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

17

PCI1225 GHK/PDV

I/O

NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B) (continued)

TERMINAL

NUMBER
†

NAME

READY
(IREQ

)

REG

RESET 124 L18 58 W5 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
VS1

VS2
WAIT

WE 110 R19 46 P3 O

WP
(IOIS16

)

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19 is A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3 is B_WE

SLOT A

PDV GHK PDV GHK

135 J17 69 V8 I

130 K17 63 P8 O

134

J18

122

M196856

136 J14 70 W8 I

139 H18 73 U9 I

SLOT B

U8
P7

I/O

‡

TYPE

Ready. The ready function is provided by READY when the 16-bit PC Card and the
host socket are configured for the memory-only interface. READY is driven low by
the 16-bit memory PC Cards to indicate that the memory card circuits are busy
processing a previous write command. READY is driven high when the 16-bit
memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ
that a device on the 16-bit I/O PC Card requires service by the host software. IREQ
is high (deasserted) when no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses.
When REG
to the I/O space (IORD
section of card memory and is generally used to record card capacity and other
configuration and attribute information.

DMA acknowledge. REG
operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts REG
indicate a DMA operation. REG
or DMA write (IORD

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with

I/O

each other, determine the operating voltage of the 16-bit PC Card.
Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e.,

extend) the memory or I/O cycle in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards.

WE is also used for memory PC Cards that employ programmable memory
technologies.

DMA terminal count. WE
that supports DMA. The PCI1225 asserts WE to indicate TC for a DMA read
operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the
write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used
for the 16-bit port (IOIS16) function.

I/O is 16 bits. IOIS16
PC Card when the address on the bus corresponds to an address to which the 16-bit
PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations
to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate
a request for a DMA operation.

is asserted, access is limited to attribute memory (OE or WE active) and

is asserted by a 16-bit I/O PC Card to indicate to the host

or IOWR active). Attribute memory is a separately accessed

is used as a DMA acknowledge (DACK) during DMA

) strobes to transfer data.

is used as TC during DMA operations to a 16-bit PC Card

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit

FUNCTION

is used in conjunction with the DMA read (IOWR)

.

to

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC CARD CONTROLLERS

I/O

NAME

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

CardBus PC Card interface system (slots A and B)

TERMINAL

NUMBER
†

NAME

CCLK 112 P18 48 P6 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 is A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 is B_CCLK.

SLOT A

PDV GHK PDV GHK

139 H18 73 U9 O

124 L18 58 W5 I/O

SLOT B

I/O

‡

TYPE

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on
the CardBus interface. All signals except CRST
CAUDIO, CCD2
and all timing parameters are defined with the rising edge of this signal. CCLK
operates at the PCI bus clock frequency, but it can be stopped in the low state or
slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request
an increase in the CCLK frequency, and by the PCI1225 to indicate that the CCLK
frequency is going to be decreased.

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers,
sequencers, and signals to a known state. When CRST
Card signals must be 3-stated, and the PCI1225 drives these signals to a valid logic
level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous
to CCLK.

, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK,

FUNCTION

PCI1225 GHK/PDV

, CCLKRUN, CINT, CSTSCHG,

is asserted, all CardBus PC

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

PCI1225 GHK/PDV

I/O

NAME

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

CardBus PC Card address and data (slots A and B)

TERMINAL

PIN NUMBER

†

NAME

CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0

CC/BE3
CC/BE2
CC/BE1
CC/BE0

CPAR 106 R17 41 N3 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 is A_CPAR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 is B_CPAR.

SLOT A

PDV GHK PDV GHK

147
145
144
142
141
133
132
131
128
126
125
123
121

103
101
102

100

130

104

119
118

99

98
97
95
93
92
89
90
87
88
84
85
83

117

94

F19
G17
G18
H15
H14

J19

K14

K15

K19

L15

L17

L19
M18
M15
N19
U15

V15
R14
W15

P14
U14
R13
W14
U13

V13

P12
R12

V12
U12

P11

R11

U11

K17
N18
W16

P13

SLOT B

81
79
78
77
76
67
66
65
62
60
59
57
55
54
53
37
35
36
33
34
32
30
29
27
26
23
24
20
21
18
19
17

63
52
39
28

W11

R10
U10
V10

W10

W7

W6

W4
M6
M2
M3

M1

R8

V7

V6
U6
V5
R6
U5

L5

L6
L2

L1
K5
K3

J6
K1

J2

J3
H1

J1
H2

P8

T1
N1
K6

I/O

‡

TYPE

PC Card address and data. These signals make up the multiplexed CardBus address
and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of a CardBus cycle,

–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is

CC/BE3
used as byte enables. The byte enables determine which byte paths of the full 32-bit data

I/O

bus carry meaningful data. CC/BE0
to byte 1 (CAD15–CAD8), CC/BE2
applies to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1225 calculates even parity
across the CAD and CC/BE
outputs CPAR with a one-CCLK delay . As a target during CardBus cycles, the calculated
parity is compared to the initiator parity indicator; a compare error results in a parity error
assertion.

buses. As an initiator during CardBus cycles, the PCI1225

FUNCTION

applies to byte 0 (CAD7–CAD0), CC/BE1 applies

applies to byte 2 (CAD23–CAD8), and CC/BE3

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC CARD CONTROLLERS

I/O

NAME

CCD1

82

V11

H3

CVS1

134

J18

U8

SCPS035B – MA Y 1998 – REVISED – MAY 2000

Terminal Functions (Continued)

CardBus PC Card interface control (slots A and B)

TERMINAL

PIN NUMBER

†

NAME

CAUDIO 137 J15 71 W9 I

CBLOCK

CCD1
CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 134 J18 68 U8
CVS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 137 and J15 is A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 71 and W9 is B_CAUDIO.

SLOT A

PDV GHK PDV GHK

107 P15 42 N6 I/O

82 V11 16 H3

140

H171674

111 P17 47 R1 I/O

116 N17 51 R3 I/O

110 R19 46 P3 I

135 J17 69 V8 I

115 M14 50 P5 I/O

108 N14 43 P1 I/O

127 L14 61 R7 I

136 J14 70 W8 I

109 R18 45 N5 I/O

138 H19 72 V9 I

114 P19 49 R2 I/O

122

M196856

SLOT B

‡

R9

P7

I/O

TYPE

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system
speaker. The PCI1225 supports the binary audio mode and outputs a binary signal
from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

I

with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the
operating voltage and card type.

CardBus device select. The PCI1225 asserts CDEVSEL to claim a CardBus cycle as
the target device. As a CardBus initiator on the bus, the PCI1225 monitors CDEVSEL
until a target responds. If no target responds before timeout occurs, the PCI1225
terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle.
CFRAME
transfers continue while this signal is asserted. When CFRAME
CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI1225 to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt
servicing from the host.

CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to
complete the current data phase of the transaction. A data phase is completed on a
rising edge of CCLK when both CIRDY
CTRDY are both sampled asserted, wait states are inserted.

CardBus parity error. CPERR is used to report parity errors during CardBus
transactions, except during special cycles. It is driven low by a target two clocks
following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires
use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors
that could lead to catastrophic results. CSERR
CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The
PCI1225 can report CSERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop
the current CardBus transaction. CSTOP
commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card
status, and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the ability of the CardBus target to complete
the current data phase of the transaction. A data phase is completed on a rising edge
of CCLK, when both CIRDY
inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

I/O

in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards
to determine the operating voltage and card type.

is asserted to indicate that a bus transaction is beginning, and data

FUNCTION

and CTRDY are asserted. Until CIRDY and

is driven by the card synchronous to

to the system by assertion of SERR on the PCI interface.

is used for target disconnects, and is

and CTRDY are asserted; until this time, wait states are

PCI1225 GHK/PDV

is deasserted, the

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

power supply sequencing

The PCI1225 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp power
supplies. The core power supply is always 3.3 V . The clamp power supplies can be either 3.3 V or 5 V , depending
on the interface. The following power-up and power-down sequences are recommended.

The power-up sequence is:

1. Apply 3.3-V power to the core.

2. Assert PRST

to the device to disable the outputs during power up. Output drivers must be powered up in

the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.

3. Apply the clamp power.
The power-down sequence is:

1. Use PRST

to switch outputs to a high-impedance state.

2. Remove the clamp power.

3. Remove the 3.3-V power from the core.

I/O characteristics

Figure 1 shows a 3-state bidirectional buffer. The
provides the electrical characteristics of the inputs and outputs.

NOTE:

The PCI1225 meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus
Specification Rev. 2.2.

Tied for Open Drain

OE

recommended operating conditions

V

CCP

Pad

table, on page 120,

Figure 1. 3-State Bidirectional Buffer

NOTE:

Unused pins (input or I/O) must be held high or low to prevent them from floating.

clamping rail voltages

The clamping rail voltages are set to match whatever external environment the PCI1225 will be working with:

3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a power rail that protects the core from
external signals. The core power supply is always 3.3 V and is independent of the clamping rail voltages. For
example, PCI signaling can be either 3.3 V or 5 V, and the PCI1225 must reliably accommodate both voltage
levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping rail
voltage applied. If a system designer desires a 5-V PCI bus, V

The PCI1225 requires four separate clamping rails because it supports a wide range of features. The four rails
are listed and defined in the

22

recommended operating conditions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

can be connected to a 5-V power supply.

CCP

, on page 120.

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

peripheral component interconnect (PCI) interface

The PCI1225 is fully compliant with the PCI Local Bus Specification Rev. 2.2. The PCI1225 provides all required
signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by
connecting the V
PCI1225 provides the optional interrupt signals INTA

PCI bus lock (LOCK)

The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the
PCI1225 as an additional compatibility feature. The PCI LOCK
via the multifunction routing register; see the
Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from
the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is
asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a
transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own
protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK.
Note that the CardBus signal for this protocol is CBLOCK

An agent may need to do an exclusive operation because a critical access to memory might be broken into
several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock
is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without
interfering with nonexclusive real-time data transfer, such as video.

terminals to the desired voltage level. In addition to the mandatory PCI signals, the

CCP

and INTB.

signal can be routed to the MFUNC4 terminal

multifunction routing register

description on page 64 for details.

to avoid confusion with the bus clock.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK
scenario, the arbiter will not grant the bus to any other agent (other than the LOCK

master) while LOCK is

protocol. In this

asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that
supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified
line when a locked operation is in progress.

The PCI1225 supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can
solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur
if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed
read. This target characteristic is prohibited by the 2.2 PCI specification, and the issue is resolved by the PCI
master using LOCK

.

loading subsystem identification

The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space
located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile
dock) identification purposes and is required by some operating systems. Implementation of this unique
identifier register is a PC 95 requirement.

The PCI1225 offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by setting the SUBSYSRW bit in the system
control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value
into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID
register and subsystem ID register is limited to read-only access. This approach saves the added cost of
implementing the serial electrically erasable programmable ROM (EEPROM).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

loading subsystem identification (continued)

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID
register must be loaded with a unique identifier via a serial EEPROM. The PCI1225 loads the data from the serial
EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire
PCI1225 core, including the serial bus state machine (see
SUSPEND).

The PCI1225 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM.
See

serial bus interface

on page 31 for details on the two-wire serial bus controller and applications.

PC Card applications

This section describes the PC Card interfaces of the PCI1225:

 Card insertion/removal and recognition

2

 P

C power-switch interface

 Zoom video support
 Speaker and audio applications
 LED socket activity indicators
 16-bit PC Card DMA support
 CardBus socket registers

suspend mode

, on page 42, for details on using

PC Card insertion/removal and recognition

The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this
interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined.

The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). The
configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface.
The encoding scheme is defined in the 1997 PC Card Standard and in Table 5.

Table 5. PC Card Card-Detect and Voltage-Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE

Ground Ground Open Open 5 V 16-bit PC Card 5 V
Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V
Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V
Ground Ground Open Ground LV 16-bit PC Card 3.3 V
Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V

Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V
Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V
Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V

Ground Ground Ground Open LV 16-bit PC Card Y.Y V
Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V
Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved

Ground Connect to CVS2 Connect to CCD1 Ground Reserved

24

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PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

P2C power-switch interface (TPS2202A/2206)

2

The PCI1225 provides a P
The CLOCK, DATA, and LATCH terminals interface with the TI TPS2202A/2206 dual-slot PC Card power
interface switches to provide power switch support. Figure 2 shows the terminal assignments of the TPS2206,
and Figure 3 illustrates a typical application where the PCI1225 represents the PCMCIA controller.

C (PCMCIA peripheral control) interface for control of the PC Card power switch.

5 V
5 V

DATA

CLOCK

LATCH

RESET

12 V
A VPP
A VCC
A VCC
A VCC

GND

NC

RESET

3.3 V

NC – No internal connection

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

5 V
NC
NC
NC
NC
NC
12 V
BVPP
BVCC
BVCC
BVCC
NC
OC

3.3 V

3.3 V

Figure 2. TPS2206 Terminal Assignments

The CLOCK terminal on the PCI1225 can be an input or an output. The PCI1225 defaults the CLOCK terminal
as an input to control the serial interface and the internal state machine. The P2CCLK bit in the system control
register can be set by the platform BIOS to enable the PCI1225 to generate and drive the CLOCK internally from
the PCI clock. When the system design implements CLOCK as an output from the PCI1225, an external
pulldown is required.

Power Supply

12 V

5 V

3.3 V

Supervisor

PCI1225

(PCMCIA

Controller)

TPS2206

12 V
5 V

3.3 V

RESET
RESET

CLOCK
DATA
LATCH

AVPP

AVCC
AVCC
AVCC

BVPP

BVCC
BVCC
BVCC

V
V
V
V

V
V
V
V

PP1
PP2
CC
CC

PP1
PP2
CC
CC

Figure 3. TPS2206 Typical Application

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC Card

A

PC Card

B

25

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

zoom video support

The PCI1225 allows for the implementation of zoom video for PC Cards. Zoom video is supported by setting
the ZVENABLE bit in the card control register on a per-socket-function basis. Setting this bit puts 16-bit PC Card
address lines A25–A4 of the PC Card interface in the high-impedance state. These lines can then be used to
transfer video and audio data directly to the appropriate controller. Card address lines A3–A0 can still be used
to access PC Card CIS registers for PC Card configuration. Figure 4 illustrates a PCI1225 ZV implementation.

Audio

Codec

PCM
Audio
Input

Speakers

PC Card

19

PC Card

Interface

Video

Audio

4

CRT

Motherboard

PCI Bus

VGA

Controller

Zoom Video

Port

19 4

PCI1225

Figure 4. Zoom Video Implementation Using PCI1225

Not shown in Figure 4 is the multiplexing scheme used to route either socket 0 or socket 1 ZV source to the
graphics controller. The PCI1225 provides ZVSTAT, ZVSEL0, and ZVSEL1 signals on the multifunction
terminals to switch external bus drivers. Figure 5 shows an implementation for switching between three ZV
streams using external logic.

26

2

PCI1225

ZVSTAT
ZVSEL0
ZVSEL1

0 1

Figure 5. Zoom Video Switching Application

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PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

zoom video support (continued)

Figure 5 illustrates an implementation using standard three-state bus drivers with active-low output enables.
ZVSEL0
output indicating that socket 1 ZV is enabled. When both sockets have ZV mode enabled, the PCI1225 defaults
to indicating socket 0 enabled through ZVSEL0
software to select the socket ZV source priority. Table 6 illustrates the functionality of the ZV output signals.

Also shown in Figure 5 is a third ZV source that may be provided from a source such as a high-speed serial bus
like IEEE 1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an
active-high output indicating that one of the PCI1225 sockets is enabled for ZV mode. The implementation
shown in Figure 5 can be used if PC Card ZV is prioritized over other sources.

is an active-low output indicating that the socket 0 ZV mode is enabled, and ZVSEL1 is an active-low

; however, the POR TSEL bit in the card control register allows

Table 6. PC Card Card-Detect and Voltage-Sense Connections

INPUTS OUTPUTS

PORTSEL SOCKET 0 ENABLE SOCKET 1 ENABLE ZVSEL0 ZVSEL1 ZVSTAT

X 0 0 1 1 0
0 1 X 0 1 1
0 0 1 1 0 1
1 X 1 1 0 1
1 1 0 0 1 1

SPKROUT and CAUDPWM usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured
for I/O mode, the BVD2 terminal becomes SPKR

. This terminal is also used in CardBus binary audio
applications, and is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1225. The
CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the
two PC Card sockets are XORed in the PCI1225 to produce SPKROUT. This output is enabled by the
SPKROUTEN bit in the card control register.

Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio
chips may not support both modes on one terminal and may have a separate terminal for binary and PWM. The
PCI1225 implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal.
The AUD2MUX bit located in the card control register is programmed on a per-socket-function basis to route
a CardBus CAUDIO PWM terminal to CAUDPWM. If both CardBus functions enable CAUDIO PWM routing to
CAUDPWM, then socket 0 audio takes precedence. See the

multifunction routing register

description on page

64 for details on configuring the MFUNC terminals.
Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM.

System

Core Logic

BINARY_SPKR

Speaker

Subsystem

PWM_SPKR

PCI1225

SPKROUT

CAUDPWM

Figure 6. Sample Application of SPKROUT and CAUDPWM

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27

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

LED socket activity indicators

The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LEDA1 and LEDA2
signals can be routed to the multifunction terminals. When configured for LED outputs, these terminals output
an active high signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates
socket 1 (card B) activity. The LED_SKT output indicates socket activity to either socket 0 or socket 1. See the

multifunction routing register

The LED signal is active high and is driven for 64-ms durations. When the LED is not being driven high, it is driven
to a low state. Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling, and
it is left for the board designer to implement the circuit that best fits the application.

The LED activity signals are valid when a card is inserted, powered, and not in reset. For a 16-bit PC Card, the
LED activity signals are pulsed when READY/IREQ is low. For CardBus cards, the LED activity signals are
pulsed if CFRAME, IRDY, or CREQ is active.

description on page 64 for details on configuring the multifunction terminals.

Current Limiting

R ≈ 500 Ω

PCI1225

PCI1225

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

LED

LED

Figure 7. T wo Sample LED Circuits

As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of
the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut-off when the SUSPEND
signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1
power state.

If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), the LED signals remain driven.

16-bit PC Card Distributed DMA support

The PCI1225 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA
(DDMA) slave register set provides the programmability necessary for the slave DDMA engine. The DDMA
register configuration is provided in Table 7.

Two socket function dependent PCI configuration header registers that are critical for DDMA are the socket
DMA register 0 and the socket DMA register 1. Distributed DMA is enabled through socket DMA register 0 and
the contents of this register configure the 16-bit PC Card terminal (SPKR

, IOIS16, or INPACK) which is used
for the DMA request signal, DREQ. The base address of the DDMA slave registers and the transfer size (bytes
or words) are programmed through the socket DMA register 1. See the programming model and register
descriptions for details.

28

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PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

16-bit PC Card distributed DMA support (continued)

Table 7. Distributed DMA Registers

TYPE REGISTER NAME

R
W
R
W
R N/A
W Mode
R Multichannel
W Mask

Reserved Page

Reserved Reserved

Reserved

Reserved

Request Command

Master clear

Current address 00h

Base address
Current count 04h

Base count

N/A Status 08h

N/A

Reserved

The DDMA registers contain control and status information consistent with the 8237 DMA controller; however,
the register locations are reordered and expanded in some cases. While the DDMA register definitions are
identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA
controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1225 implements these
obsolete register bits as read-only , nonfunctional bits. The reserved registers shown in T able 7 are implemented
as read-only and return zeros when read. Write transactions to reserved registers have no effect.

BASE ADDRESS

OFFSET

DMA

0Ch

The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be
completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ

signal
assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed
above, this is done through socket DMA register 0 and socket DMA register 1. The DMA register set is then
programmed similarly to an 8237 controller, and the PCI1225 awaits a DREQ assertion from the PC Card
requesting a DMA transfer.

DMA writes transfer data from the PC Card to PCI memory addresses. The PCI1225 accepts data 8 or 16 bits
at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its
REQ signal. Once the PCI bus is granted in an idle state, the PCI1225 initiates a PCI memory write command
to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle,
the PCI1225 accepts the next byte(s) from the PC Card until the transfer count expires.

DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ
the PCI1225 asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1225 initiates
a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on
the programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After
terminating the PC Card cycle, the PCI1225 requests access to the PCI bus again until the transfer count has
expired.

The PCI1225 target interface acts normally during this procedure and accepts I/O reads and writes to the DDMA
registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1225 asserts TC
and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the
PCI1225 supports demand mode transfers. The PCI1225 asserts DACK during the transfer unless DREQ

is
deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to
WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all
transfers, and the DREQ terminal is routed to one of three options which is programmed through socket DMA
register 0.

,

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29

PCI1225 GHK/PDV
PC CARD CONTROLLERS

SCPS035B – MA Y 1998 – REVISED – MAY 2000

16-bit PC Card PC/PCI DMA

Some chip sets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA
protocol, the PCI1225 acts as a PCI target device to certain DMA related I/O addresses. The PCI1225 PCREQ
and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The
PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. See the

multifunction routing register

Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1225) requests a DMA transfer on a
particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus,
and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle
and memory cycles are then presented on the PCI bus, which performs the DMA transfers similarly to legacy
DMA master devices.

PC/PCI DMA is enabled for each 16-bit PC Card slot by setting bit 19 in the respective system control register .
On power up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 of the system control register is a global
enable for PC/PCI DMA, and is set at power-up and never cleared if the PC/PCI DMA mechanism is
implemented. The desired DMA channel for each 16-bit PC Card slot must be configured through bits 18–16
in the system control register. The channels are configured as indicated in Table 8.

description on page 64 for details on configuring the multifunction terminals.

Table 8. PC/PCI Channel Assignments

SYSTEM CONTROL REGISTER

BIT 18 BIT 17 BIT16

0 0 0 Channel 0 8-bit DMA transfers
0 0 1 Channel 1 8-bit DMA transfers
0 1 0 Channel 2 8-bit DMA transfers
0 1 1 Channel 3 8-bit DMA transfers
1 0 0 Channel 4 Not used
1 0 1 Channel 5 16-bit DMA transfers
1 1 0 Channel 6 16-bit DMA transfers
1 1 1 Channel 7 16-bit DMA transfers

DMA CHANNEL CHANNEL TRANSFER DATA WIDTH

As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA
register 0. The data transfer width is a function of channel number , and the DDMA slave registers are not used.
When a DREQ

is received from a PC Card and the channel has been granted, the PCI1225 decodes the I/O

addresses listed in Table 9 and performs actions dependent upon the address.

Table 9. I/O Addresses Used for PC/PCI DMA

DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE

00h Normal 0 I/O read/write

04h Normal TC 1 I/O read/write
C0h Verify 0 I/O read
C4h Verify TC 1 I/O read

When the PC/PCI DMA is used as a 16-bit PC Card DMA mechanism, it may not provide the performance levels
of DDMA; however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus
master state machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset.
This DMA scheme is often referred to as centralized DMA for this reason.

CardBus socket registers

The PCI1225 contains all registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge
specification. These registers exist as the CardBus socket registers, and are listed in Table 10.

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