Texas Instruments PCI1221PDV Datasheet

PCI Bus Power Management Interface Specification 1.0 Compliant

ACPI 1.0 Compliant

Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset

Packaged in a 208-Pin Low-Profile QFP (PDV) or GHK High Density Ball Grid Array (BGA)

PCI Local Bus Specification Revision 2.2 Compliant

1997 PC Card Standard Compliant

PC 99 Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards

Supports Two PC Card or CardBus Slots With Hot Insertion and Removal

Uses Serial Interface to TI TPS2202/2206 Dual-Slot PC Card Power Switch

Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and CardBus Bus

Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Name/Terminal Number Sort Tables 6. . . . . . . . . . . . . . . . .

Terminal Functions 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Sequencing 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Voltages 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Component Interconnect (PCI) Interface 23. . . . . . . .

PC Card Applications 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Bus Interface 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 34. . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 39. . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Controller Programming Model 44. . . . . . . . . . . . . . . . . .

PCI Configuration Registers (Functions 0 and 1) 44. . . . . . . . . . .

ExCA Compatibility Registers (Functions 0 and 1) 80. . . . . . . . .

D D

D D D

Table of Contents

CardBus Socket Registers (Functions 0 and 1) 103. . . . . . . . . . . . . .

Absolute Maximum Ratings 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 112. . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 114. . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 115. . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 116. . . . . . . . . . . . . . .

PC Card Cycle Timing 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements (Memory Cycles) 118. . . . . . . . . . . . . . . . . . . . .

Timing Requirements (I/O Cycles) 118. . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics (Miscellaneous 119. . . . . . . . . . . . . . . . . . .

PC Card Parameter Measurement Information 120. . . . . . . . . . . . . . .

Mechanical Data 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

Pipelined Architecture Allows Greater Than 130M-Bps Throughput From CardBus-to-PCI and From PCI-to-CardBus

Supports Up to Five General-Purpose I/Os Serial EEPROM Interface for Loading

Subsystem ID and Subsystem Vendor ID Programmable Output Select for CLKRUN Multifunction PCI Device With Separate

Configuration Space for Each Socket Five PCI Memory Windows and T wo I/O

Windows Available for Each R2 Socket Two I/O Windows and Two Memory

Windows Available to Each CardBus Socket

Exchangeable Card Architecture (ExCA) Compatible Registers Are Mapped in Memory and I/O Space

Intel 82365SL-DF Register Compatible Supports Ring Indicate, SUSPEND, PCI

CLKRUN, and CardBus CCLKRUN LED Activity Pins Supports PCI Bus Lock (LOCK) Advanced Submicron, Low-Power CMOS

T echnology

ADVANCE INFORMATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). Intel is a trademark of Intel Corporation. TI is a trademark of Texas Instruments Incorporated.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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PCI1221 GHK/PDV PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

description

The TI PCI1221 is a high-performance PCI-to-PC Card controller that supports two independent card sockets compliant with the 1997 PC Card Standard. The PCI1221 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2 and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1221 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1221 is compliant with the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The PCI1221 is also compliant with the latest

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1221 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1221 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1221 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1221, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.

PCI Bus Power Management Interface Specification

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

Unused PCI1221 inputs must be pulled up using a 43kW-resistor.

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PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

system block diagram

A simplified block diagram of the PCI1221 is provided below. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface terminals include multifunction terminals: SUSPEND

, RI_OUT/PME (power management control signal), and SPKROUT.

PCI Bus

Activity LED’s

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed

video signals to the VGA controller.

PCI1221

68 68

IRQSER

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

INTA

INTB

Interrupt

Controller

IRQ2–15

VGA

Controller

Audio

Sub-System

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PCI1221 GHK/PDV PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

terminal assignments

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30 AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17 AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

SUSPEND

GND

MFUNC0

DATA

SPKROUT

LATCH

CLOCK

152

151

150

149

VCCI

148

MFUNC1

154

153

156

155

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_CAD31

A_CAD30

A_RSVD

146

145

147

A_CAD28

A_CAD29

A_CAD27

142

141

144

143

PCI1221 Core

A_CCD2

A_CCLKRUN

A_CSTSCHG

138

140

139

A_CAUDIO

137

A_CINT

A_CSERR

A_CVS1

134

136

135

A_CAD25

A_CAD26

A_CAD24

132

131

133

A_CC/BE3

A_CAD23

GND

128

130

129

Card A

A_CAD21

A_CAD22

A_CREQ

126

125

127

A_CRST

124

A_CAD20

A_CAD19

A_CVS2

122

121

123

Card B

CCA

A_CAD18

119

120

A_CC/BE2

A_CAD17

118

117

A_CFRAME

A_CTRDY

A_CIRDY

114

113

116

115

A_CCLKVA_CDEVSEL

112

A_CGNT

111

110

A_CSTOP

A_CBLOCK

A_CPERR

108

107

109

A_RSVD

A_CPAR

105 104

103 102 101 100

51 106

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

A_CC/BE1 A_CAD16 A_CAD14 A_CAD15 A_CAD12 A_CAD13 A_CAD11 A_CAD10 GND A_CAD9 A_CC/BE0 A_CAD8 A_CAD7 A_RSVD A_CAD5 A_CAD6 A_CAD3 A_CAD4

CC A_CAD1 A_CAD2 A_CAD0 A_CCD1 B_CAD31 B_RSVD B_CAD30 B_CAD29 B_CAD28 B_CAD27 GND B_CCD2 B_CCLKRUN B_CSTSCHG B_CAUDIO B_CSERR B_CINT B_CVS1 B_CAD26 B_CAD25 B_CAD24 V

CC B_CC/BE3

B_CAD23 B_CREQ B_CAD22 B_CAD21 B_CRST B_CAD20 B_CVS2 B_CAD19 B_CAD18 B_CAD17

CCP

AD10

AD9

AD8

AD7

C/BE0

AD4

AD6

AD5

AD3

AD1

AD0

AD2

GND

B_CAD0

B_CAD2

B_CCD1

B_CAD1

B_CAD4

B_CAD3

GND

B_CAD6

B_CAD5

B_CAD7

B_RSVD

B_CAD8

B_CAD9

B_CAD10

B_CC/BE0

B_CAD11

B_CAD13

B_CAD14

B_CAD12

B_CAD15

CCB

B_CAD16

B_CC/BE1

B_CPAR

B_RSVD

B_CBLOCK

GND

B_CSTOP

B_CPERR

B_CCLK

B_CGNT

B_CDEVSEL

B_CIRDY

B_CTRDY

B_CFRAME

B_CC/BE2

PCI-to-CardBus Pin Diagram

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terminal assignments (continued)

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30 AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17

AD16

C/BE2

FRAME

GND IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

A_D10

A_D2

146

147

A_D9

A_D8

A_D1

142

144

143

145

PCI1221 Core

A_BVD2(SPKR)

A_CD2

A_D0

A_WP(IOIS16)

A_BVD1(STSCHG/RI)

138

137

140

139

141

A_A1

A_READY(IREQ)

A_WAIT

A_A0

A_VS1

132

134

133

136

135

A_A2

131

A_REG

GND

130

129

Card A

A_A3

128

A_INPACK

127

A_A4

126

A_A5

125

CCI

DATA

152

LATCH

CLOCK

150

151

SPKROUT

148

149

SUSPEND

GND

MFUNC0

MFUNC1

154

153

156

155

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_A6

A_RESET

A_VS2

122

124

123

Card B

CCA

A_A25

120

121

A_A7

119

A_A24

118

A_A23

A_A12

116

117

A_A22

A_A15

114

115

A_A16VA_A21

112

113

111

A_A20

A_WE

110

109

A_A19

A_A14

108

107

A_A18

A_A13

105

104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

51 106

A_A8 A_A17 A_A9 A_IOWR A_A11 A_IORD A_OE A_CE2 GND A_A10 A_CE1 A_D15 A_D7 A_D14 A_D6 A_D13 A_D5 A_D12

CC A_D4 A_D11 A_D3 A_CD1 B_D10 B_D2 B_D9 B_D1 B_D8 B_D0 GND B_CD2 B_WP(IOIS16) B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A0 B_A1 B_A2 V

CC B_REG B_A3 B_INPACK B_A4 B_A5 B_RESET B_A6

B_VS2 B_A25 B_A7 B_A24

CCP

AD9

AD10

AD8

AD7

C/BE0

AD6

AD5

AD4

AD3

AD2

GND

AD1

AD0

B_D3

B_CD1

B_D11

B_D4

B_D5

B_D12

GND

B_D6

B_D13

B_D7

B_D14

B_D15

B_CE1

B_A10

B_CE2

B_OE

B_IORD

B_A11

B_IOWR

B_A9

CCB

B_A17

B_A8

B_A18

B_A13

B_A19

GND

B_A14

B_WE

B_A20

B_A21

B_A16

B_A15

B_A22

B_A23

B_A12

PCI-to-PC Card (16-Bit) Diagram

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PCI1221 GHK/PDV PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

terminal assignments (continued)

GHK PLASTIC BALL GRID ARRAY

BOTTOM VIEW

signal names and terminal assignments

Table 1 and Table 2 show the terminal assignments for the CardBus PC Card; Table 3 and Table 4 show the terminal assignments for the 16-bit PC Card; Table 1 and Table 3 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the associated GHK package terminal number; and Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and it’s associated terminal numbers.

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SIGNAL NAME

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

Table 1. CardBus PC Card Signal Names by GHK/PDV Pin Number

PIN NO.

GHK PDV

D1 1 V A4 208 AD12 F2 8 AD6 K14 132 A_CAD25 P5 50 B_CIRDY E6 206 AD13 E7 201 V C6 202 PAR C7 197 DEVSEL K17 130 A_CC/BE3 V5 57 B_CAD20

F7 198 STOP F8 193 FRAME L2 30 B_CAD10 V6 60 B_CAD22 E8 194 GND E9 189 AD18 L3 31 V A8 190 AD17 A9 185 AD21 L6 32 B_CAD11 U8 68 B_CVS1 B9 186 AD20 B10 181 GND L1 29 B_CAD9 V9 72 B_CSTSCHG

C10 182 IDSEL C11 177 AD26 L17 125 A_CAD21 W10 76 B_CAD27 E11 178 V A12 174 AD28 B13 169 REQ L14 127 A_CREQ P11 84 A_CAD2 A13 170 AD31 E13 165 AD25 L15 126 A_CAD22 U12 88 A_CAD3 A14 166 PRST G15 149 SPKROUT M1 34 B_CAD12 V13 92 A_CAD7 A15 162 C/BE3 F14 152 DATA M2 35 B_CAD15 V14 96 GND E14 159 MFUNC4 E19 151 CLOCK M3 36 B_CAD14 P14 100 A_CAD12 C15 158 MFUNC3 F17 150 LATCH L5 33 B_CAD13 R18 109 A_CSTOP A16 157 MFUNC2 F1 10 AD4 M18 121 A_CAD19 N14 108 A_CPERR

E3 2 AD10 H6 11 AD3 L18 124 A_CRST P15 107 A_CBLOCK C5 207 GND G3 12 AD2 L19 123 A_CAD20 T1 52 B_CC/BE2 B5 205 AD14 G5 9 AD5 M19 122 A_CVS2 R3 51 B_CFRAME A5 203 C/BE1 G17 145 A_CAD30 M5 38 V A6 199 PERR F18 148 V A7 195 IRDY F19 147 A_CAD31 N2 40 B_RSVD P8 63 B_CC/BE3 B8 191 AD16 G14 146 A_RSVD M6 37 B_CAD16 R8 67 B_CAD26 C9 187 V

E10 183 AD23 H5 15 AD0 M17 120 V F11 179 AD24 H3 16 B_CCD1 M15 119 A_CAD18 R10 79 B_CAD30 A11 175 V E12 171 AD30 H14 141 A_CAD27 N6 42 B_CBLOCK V12 87 A_CAD4 F12 167 GND G18 144 A_CAD29 P1 43 B_CPERR W13 91 A_RSVD C14 163 RI_OUT/PME G19 143 V F13 160 MFUNC5 H15 142 A_CAD28 N3 41 B_CPAR W15 99 A_CAD13 E17 155 MFUNC1 H1 18 B_CAD2 N15 113 V D19 156 SUSPEND J1 19 B_CAD1 N17 116 A_CFRAME U15 103 A_CAD16

F5 3 AD9 J2 20 B_CAD4 M14 115 A_CIRDY R17 106 A_CPAR G6 4 AD8 H2 17 B_CAD0 P19 114 A_CTRDY W4 53 B_CAD17 E2 5 C/BE0 J15 137 A_CAUDIO P3 46 B_CGNT U5 54 B_CAD18

F6 204 AD15 H17 140 A_CCD2 R1 47 B_CDEVSEL R6 55 B_CAD19 B6 200 SERR H18 139 A_CCLKRUN P6 48 B_CCLK W5 58 B_CRST B7 196 TRDY H19 138 A_CSTSCHG N5 45 B_CSTOP W6 62 B_CAD23 C8 192 C/BE2 J5 22 GND R7 61 B_CREQ W7 66 B_CAD25

F9 188 AD19 J6 23 B_CAD6 V7 65 B_CAD24 W8 70 B_CSERR

F10 184 AD22 K1 24 B_CAD5 V8 69 B_CINT R9 74 B_CCD2 A10 180 PCLK J3 21 B_CAD3 U9 73 B_CCLKRUN U10 78 B_CAD29 B11 176 AD27 J19 133 A_CAD26 V10 77 B_CAD28 V11 82 A_CCD1 C12 172 AD11 J14 136 A_CSERR W11 81 B_CAD31 W12 86 V C13 168 GNT J17 135 A_CINT R11 85 A_CAD1 R12 90 A_CAD5 B14 164 V B15 161 MFUNC6/CLKRUN K3 26 B_CAD7 U13 93 A_CAD8 U14 98 A_CAD11 E18 153 GND K5 27 B_CAD8 R13 97 A_CAD10 R14 102 A_CAD14 F15 154 MFUNC0 K6 28 B_CC/BE0 P18 112 A_CCLK W16 104 A_CC/BE1

E1 6 AD7 K2 25 B_RSVD P17 111 A_CDEVSEL T19 105 A_RSVD

CCP

PIN NO.

GHK PDV

F3 7 V

B12 173 AD29 K19 128 A_CAD23 P10 80 B_RSVD

G1 14 AD1 N18 117 A_CC/BE2 W9 71 B_CAUDIO

G2 13 GND N19 118 A_CAD17 U11 83 A_CAD0

J18 134 A_CVS1 P12 89 A_CAD6 P13 94 A_CC/BE0

CCI

PIN NO.

GHK PDV

K18 129 GND R19 110 A_CGNT

K15 131 A_CAD24 R2 49 B_CTRDY

CCB

N1 39 B_CC/BE1 U6 59 B_CAD21

CCA

P2 44 GND W14 95 A_CAD9

PIN NO.

GHK PDV

U7 64 V

P7 56 B_CVS2

P9 75 GND

V15 101 A_CAD15

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PCI1221 GHK/PDV

SIGNAL NAME

PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

Table 2. CardBus PC Card Signal Names Sorted Alphabetically

PIN NO.

GHK PDV

A_CAD0 U11 83 A_CSTOP R18 109 B_CAD12 M1 34 CLOCK E19 151 A_CAD1 R11 85 A_CSTSCHG H19 138 B_CAD13 L5 33 DATA F14 152 A_CAD2 P11 84 A_CTRDY P19 114 B_CAD14 M3 36 DEVSEL C7 197 A_CAD3 U12 88 A_CVS1 J18 134 B_CAD15 M2 35 FRAME F8 193 A_CAD4 V12 87 A_CVS2 M19 122 B_CAD16 M6 37 GND E8 194 A_CAD5 R12 90 A_RSVD G14 146 B_CAD17 W4 53 GND C5 207 A_CAD6 P12 89 A_RSVD W13 91 B_CAD18 U5 54 GND F12 167 A_CAD7 V13 92 A_RSVD T19 105 B_CAD19 R6 55 GND E18 153 A_CAD8 U13 93 AD0 H5 15 B_CAD20 V5 57 GND B10 181 A_CAD9 W14 95 AD1 G1 14 B_CAD21 U6 59 GND G2 13 A_CAD10 R13 97 AD2 G3 12 B_CAD22 V6 60 GND J5 22 A_CAD11 U14 98 AD3 H6 11 B_CAD23 W6 62 GND K18 129 A_CAD12 P14 100 AD4 F1 10 B_CAD24 V7 65 GND P2 44 A_CAD13 W15 99 AD5 G5 9 B_CAD25 W7 66 GND V14 96 A_CAD14 R14 102 AD6 F2 8 B_CAD26 R8 67 GND P9 75 A_CAD15 V15 101 AD7 E1 6 B_CAD27 W10 76 GNT C13 168 A_CAD16 U15 103 AD8 G6 4 B_CAD28 V10 77 IDSEL C10 182 A_CAD17 N19 118 AD9 F5 3 B_CAD29 U10 78 IRDY A7 195 A_CAD18 M15 119 AD10 E3 2 B_CAD30 R10 79 LATCH F17 150 A_CAD19 M18 121 AD11 C12 172 B_CAD31 W11 81 MFUNC0 F15 154 A_CAD20 L19 123 AD12 A4 208 B_CAUDIO W9 71 MFUNC1 E17 155 A_CAD21 L17 125 AD13 E6 206 B_CBLOCK N6 42 MFUNC2 A16 157 A_CAD22 L15 126 AD14 B5 205 B_CC/BE0 K6 28 MFUNC3 C15 158 A_CAD23 K19 128 AD15 F6 204 B_CC/BE1 N1 39 MFUNC4 E14 159 A_CAD24 K15 131 AD16 B8 191 B_CC/BE2 T1 52 MFUNC5 F13 160 A_CAD25 K14 132 AD17 A8 190 B_CC/BE3 P8 63 MFUNC6/CLKRUN B15 161 A_CAD26 J19 133 AD18 E9 189 B_CCD1 H3 16 PAR C6 202 A_CAD27 H14 141 AD19 F9 188 B_CCD2 R9 74 PCLK A10 180 A_CAD28 H15 142 AD20 B9 186 B_CCLK P6 48 PERR A6 199 A_CAD29 G18 144 AD21 A9 185 B_CCLKRUN U9 73 PRST A14 166 A_CAD30 G17 145 AD22 F10 184 B_CDEVSEL R1 47 REQ B13 169 A_CAD31 F19 147 AD23 E10 183 B_CFRAME R3 51 RI_OUT/PME C14 163 A_CAUDIO J15 137 AD24 F11 179 B_CGNT P3 46 SERR B6 200 A_CBLOCK P15 107 AD25 E13 165 B_CINT V8 69 SPKROUT G15 149 A_CC/BE0 P13 94 AD26 C11 177 B_CIRDY P5 50 STOP F7 198 A_CC/BE1 W16 104 AD27 B11 176 B_CPAR N3 41 SUSPEND D19 156 A_CC/BE2 N18 117 AD28 A12 174 B_CPERR P1 43 TRDY B7 196 A_CC/BE3 K17 130 AD29 B12 173 B_CREQ R7 61 V A_CCD1 V11 82 AD30 E12 171 B_CRST W5 58 V A_CCD2 H17 140 AD31 A13 170 B_CSERR W8 70 V A_CCLK P18 112 B_CAD0 H2 17 B_CSTOP N5 45 V A_CCLKRUN H18 139 B_CAD1 J1 19 B_CSTSCHG V9 72 V A_CDEVSEL P17 111 B_CAD2 H1 18 B_CTRDY R2 49 V A_CFRAME N17 116 B_CAD3 J3 21 B_CVS1 U8 68 V A_CGNT R19 110 B_CAD4 J2 20 B_CVS2 P7 56 V A_CINT J17 135 B_CAD5 K1 24 B_RSVD K2 25 V A_CIRDY M14 115 B_CAD6 J6 23 B_RSVD N2 40 V A_CPAR R17 106 B_CAD7 K3 26 B_RSVD P10 80 V A_CPERR N14 108 B_CAD8 K5 27 C/BE0 E2 5 V A_CREQ L14 127 B_CAD9 L1 29 C/BE1 A5 203 V A_CRST L18 124 B_CAD10 L2 30 C/BE2 C8 192 V A_CSERR J14 136 B_CAD11 L6 32 C/BE3 A15 162 V

PIN NO.

GHK PDV

PIN NO.

GHK PDV

CC CC CC CC CC CC CC CC CC CC CCA CCB CCI CCP CCP

PIN NO.

GHK PDV

C9 187 A11 175 B14 164

F3 7

E7 201

G19 143

L3 31

N15 113

U7 64

W12 86

M17 120

M5 38

F18 148

D1 1 E11 178

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SIGNAL NAME

PCI1221 GHK/PDV

PC CARD CONTROLLERS

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Pin Number

PIN NO.

GHK PDV

D1 1 V A4 208 AD12 F2 8 AD6 K14 132 A_A1 E6 206 AD13 E7 201 V C6 202 PAR C7 197 DEVSEL K17 130 A_REG F7 198 STOP F8 193 FRAME L2 E8 194 GND E9 189 AD18 L3 A8 190 AD17 A9 185 AD21 L6 B9 186 AD20 B10 181 GND L1

C10 182 IDSEL C11 177 AD26 L17 125 A_A5

E11 178 V A12 174 AD28 B13 169 REQ L14 127 A_INPACK A13 170 AD31 E13 165 AD25 L15 126 A_A4 A14 166 PRST G15 149 SPKROUT M1 A15 162 C/BE3 F14 152 DATA M2 E14 159 MFUNC4 E19 151 CLOCK M3

C15 158 MFUNC3 F17 150 LATCH L5

A16 157 MFUNC2 F1 10 AD4 M18 121 A_A25

E3 2 AD10 H6 11 AD3 L18 124 A_RESET C5 207 GND G3 12 AD2 L19 123 A_A6 B5 205 AD14 G5 9 AD5 M19 122 A_VS2 A5 203 C/BE1 G17 145 A_D9 M5 A6 199 PERR F18 148 V A7 195 IRDY F19 147 A_D10 N2 B8 191 AD16 G14 146 A_D2 M6

C9 187 V E10 183 AD23 H5 15 AD0 M17 120 V F11 179 AD24 H3 16 B_CD1 M15 119 A_A7 A11 175 V E12 171 AD30 H14 141 A_D0 N6 F12 167 GND G18 144 A_D1 P1

C14 163 RI_OUT/PME G19 143 V

F13 160 MFUNC5 H15 142 A_D8 N3 E17 155 MFUNC1 H1 18 B_D11 N15 113 V

D19 156 SUSPEND J1

F5 3 AD9 J2

G6 4 AD8 H2 17 B_D3 P19 114 A_A22

E2 5 C/BE0 J15 137 A_BVD2(SPKR)P3

F6 204 AD15 H17 140 A_CD2 R1

B6 200 SERR H18 139 A_WP(IOIS16)P6

B7 196 TRDY H19 138 A_BVD1(STSCHG/RI)N545B_A20

C8 192 C/BE2 J5

F9 188 AD19 J6 F10 184 AD22 K1 A10 180 PCLK J3 21 B_D5 U9 B11 176 AD27 J19 133 A_A0 V10

C12 172 AD11 J14 136 A_WAIT W11 C13 168 GNT J17 135 A_READY(IREQ)R1185A_D4

B14 164 V B15 161 MFUNC6 K3 E18 153 GND K5 F15 154 MFUNC0 K6

E1 6 AD7 K2

CCP

PIN NO.

GHK PDV

F3 7 V

B12 173 AD29 K19 128 A_A3

G1 14 AD1 N18 117 A_A12

G2 13 GND N19 118 A_A24

J18 134 A_VS1 P12

CCI

B_D4 N17 116 A_A23

B_D12 M14 115 A_A15

GND R7

B_D13 V7

B_D6 V8

B_D7 U13

B_D15 R13

B_CE1 P18 112 A_A16

B_D14 P17 111 A_A21

PIN NO.

GHK PDV

K18 129 GND

K15 131 A_A2

B_CE2

B_OE

B_A10

B_A11

B_IOWR

B_A9

B_IORD

B_A8

B_A18

B_A17

B_A19

B_A14

GND

B_A13

B_WE

B_A21

B_A16

B_INPACK

B_A2

B_READY(IREQ)

B_WP(IOIS16)

B_D8

B_D10

A_D13

A_D15

A_CE2

CCB

CCA

SCPS042 – JULY 1998

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PCI1221 GHK/PDV

SIGNAL NAME

PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Pin Number (Continued)

PIN NO.

GHK PDV

R19 110 A_WE T1

P5 R2 V5 V6 U7 U8 V9

W10

P10 P11 U12 V13 V14 P14 R18 109 A_A20 U15 N14 108 A_A14 R17 106 A_A13 P15 107 A_A19 W4

B_A15 R3

B_A22 P7

B_A6 U6

B_A4 P8

B_VS1 W9

68 72 B_BVD1(STSCHG/RI)

B_D0 R10

B_D2 U11

A_D11 V12

A_D5 W13

A_D7 W14

GND W15

A_A11 V15

100

PIN NO.

GHK PDV

52 51 56 59 63

67 71

75 79 83 87 91 95

99 101 103

PIN NO.

GHK PDV

B_A12 U5 B_A23 R6 B_VS2 W5 B_A5 W6 B_REG W7 B_A0 W8 B_BVD2(SPKR)R974B_CD2 GND U10 B_D9 V11 A_D3 W12 A_D12 R12 A_D14 P13 A_A10 U14 A_IORD R14 A_IOWR W16 A_A17 T19 105 A_A18

B_A24

54 55 58 62 66 70

78 82 86 90 94

98 102 104

B_A7 B_A25 B_RESET B_A3 B_A1 B_WAIT

B_D1 A_CD1 V

A_D6 A_CE1 A_OE A_A9 A_A8

Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically

PIN NO.

GHK PDV

A_A0 J19 133 A_A20 R18 109 A_D8 H15 142 A_A1 K14 132 A_A21 P17 111 A_D9 G17 145

A_A2 K15 131 A_A22 P19 114 A_D10 F19 147 A_A3 K19 128 A_A23 N17 116 A_D11 P11 A_A4 L15 126 A_A24 N19 118 A_D12 V12 A_A5 L17 125 A_A25 M18 121 A_D13 P12 A_A6 L19 123 A_BVD1(STSCHG/RI) H19 138 A_D14 W13 A_A7 M15 119 A_BVD2(SPKR) J15 137 A_D15 U13 A_A8 W16 A_A9 R14 A_A10 W14 A_A11 P14 A_A12 N18 117 A_D0 H14 141 A_READY(IREQ) J17 135 A_A13 R17 106 A_D1 G18 144 A_REG K17 130 A_A14 N14 108 A_D2 G14 146 A_RESET L18 124 A_A15 M14 115 A_D3 U11 A_A16 P18 112 A_D4 R11 A_A17 U15 A_A18 T19 105 A_D6 R12 A_A19 P15 107 A_D7 V13

A_CD1 V11

104

A_CD2 H17 140 A_IORD W15

102

A_CE1 P13

A_CE2 R13

100

A_D5 U12

103

PIN NO.

GHK PDV

94 97

83 85 88 90 92

PIN NO.

GHK PDV

84 87 89 91 93

A_INPACK L14 127

A_IOWR V15 A_OE U14

A_VS1 J18 134 A_VS2 M19 122 A_WAIT J14 136 A_WE R19 110 A_WP(IOIS16) H18 139

101

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SIGNAL NAME

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

PIN NO.

GHK PDV

AD0 H5 15 B_A18 N2 AD1 G1 14 B_A19 N6 AD2 G3 12 B_A20 N5 AD3 H6 11 B_A21 R1 AD4 F1 10 B_A22 R2 AD5 G5 9 B_A23 R3 AD6 F2 8 B_A24 W4 AD7 E1 6 B_A25 R6 AD8 G6 4 AD9 F5 3 B_BVD2(SPKR) W9 AD10 E3 2 B_CD1 H3 16 GND P9 AD11 C12 172 B_CD2 R9 AD12 A4 208 B_CE1 K6 AD13 E6 206 B_CE2 L2 AD14 B5 205 B_D0 W10 AD15 F6 204 B_D1 U10 AD16 B8 191 B_D2 P10 AD17 A8 190 B_D3 H2 17 MFUNC2 A16 157 AD18 E9 189 B_D4 J1 AD19 F9 188 B_D5 J3 21 MFUNC4 E14 159 AD20 B9 186 B_D6 K1 AD21 A9 185 B_D7 K3 AD22 F10 184 B_D8 V10 AD23 E10 183 B_D9 R10 AD24 F11 179 B_D10 W11 AD25 E13 165 B_D11 H1 18 PRST A14 166 AD26 C11 177 B_D12 J2 AD27 B11 176 B_D13 J6 AD28 A12 174 B_D14 K2 AD29 B12 173 B_D15 K5 AD30 E12 171 B_INPACK R7 AD31 A13 170 B_IORD L5 B_A0 R8 B_A1 W7 B_A2 V7 B_A3 W6 B_A4 V6 B_A5 U6 B_A6 V5 B_A7 U5 B_A8 N1 B_A9 M3 B_A10 L1 B_A11 M1 B_A12 T1 B_A13 N3 B_A14 P1 B_A15 P5 B_A16 P6 B_A17 M6

B_BVD1(STSCHG/RI)

B_IOWR M2

B_OE L6

B_READY(IREQ) V8

B_REG P8

B_RESET W5

B_VS1 U8

B_VS2 P7

B_WAIT W8

B_WE P3

B_WP(IOIS16) U9

C/BE0 E2 5 V

C/BE1 A5 203 V

C/BE2 C8 192 V

C/BE3 A15 162 V

CLOCK E19 151 V

DATA F14 152 V

DEVSEL C7 197

FRAME F8 193

PIN NO.

GHK PDV

40 42 45 47 49 51 53 55

72 71

74 28 30 76 78 80

24 26 77 79 81

20 23 25 27 61 33 35 32 69 63 58 68 56 70 46 73

PIN NO.

GHK PDV

GND E8 194 GND C5 207 GND F12 167 GND E18 153 GND B10 181 GND G2 13 GND J5 GND K18 129 GND P2 GND V14

44 96 75

GNT C13 168 IDSEL C10 182 IRDY A7 195 LATCH F17 150 MFUNC0 F15 154 MFUNC1 E17 155

MFUNC3 C15 158

MFUNC5 F13 160 MFUNC6 B15 161 PAR C6 202 PCLK A10 180 PERR A6 199

REQ B13 169 RI_OUT/PME C14 163 SERR B6 200 SPKROUT G15 149 STOP F7 198 SUSPEND D19 156 TRDY B7 196 V

CC CC CCA CCB CCI CCP CCP

A11 175

C9 187

B14 164

F3 7 E7 201

G19 143

N15 113

W12

M17 120

F18 148

D1 1

E11 178

64 86

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PCI1221 GHK/PDV

FUNCTION

I/O

NAME

TYPE

NAME

TYPE

PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

power supply

TERMINAL

NAME PDV NUMBER GHK NUMBER

GND

CCA

CCB

CCI

CCP

13, 22, 44, 75, 96, 129, 153,

167, 181, 194, 207

7, 31, 64, 86, 113, 143, 164,

175, 187, 201

120 M17

38 M5

148 F18

1, 178 D1, E11 Clamp voltage for PCI signaling (5 V or 3.3 V)

G2, J5, P2, P9, V14, K18, E18,

F12, B10, E8, C5

F3, L3, U7, W12, N15, G19,

B14, A11, C9, E7

Device ground terminals

Power supply terminal for core logic (3.3 V) Clamp voltage for PC Card A interface. Indicates Card A

signaling environment, 5 V or 3.3 V. Clamp voltage for PC Card B interface. Indicates Card B

signaling environment, 5 V or 3.3 V. Clamp voltage for interrupt subsystem interface and

miscellaneous I/O. (5 V or 3.3 V)

PC Card power switch

TERMINAL

PIN NUMBER

PDV GHK

CLOCK 151 E19 I/O

DATA 152 F14 O

LATCH 150 F17 O

PCI system

TERMINAL

PIN NUMBER

PDV GHK

PCLK 180 A10 I

PRST

166 A14 I

FUNCTION

Three-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1221 output by using the P2CCLK bit in the System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz.

If a system design defines this terminal as an output, then this terminal requires an external pull down resister. The frequency of the PCI1221 output CLOCK is derived from dividing the PCI CLK by 36.

Three-line power switch data. DATA is used to serially communicate socket power control information to the power switch.

Three-line power switch latch. LATCH is asserted by the PCI1221 to indicate to the PC Card power switch that the data on the DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface.

I/O

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1221 to place all output buffers in a high-impedance state and reset all internal registers. When PRST completely nonfunctional. After PRST

When the SUSPEND and PRST are asserted, the device is protected from the PRST clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

FUNCTION

is asserted, the device is

is deasserted, the PCI1221 is in its default state.

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NAME

TYPE

PCI address and data

TERMINAL

PIN NUMBER

PDV GHK

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR 202 C6 I/O

170 171 173 174 176 177 165 179 183 184 185 186 188 189 190 191 204 205 206 208 172

2 3 4 6 8 9

11 12 14 15

162 192 203

A13 E12 B12 A12 B11 C11 E13 F11 E10 F10

A9 B9 F9 E9 A8 B8 F6 B5 E6 A4

C12

E3 F5

E1 F2

F1 H6 G3 G1 H5

A15

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

Terminal Functions (Continued)

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31-AD0 contain a 32-bit address or

I/O

other destination information. During the data phase, AD31-AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. C/BE0 (AD15–AD8), C/BE2

PCI bus parity. In all PCI bus read and write cycles, the PCI1221 calculates even parity across the AD31–AD0 and C/BE3– indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

C/BE0 buses. As an initiator during PCI cycles, the PCI1221 outputs this parity

FUNCTION

–C/BE0 define the bus command. During the data

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1

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PCI1221 GHK/PDV

NAME

TYPE

PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

PCI interface control

TERMINAL

PIN NUMBER

PDV GHK

DEVSEL

FRAME

GNT

IDSEL 182 C10 I

IRDY

PERR REQ

SERR

STOP

TRDY

197 C7 I/O

193 F8 I/O

168 C13 I

195 A7 I/O

199 A6 I/O

169 B13 O PCI bus request. REQ is asserted by the PCI1221 to request access to the PCI bus as an initiator.

200 B6 O

198 F7 I/O

196 B7 I/O

I/O

Terminal Functions (Continued)

FUNCTION

PCI device select. The PCI1221 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1221 monitors DEVSEL responds before timeout occurs, the PCI1221 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When

is deasserted, the PCI bus transaction is in the final data phase.

FRAME PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1221 access to the PCI bus

after the current data transaction has completed. GNT depending on the PCI bus parking algorithm.

Initialization device select. IDSEL selects the PCI1221 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1221 when enabled through the command register indicating a system error has occurred. The PCI1221 need not be the target of the PCI cycle to assert this signal. When SERR pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

is enabled through bit 6 of the command register.

is enabled in the control register, this signal also

is used for target disconnects and is commonly asserted by target devices

until a target responds. If no target

may or may not follow a PCI bus request,

and TRDY

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I/O

NAME

TYPE

Terminal Functions (Continued)

multifunction and miscellaneous pins

TERMINAL

PIN NUMBER

PDV GHK

Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0,

MFUNC0 154 F15 I/O

MFUNC1 155 E17 I/O

MFUNC2 157 A16 I/O

MFUNC3 158 C15 I/O

GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE parallel IRQ. Refer to the configuration details.

Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE parallel IRQ. Refer to the configuration details.

Serial data (SDA). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC1 terminal provides the SDA signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the other serial bus applications.

Multifunction terminal 2. MFUNC2 can be configured as GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. Refer to the configuration details.

Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket

activity LED output, ZV switching outputs, CardBus audio PWM, GPE

to the

multifunction routing register

FUNCTION

multifunction routing register

serial bus interface implementation

description on page 62 for configuration details.

multifunction routing register

description on page 62 for configuration details.

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

, or a

description on page 62 for

, or a

description on page 62 for

description on page 29 for details on

, or a parallel IRQ. Refer to the

description on page 62 for

, or a parallel IRQ. Refer

MFUNC4 159 E14 I/O

MFUNC5 160 F13 I/O

MFUNC6 161 B15 I/O

RI_OUT/PME 163 C14 O

SPKROUT

SUSPEND 156 D19 I

149 G15 O

Serial clock (SCL). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC4 terminal provides the SCL signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the other serial bus applications.

Multifunction terminal 5. MFUNC5 can be configured as GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

multifunction routing register

Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. Refer to the

Ring Indicate Out and Power Management Event Output. Terminal provides an output for ring-indicate or PME

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1221 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR

Suspend. SUSPEND is used to protect the internal registers from clearing when the PRST signal is asserted. See

serial bus interface implementation

description on page 62 for configuration details.

multifunction routing register

signals.

//CAUDIO inputs.

suspend mode

description on page 40 for details.

description on page 29 for details on

, or a parallel IRQ. Refer to the

description on page 62 for configuration details.

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PCI1221 GHK/PDV

FUNCTION

PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

Terminal Functions (Continued)

16-bit PC Card address and data (slots A and B)

TERMINAL

PIN NUMBER

NAME

PDV

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 121 and M18 are A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R6 are B_A25.

121 118 116 114

111 109 107 105 103 112 115 108 106 117 100

95 102 104 119 123 125 126 128 131 132 133

84 147 145 142

83 146 144 141

SLOT A

†

GHK

M18 N19 N17 P19 P17 R18 P15

T19 U15 P18 M14 N14 R17 N18 P14 W14 R14 W16 M15

L19

L17

L15 K19 K15 K14

J19 U13

W13 P12 V12

P11

F19 G17 H15 V13 R12 U12 R11 U11 G14 G18 H14

SLOT B

PDV

55 53 51 49 47 45 42 40 37 48 50 43 41 52 34 29 36 39 54 57 59 60 62 65 66 67

27 25 23 20 18 81 79 77 26 24 21 19 17 80 78 76

GHK

R6 W4 R3 R2 R1 N5 N6 N2 M6

M3 N1 U5

W7 R8

W11

R10 V10

H2 P10 U10

W10

I/O

‡

TYPE

P6 P5 P1

K5 K2 J6 J2

K3 K1 J3 J1

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

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FUNCTION

PC CARD CONTROLLERS

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B)

TERMINAL

PIN NUMBER

NAME

PDV GHK PDV GHK

BVD1 (STSCHG

BVD2 (SPKR

)

CD1 CD2

CE1 CE2

INPACK 127 L14 61 R7 I

IORD

IOWR

OE 98 U14 32 L6 O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 are A_INP ACK .

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 are B_INPACK

138 H19 72 V9 I

/RI)

137 J15 71 W9 I

140

9497P13

99 W15 33 L5 O

101 V15 35 M2 O

†

SLOT A

V11 H171674H3R9

R132830

SLOT B

K6 L2

I/O

‡

TYPE

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See

configuration register

status bits for this signal. Status change. STSCHG

write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI

Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See

configuration register register

status bits for this signal. Speaker. SPKR

and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1221 and are output on SPKROUT .

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1

CD2 Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1

odd-numbered address bytes. Input acknowledge. INP ACK is asserted by the PC Card when it can respond to

an I/O read cycle at the current address. I/O read. IORD is asserted by the PCI1221 to enable 16-bit I/O PC Card data

output during host I/O read cycles. I/O write. IOWR is driven low by the PCI1221 to strobe write data into 16-bit I/O

PC Cards during host I/O write cycles. Output enable. OE is driven low by the PCI1221 to enable 16-bit memory PC

Card data output during host memory read cycles.

on page 88 and the

are pulled low. For signal status, see

on page 89 for enable bits. See

ExCA interface status register

is used to alert the system to a change in the READY ,

is used by 16-bit modem cards to indicate a ring detection.

on page 89 for enable bits. See

ExCA interface status register

is an optional binary audio signal available only when the card

enables even-numbered address bytes, and CE2 enables

ExCA card status-change interrupt

interface status register

PCI1221 GHK/PDV

SCPS042 – JULY 1998

ExCA card status-change

on page 85 for the

ExCA card status-change

on page 85 for the

and

on page 88.

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PCI1221 GHK/PDV

FUNCTION

PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B) (continued)

TERMINAL

PIN NUMBER

NAME

PDV GHK PDV GHK

READY (IREQ

)

REG

RESET 124 L18 58 W5 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT

WE 110 R19 46 P3 O

WP (IOIS16

)

VS1 VS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 1 10 and R19 are A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3 are B_WE

135 J17 69 V8 I

130 K17 63 P8 O

136 J14 70 W8 I

139 H18 73 U9 I

134 122

†

SLOT A

J18

M196856U8P7

SLOT B

I/O

‡

TYPE

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ that a device on the 16-bit I /O PC Card requires service by the host software.

is high (deasserted) when no interrupt is requested.

IREQ Attribute memory select. REG remains high for all common memory accesses.

When REG and to the I/O space (IORD accessed section of card memory and is generally used to record card capacity and other configuration and attribute information.

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16

I/O is 16 bits. IOIS16 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction

I/O

with each other, determine the operating voltage of the 16-bit PC Card.

is asserted, access is limited to attribute memory (OE or WE active)

is asserted by a 16-bit I/O PC Card to indicate to the host

or IOWR active). Attribute memory is a separately

) function.

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the

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FUNCTION

PC CARD CONTROLLERS

Terminal Functions (Continued)

CardBus PC Card interface system (slots A and B)

TERMINAL

PIN NUMBER

NAME

PDV GHK PDV GHK

CCLK 112 P18 48 P6 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 1 12 and P18 are A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 are B_CCLK.

139 H18 73 U9 O

124 L18 58 W5 I/O

SLOT A

†

SLOT B

I/O

‡

TYPE

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST CAUDIO, CCD2-1 all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1221 to indicate that the CCLK frequency is going to be decreased.

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST CardBus PC Card signals must be 3-stated, and the PCI1221 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

, and CVS2-CVS1 are sampled on the rising edge of CCLK, and

, CCLKRUN, CINT, CSTSCHG,

PCI1221 GHK/PDV

SCPS042 – JULY 1998

is asserted, all

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PCI1221 GHK/PDV

FUNCTION

PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

Terminal Functions (Continued)

CardBus PC Card address and data (slots A and B)

TERMINAL

PIN NUMBER

NAME

PDV GHK PDV GHK

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR 106 R17 41 N3 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 are A_CP AR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 are B_CPAR.

147 145 144 142 141 133 132 131 128 126 125 123 121

119

118 103 101 102

100

98 97 95 93 92 89 90 87 88 84 85 83

130

117 104

SLOT A

†

F19 G17 G18 H15 H14

J19

K14

K15

K19

L15

L17

L19 M18 M15 N19 U15

V15 R14 W15

P14 U14 R13 W14 U13

V13

P12 R12

V12 U12

P11

R11

U11

K17 N18 W16

P13

SLOT B

81 79 78 77 76 67 66 65 62 60 59 57 55 54 53 37 35 36 33 34 32 30 29 27 26 23 24 20 21 18 19 17

63 52 39 28

W11

R10 U10 V10

W10

W4 M6 M2 M3

V6 U6 V5 R6 U5

L6 L2

L1 K5 K3

J6 K1

J3 H1

J1 H2

T1 N1 K6

I/O

‡

TYPE

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3– used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. CC/BE0 applies to byte 1 (CAD15-CAD8), CC/BE2 applies to byte 2 (CAD23-CAD8), and CC/BE3

CardBus parity. In all CardBus read and write cycles, the PCI1221 calculates even parity across the CAD and CC/BE PCI1221 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

CC/BE0 defines the bus command. During the data phase, this 4-bit bus is

applies to byte 0 (CAD7-CAD0), CC/BE1

applies to byte 3 (CAD31-CAD24).

buses. As an initiator during CardBus cycles, the

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FUNCTION

ith CVS1

CVS2 to identif

I/O

ith CCD1

CCD2 to identif

PC CARD CONTROLLERS

Terminal Functions (Continued)

CardBus PC Card interface control (slots A and B)

TERMINAL

PIN NUMBER

NAME

PDV GHK PDV GHK

CAUDIO 137 J15 71 W9 I

CBLOCK

CCD1 CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 134 J18 68 U8 CVS2 122 M19 56 P7

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 137 and J15 are A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 71 and W9 are B_CAUDIO.

107 P15 42 N6 I/O

82 V11 16 H3

140 H17 74 R9

111 P17 47 R1 I/O

116 N17 51 R3 I/O

110 R19 46 P3 I

135 J17 69 V8 I

115 M14 50 P5 I/O

108 N14 43 P1 I/O

127 L14 61 R7 I

136 J14 70 W8 I

109 R18 45 N5 I/O

138 H19 72 V9 I

114 P19 49 R2 I/O

SLOT A

†

SLOT B

I/O

‡

TYPE

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1221 supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

w the operating voltage and card type.

CardBus device select. The PCI1221 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1221 monitors CDEVSEL PCI1221 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME transfers continue while this signal is asserted. When CFRAME CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI1221 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY CTRDY are both sampled asserted, wait states are inserted.

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1221 can report CSERR on the PCI interface.

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status, and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’ s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY are inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

n conjunction w

to determine the operating voltage and card type.

and

until a target responds. If no target responds before timeout occurs, the

is asserted to indicate that a bus transaction is beginning, and data

y card insertion and interrogate cards to determine

and CTRDY are asserted. Until CIRDY and

to the system by assertion of SERR

is used for target disconnects, and is

and CTRDY are asserted; until this time, wait states

and

y card insertion and interrogate cards

PCI1221 GHK/PDV

SCPS042 – JULY 1998

is deasserted, the

is driven by the card

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PCI1221 GHK/PDV PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

power supply sequencing

The PCI1221 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamping voltage. The core power supply is always 3.3 V . The clamp voltage can be either 3.3 V or 5 V , depending on the interface. The following power-up and power-down sequences are recommended.

The power-up sequence is:

1. Apply 3.3-V power to the core.

2. Assert PRST

to the device to disable the outputs during power up. Output drivers must be powered up in

the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.

3. Apply the clamping voltage. The power-down sequence is:

1. Use PRST to switch outputs to a high-impedance state.

2. Remove the clamping voltage.

3. Remove the 3.3-V power from the core.

I/O characteristics

Figure 1 shows a 3-state bidirectional buffer. The provides the electrical characteristics of the inputs and outputs.

NOTE:

The PCI1221 meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification Rev. 2.2.

Tied for Open Drain

recommended operating conditions

CCP

Pad

table, on page 120,

Figure 1. 3-State Bidirectional Buffer

NOTE:

Unused pins (input or I/O) must be held high or low to prevent them from floating.

clamping voltages

The clamping voltages are set to match whatever external environment the PCI1221 will be working with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1221 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, V

The PCI1221 requires four separate clamping voltages because it supports a wide range of features. The four voltages are listed and defined in the

recommended operating conditions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

can be connected to a 5-V power supply.

CCP

, on page 112.

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

peripheral component interconnect (PCI) interface

The PCI1221 is fully compliant with the PCI Local Bus Specification Rev. 2.2. The PCI1221 provides all required signals for PCI master or slave operation, and may operate in either a 5-V of 3.3-V signaling environment by connecting the V PCI1221 provides the optional interrupt signals INTA and INTB.

PCI bus lock (LOCK)

The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1221 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal via the multifunction routing register, see the Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock.

An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video.

terminals to the desired voltage level. In addition to the mandatory PCI signals, the

CCP

multifunction routing register

description on page 62 for details.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario, the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress.

The PCI1221 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the 2.2 PCI specification, and the issue is resolved by the PCI master using LOCK

loading subsystem identification

The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 95 requirement.

The PCI1221 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read only , but can be made read/write by setting the SUBSYSRW bit in the system control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).

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PCI1221 GHK/PDV PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

loading subsystem identification (continued)

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The PCI1221 loads the data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI1221 core, including the serial bus state machine (see SUSPEND).

The PCI1221 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM. Refer to

serial bus interface

on page 29 for details on the two-wire serial bus controller and applications.

PC Card applications

This section describes the PC Card interfaces of the PCI1221:

Card insertion/removal and recognition

P2C power-switch interface

Zoom video support

Speaker and audio applications

LED socket activity indicators

CardBus socket registers

suspend mode

, on page 40, for details on using

PC Card insertion/removal and recognition

The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined.

The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1997 PC Card Standard and in Table 5.

Table 5. PC Card Card-Detect and Voltage-Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE

Ground Ground Open Open 5 V 16-bit PC Card 5 V Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Open Ground LV 16-bit PC Card 3.3 V Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V

Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V

Ground Ground Ground Open LV 16-bit PC Card Y.Y V Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved

Ground Connect to CVS2 Connect to CCD1 Ground Reserved

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PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

P2C power-switch interface (TPS2202A/2206)

The PCI1221 provides a P2C (PCMCIA Peripheral Control) interface for control of the PC Card power switch. The CLOCK, DATA, and LATCH terminals interface with the TI TPS2202A/2206 dual-slot PC Card power interface switches to provide power switch support. Figure 2 shows the terminal assignments of the TPS2206, and Figure 3 illustrates a typical application where the PCI1221 represents the PCMCIA controller.

5 V 5 V

DATA

CLOCK

LATCH

RESET

12 V A VPP A VCC A VCC A VCC

GND

RESET

3.3 V

NC – No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

5 V NC NC NC NC NC 12 V BVPP BVCC BVCC BVCC NC OC

3.3 V

Figure 2. TPS2206 Terminal Assignments

The CLOCK terminal on the PCI1221 can be an input or an output. The PCI1221 defaults the CLOCK terminal as an input to control the serial interface and the internal state machine. The P2CCLK bit in the system control register can be set by the platform BIOS to enable the PCI1221 to generate and drive the CLOCK internally from the PCI clock. When the system design implements CLOCK as an output from the PCI1221, an external pull down is required.

Power Supply

12 V

5 V

3.3 V

Supervisor

PCI1221

(PCMCIA

Controller)

TPS2206

12 V 5 V

3.3 V

RESET RESET

CLOCK DATA LATCH

AVPP

AVCC AVCC AVCC

BVPP

BVCC BVCC BVCC

V V V V

PP1 PP2 CC CC

Figure 3. TPS2206 Typical Application

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PC Card

PCI1221 GHK/PDV PC CARD CONTROLLERS

SCPS042 – JUL Y 1998

zoom video support

The PCI1221 allows for the implementation of zoom video for PC Cards. Zoom video is supported by setting the ZVENABLE bit in the card control register on a per socket function basis. Setting this bit puts PC Card-16 address lines A25–A4 of the PC Card interface in the high-impedance state. These lines can then be used to transfer video and audio data directly to the appropriate controller. Card address lines A3-A0 can still be used to access PC Card CIS registers for PC Card configuration. Figure 4 illustrates a PCI1221 ZV implementation.

Audio

Codec

PCM Audio Input

Speakers

PC Card

Interface

Video

Audio

CRT

Motherboard

PCI Bus

VGA

Controller

Zoom Video

Port

19 4

PCI1221

Figure 4. Zoom Video Implementation Using PCI1221

Not shown in Figure 4 is the multiplexing scheme used to route either socket 0 or socket 1 ZV source to the graphics controller. The PCI1221 provides ZVSTAT, ZVSEL0, and ZVSEL1 signals on the multifunction terminals to switch external bus drivers. Figure 5 shows an implementation for switching between three ZV streams using external logic.

PCI1221

ZVSTAT ZVSEL0 ZVSEL1

0 1

Figure 5. Zoom Video Switching Application

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PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

zoom video support (continued)

Figure 5 illustrates an implementation using standard three-state bus drivers with active-low output enables. ZVSEL0 is an active-low output indicating that the Socket 0 ZV mode is enabled, and ZVSEL1 is an active-low output indicating that Socket 1 ZV is enabled. When both sockets have ZV mode enabled, the PCI1221 defaults to indicating socket 0 enabled through ZVSEL0; however , the PORTSEL bit in the card control register allows software to select the socket ZV source priority. Table 6 illustrates the functionality of the ZV output signals.

Table 6. PC Card Card-Detect and Voltage-Sense Connections

INPUTS OUTPUTS

PORTSEL SOCKET 0 ENABLE SOCKET 1 ENABLE ZVSEL0 ZVSEL1 ZVSTAT

X 0 0 1 1 0 0 1 X 0 1 1 0 0 1 1 0 1 1 X 1 1 0 1 1 1 0 0 1 1

Also shown in Figure 5 is a third ZV source that may be provided from a source such as a high-speed serial bus like IEEE1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an active-high output indicating that one of the PCI1221 sockets is enabled for ZV mode. The implementation shown in Figure 5 can be used if PC Card ZV is prioritized over other sources.

SPKROUT and CAUDPWM usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 pin becomes SPKR. This terminal is also used in CardBus binary audio applications, and is referred to as CAUDIO. SPKR

passes a TTL level digital audio signal to the PCI1221. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the two PC Card Sockets are XOR’ed in the PCI1221 to produce SPKROUT. This output is enabled by the SPKROUTEN bit in the card control register.

Older controllers support CAUDIO in binary or PWM mode but use the same pin (SPKROUT). Some audio chips may not support both modes on one pin and may have a separate pin for binary and PWM. The PCI1221 implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. The AUD2MUX bit located in the card control register is programmed on a per socket function basis to route a CardBus CAUDIO PWM terminal to CAUDPWM. If both CardBus functions enable CAUDIO PWM routing to CAUDPWM, then socket 0 audio takes precedence. Refer to the

multifunction routing register

description on

page 62 for details on configuring the MFUNC terminals. Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM.

System

Core Logic

BINARY_SPKR

Speaker

Subsystem

PWM_SPKR

PCI1221

SPKROUT

CAUDPWM

Figure 6. Sample Application of SPKROUT and CAUDPWM

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LED socket activity indicators

The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LEDA1 and LEDA2 signals can be routed to the multifunction terminals. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity. The LED_SKT output indicates socket activity to either socket 0 or socket 1. Refer to the

multifunction routing register

The LED signal is active high and is driven for 64-ms durations. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling, and it is left for the board designer to implement the circuit that best fits the application.

The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card 16, the LED activity signals are pulsed when READY/IREQ is low. For CardBus cards, the LED activity signals are pulsed if CFRAME, IRDY, or CREQ are active.

description on page 62 for details on configuring the multifunction terminals.

Current Limiting

R ≈ 500 Ω

PCI1221

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

LED

Figure 7. T wo Sample LED Circuits

As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut-off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.

If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), the LED signals remain driven.

CardBus socket registers

The PCI1221 contains all registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge specification. These registers exist as the CardBus socket registers, and are listed in Table 7.

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Table 7. CardBus Socket Registers

Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch

Socket power management 20h

serial bus interface

The PCI1221 provides a serial bus interface to load subsystem identification and select register defaults through a serial EEPROM and to provide a PC Card power switch interface alternative to P2C. Refer to

power-switch interface (TPS2202A/2206)

with various I2C and SMBus components.

on page 25 for details. The PCI1221 serial bus interface is compatible

P2C

serial bus interface implementation

The PCI1221 defaults to serial bus interface are disabled. To enable the serial interface, a pulldown resistor must be implemented on the LATCH terminal and the appropriate pullup must be implemented on the SDA and SCL signals, i.e. the MFUNC1 and MFUNC4 terminals. When the interface is detected, the SBDETECT bit in the system control register is set. The SBDETECT bit is cleared by a write back of 1.

The PCI1221 implements a two pin serial interface with one clock signal (SCL) and one data signal (SDA). When a pulldown is provided on the LATCH terminal, the SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal. The PCI1221 drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I2C. An example application implementing the two-wire serial bus is illustrated in Figure 8.

Serial

EEPROM

A0 A1 A2

SCL

SDA

PCI1221

LATCH

MFUNC4 MFUNC1

Figure 8. Serial EEPROM Application

Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow.

serial bus interface protocol

The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure Figure 8. The PCI1221 supports up to 100 Kb/s data transfer rate and is compatible with standard mode I2C using seven-bit addressing.

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serial bus interface protocol (continued)

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signalled when the SDA line transitions to low state while SCL is in the high state, as illustrated in Figure 9. The end of a requested data transfer is indicated by a stop condition, which is signalled by a low to high transition of SDA while SCL is in the high state, as shown in Figure 9. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or a stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 9. Serial Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited, however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. The acknowledge protocol is illustrated in Figure 10.

SCL From

Master

SDA Output

By Transmitter

SDA Output By Receiver

123 789

Figure 10. Serial Bus Protocol Acknowledge

The PCI1221 is a serial bus master; all other devices connected to the serial bus external to the PCI1221 are slave devices. As the bus master, the PCI1221 drives the SCL clock at nearly 100 kHz during bus cycles and three-states SCL (zero frequency) during idle states.

Typically, the PCI1221 masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. Refer to

serial bus EEPROM application

on page 32 for details on how the PCI1221

automatically loads the subsystem identification and other register defaults through a serial bus EEPROM. A byte write is illustrated in Figure 11. The PCI1221 issues a start condition and sends the seven bit slave device

address and the command bit zero. A zero in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1221, then an appropriate status bit is set in the serial bus control and status register. The word address byte is then sent by the PCI1221 and another slave acknowledgment is expected. Then the PCI1221 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition.

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