TEXAS INSTRUMENTS PCI1220 Technical data

查询PCI1220供应商

PCI Bus Power Management Interface Specification 1.0 Compliant

ACPI 1.0 Compliant

Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset

Packaged in 208-Pin TQFP

PCI Local Bus Specification Revision 2.1 Compliant

1995 PC Card Standard Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards

Supports Two PC Card or CardBus Slots With Hot Insertion and Removal

Uses Serial Interface to TI TPS2202/2206 Dual-Slot PC Card Power Switch

Supports Burst Transfers to Maximize Data Throughput

Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts

Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus

Supports Up to Five General-Purpose I/Os

Programmable Output Select for CLKRUN

Multifunction PCI Device With Separate Configuration Space for Each Socket

Five PCI Memory Windows and Two I/O Windows Available for Each PC Card16 Socket

Two I/O Windows and Two Memory Windows Available to Each CardBus Socket

Exchangeable Card Architecture (ExCA) Compatible Registers Are Mapped in Memory and I/O Space

Intel 82365SL-DF Register Compatible

Supports Distributed DMA (DDMA) and PC/PCI DMA

Supports 16-Bit DMA on Both PC Card Sockets

Supports Ring Indicate, SUSPEND, PCI CLKRUN,

LED Activity Pins

Supports PCI Bus Lock (LOCK)

Advanced Submicron, Low-Power CMOS T echnology

For the Complete Data Sheet for PCI1220, Please See Literature #SCPS016

and CardBus CCLKRUN

PCI1220

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 17. . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Electrical Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 20. . . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 21. . . . . . . . . . . . . . . .

Mechanical Data 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

description

The TI PCI1220 is a high-performance PCI-to-PC Card controller that supports two independent PC Card sockets compliant with the 1995 PC Card Standard. The PCI1220 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.1, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1220 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1220 is compliant with the PCI Local Bus Specification 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions. The PCI1220 is also compliant with the latest

PCI Bus Power Management Interface Specification

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1220 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1220 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1220 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features are designed into the PCI1220, such as socket activity light-emitting diode (LED) outputs, and are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

Unused PCI1220 inputs must be pulled up using a 43 kW resistor.

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PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

system block diagram

A simplified system block diagram using the PCI1220 is provided below. The PCI950 IRQ deseralizer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability.

The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.

The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1220 that include:

Programmable multifunction terminals

SUSPEND, RI_OUT/PME (power management control signal)

SPKROUT.

PCI Bus

PCI1220

Activity LED’s

TPS22xx

Power

Switch

PC Card

Socket A

PC Card

Socket B

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed

video signals too the VGA controller.

PCI1220

68 68

IRQSER

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

INTA

INTB

Interrupt

Controller

IRQ2–15

VGA

Controller

Audio

Sub-System

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PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

terminal assignments

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30

AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17 AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

SUSPEND

GND

MFUNC0

DATA

SPKROUT

LATCH

CLOCK

A_CAD31

152

151

150

149

VCCI

148

147

MFUNC1

154

153

156

155

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_CAD30

A_RSVD

A_CAD29

144

146

145

A_CAD28

142

143

A_CCD2

A_CAD27

A_CLKRUN

140

139

141

A_CAUDIO

A_CSTSCHG

A_CINT

A_CSERR

136

135

138

137

A_CAD26

A_CVS1

A_CAD25

132

134

133

PCI1220 CorePCI

A_CC/BE3

A_CAD24

GND

130

129

131

A_CAD23

A_CAD22

A_CREQ

126

128

127

Card A

A_CAD21

A_CRST

124

125

A_CAD20

A_CAD19

A_CVS2

122

121

123

Card B

CCA

A_CAD18

119

120

A_CC/BE2

A_CAD17

118

117

A_CFRAME

A_CTRDY

A_CIDRY

114

113

116

115

A_CCLKVA_CDEVSEL

112

A_CGNT

111

110

A_CSTOP

A_CBLOCK

A_CPERR

108

107

109

A_RSVD

A_CPAR

105 104

103 102 101 100

51 106

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

A_CC/BE1 A_CAD16 A_CAD14 A_CAD15 A_CAD12 A_CAD13 A_CAD11 A_CAD10 GND A_CAD9 A_CC/BE0 A_CAD8 A_CAD7 A_RSVD A_CAD5 A_CAD6 A_CAD3 A_CAD4

CC A_CAD1 A_CAD2 A_CAD0 A_CCD1 B_CAD31 B_RSVD B_CAD30 B_CAD29 B_CAD28 B_CAD27 GND B_CCD2 B_CLKRUN B_CSTSCHG B_CAUDIO B_CSERR B_CINT B_CVS1 B_CAD26 B_CAD25 B_CAD24 V

CC B_CC/BE3

B_CAD23 B_CREQ B_CAD22 B_CAD21 B_CRST B_CAD20 B_CVS2 B_CAD19 B_CAD18 B_CAD17

CCP

AD10

AD9

AD8

AD7

C/BE0

AD4

AD6

AD5

AD3

AD1

AD0

AD2

GND

B_CAD0

B_CAD2

B_CCD1

B_CAD1

B_CAD4

B_CAD3

GND

B_CAD6

B_CAD5

B_CAD7

B_RSVD

B_CAD8

B_CAD9

B_CAD10

B_CC/BE0

B_CAD11

B_CAD13

B_CAD14

B_CAD12

B_CAD15

CCB

B_CAD16

B_CC/BE1

B_CPAR

B_RSVD

B_CBLOCK

GND

B_CSTOP

B_CPERR

B_CCLK

B_CGNT

B_CDEVSEL

B_CIRDY

B_CTRDY

B_CFRAME

B_CC/BE2

PCI-to-CardBus Pin Diagram

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terminal assignments (continued)

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30 AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17

AD16

C/BE2

FRAME

GND IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

A_D10

A_D2

146

147

A_D9

A_D1

144

145

143

A_D8

A_D0

142

141

A_CD2

A_WP(IOIS16)

140

139

A_BVD1(STSCHG/RI)

A_READY(IREQ)

A_WAIT

A_A0

A_VS1

A_A2

136

135

134

133

A_A1

132

131

A_BVD2(SPKR)

138

137

PCI1220 CorePCI

A_REG

GND

130

129

A_A3

A_A4

A_INPACK

126

128

127

Card A

A_A5

A_RESET

124

125

A_A6

A_A25

A_VS2

122

121

123

Card B

CCA

120

A_A7

119

A_A12

A_A24

118

117

A_A23

A_A15

116

115

A_A22

114

113

A_A16VA_A21

112

CCI

SPKROUT

GND

MFUNC0

DATA

LATCH

CLOCK

152

151

150

149

148

SUSPEND

MFUNC1

154

153

156

155

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

111

A_A20

A_WE

110

109

A_A19

A_A14

108

107

A_A18

A_A13

105

104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

51 106

A_A8 A_A17 A_A9 A_IOWR A_A11 A_IORD A_OE A_CE2 GND A_A10 A_CE1 A_D15 A_D7 A_D14 A_D6 A_D13 A_D5 A_D12

CC A_D4 A_D11 A_D3 A_CD1 B_D10 B_D2 B_D9 B_D1 B_D8 B_D0 GND B_CD2 B_WP(IOIS16) B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A0 B_A1 B_A2 V

CC B_REG B_A3 B_INPACK B_A4 B_A5 B_RESET B_A6

B_VS2 B_A25 B_A7 B_A24

CCP

AD9

AD10

AD8

AD7

C/BE0

AD6

AD5

AD3

AD1

AD2

GND

AD0

B_D3

B_CD1

B_D11

B_D4

B_D5

B_D12

GND

B_D6

B_D13

B_D7

B_D14

AD4

B_D15

B_CE1

B_A10

B_CE2

B_OE

B_IORD

B_A11

B_IOWR

B_A9

CCB

B_A17

B_A8

B_A18

B_A13

B_A19

GND

B_A14

B_WE

B_A20

B_A21

B_A16

B_A15

B_A22

B_A23

B_A12

PCI-to-PC Card (16-Bit) Diagram

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PCI1220

FUNCTION

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

power supply

TERMINAL

NAME NO.

GND

CCA

CCB

CCI

CCP

PC Card power switch

13, 22, 44, 75, 96, 129, 153,

167, 181, 194, 207

7, 31, 64, 86, 113, 143, 164,

175, 187, 201

120 Rail power input for PC Card A interface. Indicates Card A signaling environment, 5 V or 3.3 V.

38 Rail power input for PC Card B interface. Indicates Card B signaling environment, 5 V or 3.3 V .

148 Rail power input for interrupt subsystem interface and miscellaneous I/O. (5 V or 3.3 V)

1, 178 Rail power input for PCI signaling (5 V or 3.3 V)

Device ground terminals

Power supply terminal for core logic (3.3 V)

TERMINAL

NAME NO.

CLOCK 151 I/O

DATA 152 O

LATCH 150 O

PCI system

TERMINAL

NAME NO.

PCLK 180 I

PRST

166 I

I/O

TYPE

I/O

TYPE

3–Line Power Switch Clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1220 output by using the P2CCLK bit in the System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2MHz.

If a system design defines this terminal an output, then this terminal requires an external pullup resister. The frequency of the PCI1220 output CLOCK is derived from dividing the PCI CLK by 36.

3–Line Power Switch Data. DATA is used to serially communicate socket power control information to the power switch.

3–Line Power Switch Latch. LATCH is asserted by the PCI1220 to indicate to the PC Card power switch that the data on the DATA line is valid. When a pulldown resitor is implemented on this terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface.

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1220 to place all output buffers in a high-impedance state and reset all internal registers. When PRST nonfunctional. After PRST

When the SUSPEND and PRST registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

is deasserted, the PCI1220 is in its default state.

are asserted, the device is protected from the PRST clearing the internal

FUNCTION

is asserted, the device is completely

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FUNCTION

PCI address and data

TERMINAL

NAME NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12

AD11

AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR 202 I/O

170 171 173 174 176 177 165 179 183 184 185 186 188 189 190 191 204 205 206 208 172

162 192 203

11 12 14 15

I/O

TYPE

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination

I/O

information. During the data phase, AD31–AD0 contain data.

2 3 4 6 8 9

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry

I/O

meaningful data. C/BE0 byte 2 (AD23–AD16), and C/BE3

PCI bus parity. In all PCI bus read and write cycles, the PCI1220 calculates even parity across the AD31–AD0 and C/BE3 delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator . A compare error results in the assertion of a parity error (PERR

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Terminal Functions (Continued)

–C/BE0 define the bus command. During the data phase, this

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to

applies to byte 3 (AD31–AD24).

–C/BE0 buses. As an initiator during PCI cycles, the PCI1220 outputs this parity indicator with a one-PCLK

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PCI1220

FUNCTION

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

PCI interface control

TERMINAL

NAME NO.

DEVSEL

FRAME

GNT

IDSEL 182 I

IRDY

PERR

REQ

SERR

STOP

TRDY

197 I/O

193 I/O

168 I

195 I/O

199 I/O 169 O PCI bus request. REQ is asserted by the PCI1220 to request access to the PCI bus as an initiator.

200 O

198 I/O

196 I/O

I/O

TYPE

PCI device select. The PCI1220 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1220 monitors DEVSEL occurs, the PCI1220 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1220 access to the PCI bus after the current data transaction has completed. GNT PCI bus parking algorithm.

Initialization device select. IDSEL selects the PCI1220 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY Until IRDY

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1220 when enabled through the command register indicating a system error has occurred. The PCI1220 need not be the target of the PCI cycle to assert this signal. When SERR address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY Until both IRDY

Terminal Functions (Continued)

until a target responds. If no target responds before timeout

may or may not follow a PCI bus request, depending on the

and TRDY are asserted.

and TRDY are both sampled asserted, wait states are inserted.

is enabled through bit 6 of the command register.

is enabled in the control register, this signal also pulses, indicating that an

is used for target disconnects and is commonly asserted by target devices that do not

and TRDY are asserted.

and TRDY are asserted, wait states are inserted.

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Terminal Functions (Continued)

multifunction and miscellaneous pins

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

TERMINAL

NAME NO.

MFUNC6 161 I/O Multifunction Terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ.

MFUNC5 160 I/O

MFUNC4 159 I/O

MFUNC3 158 I/O

MFUNC2 157 I/O

MFUNC1 155 I/O

MFUNC0 154 I/O

RI_OUT/PME 163 O

SUSPEND 156 I

SPKROUT 149

I/O

TYPE

FUNCTION

Multifunction Terminal 5. MFUNC5 can be configured as PC/PCI DMA Grant, GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Multifunction Terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Serial Clock (SCL). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC4 terminal provides the SCL signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset.

Multifunction Terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER.

Multifunction Terminal 2. MFUNC2 can be configured as PC/PCI DMA Request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Multifunction Terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Serial Data (SDA). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC1 terminal provides the SDA signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset.

Multifunction Terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Ring Indicate Output and Power Management Event. When configured by the PME

, this terminal is used to indicate that a power management event is occuring. If the ring indicate

function is enabled by the Suspend. SUSPEND is used to protect the internal registers from clearing when the PRST signal is

asserted.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1220 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR

//CAUDIO inputs.

Card Control Register

, the ring indicate signal is output on this terminal.

, or a parallel IRQ.

Card Control Register

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