TEXAS INSTRUMENTS PCI1220 Technical data

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PCI Bus Power Management Interface Specification 1.0 Compliant

ACPI 1.0 Compliant

Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset

Packaged in 208-Pin TQFP

PCI Local Bus Specification Revision 2.1 Compliant

1995 PC Card Standard Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards

Supports Two PC Card or CardBus Slots With Hot Insertion and Removal

Uses Serial Interface to TI TPS2202/2206 Dual-Slot PC Card Power Switch

Supports Burst Transfers to Maximize Data Throughput

Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts

Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus

Supports Up to Five General-Purpose I/Os

Programmable Output Select for CLKRUN

Multifunction PCI Device With Separate Configuration Space for Each Socket

Five PCI Memory Windows and Two I/O Windows Available for Each PC Card16 Socket

Two I/O Windows and Two Memory Windows Available to Each CardBus Socket

Exchangeable Card Architecture (ExCA) Compatible Registers Are Mapped in Memory and I/O Space

Intel 82365SL-DF Register Compatible

Supports Distributed DMA (DDMA) and PC/PCI DMA

Supports 16-Bit DMA on Both PC Card Sockets

Supports Ring Indicate, SUSPEND, PCI CLKRUN,

LED Activity Pins

Supports PCI Bus Lock (LOCK)

Advanced Submicron, Low-Power CMOS T echnology

For the Complete Data Sheet for PCI1220, Please See Literature #SCPS016

and CardBus CCLKRUN

PCI1220

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 17. . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Electrical Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 20. . . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 21. . . . . . . . . . . . . . . .

Mechanical Data 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

description

The TI PCI1220 is a high-performance PCI-to-PC Card controller that supports two independent PC Card sockets compliant with the 1995 PC Card Standard. The PCI1220 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.1, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1220 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1220 is compliant with the PCI Local Bus Specification 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions. The PCI1220 is also compliant with the latest

PCI Bus Power Management Interface Specification

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1220 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1220 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1220 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features are designed into the PCI1220, such as socket activity light-emitting diode (LED) outputs, and are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

Unused PCI1220 inputs must be pulled up using a 43 kW resistor.

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PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

system block diagram

A simplified system block diagram using the PCI1220 is provided below. The PCI950 IRQ deseralizer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability.

The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.

The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1220 that include:

Programmable multifunction terminals

SUSPEND, RI_OUT/PME (power management control signal)

SPKROUT.

PCI Bus

PCI1220

Activity LED’s

TPS22xx

Power

Switch

PC Card

Socket A

PC Card

Socket B

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed

video signals too the VGA controller.

PCI1220

68 68

IRQSER

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

INTA

INTB

Interrupt

Controller

IRQ2–15

VGA

Controller

Audio

Sub-System

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PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

terminal assignments

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30

AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17 AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

SUSPEND

GND

MFUNC0

DATA

SPKROUT

LATCH

CLOCK

A_CAD31

152

151

150

149

VCCI

148

147

MFUNC1

154

153

156

155

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

A_CAD30

A_RSVD

A_CAD29

144

146

145

A_CAD28

142

143

A_CCD2

A_CAD27

A_CLKRUN

140

139

141

A_CAUDIO

A_CSTSCHG

A_CINT

A_CSERR

136

135

138

137

A_CAD26

A_CVS1

A_CAD25

132

134

133

PCI1220 CorePCI

A_CC/BE3

A_CAD24

GND

130

129

131

A_CAD23

A_CAD22

A_CREQ

126

128

127

Card A

A_CAD21

A_CRST

124

125

A_CAD20

A_CAD19

A_CVS2

122

121

123

Card B

CCA

A_CAD18

119

120

A_CC/BE2

A_CAD17

118

117

A_CFRAME

A_CTRDY

A_CIDRY

114

113

116

115

A_CCLKVA_CDEVSEL

112

A_CGNT

111

110

A_CSTOP

A_CBLOCK

A_CPERR

108

107

109

A_RSVD

A_CPAR

105 104

103 102 101 100

51 106

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

A_CC/BE1 A_CAD16 A_CAD14 A_CAD15 A_CAD12 A_CAD13 A_CAD11 A_CAD10 GND A_CAD9 A_CC/BE0 A_CAD8 A_CAD7 A_RSVD A_CAD5 A_CAD6 A_CAD3 A_CAD4

CC A_CAD1 A_CAD2 A_CAD0 A_CCD1 B_CAD31 B_RSVD B_CAD30 B_CAD29 B_CAD28 B_CAD27 GND B_CCD2 B_CLKRUN B_CSTSCHG B_CAUDIO B_CSERR B_CINT B_CVS1 B_CAD26 B_CAD25 B_CAD24 V

CC B_CC/BE3

B_CAD23 B_CREQ B_CAD22 B_CAD21 B_CRST B_CAD20 B_CVS2 B_CAD19 B_CAD18 B_CAD17

CCP

AD10

AD9

AD8

AD7

C/BE0

AD4

AD6

AD5

AD3

AD1

AD0

AD2

GND

B_CAD0

B_CAD2

B_CCD1

B_CAD1

B_CAD4

B_CAD3

GND

B_CAD6

B_CAD5

B_CAD7

B_RSVD

B_CAD8

B_CAD9

B_CAD10

B_CC/BE0

B_CAD11

B_CAD13

B_CAD14

B_CAD12

B_CAD15

CCB

B_CAD16

B_CC/BE1

B_CPAR

B_RSVD

B_CBLOCK

GND

B_CSTOP

B_CPERR

B_CCLK

B_CGNT

B_CDEVSEL

B_CIRDY

B_CTRDY

B_CFRAME

B_CC/BE2

PCI-to-CardBus Pin Diagram

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terminal assignments (continued)

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

C/BE3

RI_OUT/PME

AD25

PRST

GND

GNT

REQ AD31 AD30 AD11 AD29 AD28

CC AD27 AD26

CCP

AD24

PCLK

GND

IDSEL

AD23 AD22 AD21 AD20

CC AD19 AD18 AD17

AD16

C/BE2

FRAME

GND IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

C/BE1

AD15 AD14 AD13

GND

AD12

A_D10

A_D2

146

147

A_D9

A_D1

144

145

143

A_D8

A_D0

142

141

A_CD2

A_WP(IOIS16)

140

139

A_BVD1(STSCHG/RI)

A_READY(IREQ)

A_WAIT

A_A0

A_VS1

A_A2

136

135

134

133

A_A1

132

131

A_BVD2(SPKR)

138

137

PCI1220 CorePCI

A_REG

GND

130

129

A_A3

A_A4

A_INPACK

126

128

127

Card A

A_A5

A_RESET

124

125

A_A6

A_A25

A_VS2

122

121

123

Card B

CCA

120

A_A7

119

A_A12

A_A24

118

117

A_A23

A_A15

116

115

A_A22

114

113

A_A16VA_A21

112

CCI

SPKROUT

GND

MFUNC0

DATA

LATCH

CLOCK

152

151

150

149

148

SUSPEND

MFUNC1

154

153

156

155

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

111

A_A20

A_WE

110

109

A_A19

A_A14

108

107

A_A18

A_A13

105

104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

51 106

A_A8 A_A17 A_A9 A_IOWR A_A11 A_IORD A_OE A_CE2 GND A_A10 A_CE1 A_D15 A_D7 A_D14 A_D6 A_D13 A_D5 A_D12

CC A_D4 A_D11 A_D3 A_CD1 B_D10 B_D2 B_D9 B_D1 B_D8 B_D0 GND B_CD2 B_WP(IOIS16) B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A0 B_A1 B_A2 V

CC B_REG B_A3 B_INPACK B_A4 B_A5 B_RESET B_A6

B_VS2 B_A25 B_A7 B_A24

CCP

AD9

AD10

AD8

AD7

C/BE0

AD6

AD5

AD3

AD1

AD2

GND

AD0

B_D3

B_CD1

B_D11

B_D4

B_D5

B_D12

GND

B_D6

B_D13

B_D7

B_D14

AD4

B_D15

B_CE1

B_A10

B_CE2

B_OE

B_IORD

B_A11

B_IOWR

B_A9

CCB

B_A17

B_A8

B_A18

B_A13

B_A19

GND

B_A14

B_WE

B_A20

B_A21

B_A16

B_A15

B_A22

B_A23

B_A12

PCI-to-PC Card (16-Bit) Diagram

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PCI1220

FUNCTION

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

power supply

TERMINAL

NAME NO.

GND

CCA

CCB

CCI

CCP

PC Card power switch

13, 22, 44, 75, 96, 129, 153,

167, 181, 194, 207

7, 31, 64, 86, 113, 143, 164,

175, 187, 201

120 Rail power input for PC Card A interface. Indicates Card A signaling environment, 5 V or 3.3 V.

38 Rail power input for PC Card B interface. Indicates Card B signaling environment, 5 V or 3.3 V .

148 Rail power input for interrupt subsystem interface and miscellaneous I/O. (5 V or 3.3 V)

1, 178 Rail power input for PCI signaling (5 V or 3.3 V)

Device ground terminals

Power supply terminal for core logic (3.3 V)

TERMINAL

NAME NO.

CLOCK 151 I/O

DATA 152 O

LATCH 150 O

PCI system

TERMINAL

NAME NO.

PCLK 180 I

PRST

166 I

I/O

TYPE

I/O

TYPE

3–Line Power Switch Clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1220 output by using the P2CCLK bit in the System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2MHz.

If a system design defines this terminal an output, then this terminal requires an external pullup resister. The frequency of the PCI1220 output CLOCK is derived from dividing the PCI CLK by 36.

3–Line Power Switch Data. DATA is used to serially communicate socket power control information to the power switch.

3–Line Power Switch Latch. LATCH is asserted by the PCI1220 to indicate to the PC Card power switch that the data on the DATA line is valid. When a pulldown resitor is implemented on this terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface.

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1220 to place all output buffers in a high-impedance state and reset all internal registers. When PRST nonfunctional. After PRST

When the SUSPEND and PRST registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

is deasserted, the PCI1220 is in its default state.

are asserted, the device is protected from the PRST clearing the internal

FUNCTION

is asserted, the device is completely

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FUNCTION

PCI address and data

TERMINAL

NAME NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12

AD11

AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR 202 I/O

170 171 173 174 176 177 165 179 183 184 185 186 188 189 190 191 204 205 206 208 172

162 192 203

11 12 14 15

I/O

TYPE

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination

I/O

information. During the data phase, AD31–AD0 contain data.

2 3 4 6 8 9

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry

I/O

meaningful data. C/BE0 byte 2 (AD23–AD16), and C/BE3

PCI bus parity. In all PCI bus read and write cycles, the PCI1220 calculates even parity across the AD31–AD0 and C/BE3 delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator . A compare error results in the assertion of a parity error (PERR

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Terminal Functions (Continued)

–C/BE0 define the bus command. During the data phase, this

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to

applies to byte 3 (AD31–AD24).

–C/BE0 buses. As an initiator during PCI cycles, the PCI1220 outputs this parity indicator with a one-PCLK

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PCI1220

FUNCTION

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

PCI interface control

TERMINAL

NAME NO.

DEVSEL

FRAME

GNT

IDSEL 182 I

IRDY

PERR

REQ

SERR

STOP

TRDY

197 I/O

193 I/O

168 I

195 I/O

199 I/O 169 O PCI bus request. REQ is asserted by the PCI1220 to request access to the PCI bus as an initiator.

200 O

198 I/O

196 I/O

I/O

TYPE

PCI device select. The PCI1220 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1220 monitors DEVSEL occurs, the PCI1220 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1220 access to the PCI bus after the current data transaction has completed. GNT PCI bus parking algorithm.

Initialization device select. IDSEL selects the PCI1220 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY Until IRDY

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1220 when enabled through the command register indicating a system error has occurred. The PCI1220 need not be the target of the PCI cycle to assert this signal. When SERR address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY Until both IRDY

Terminal Functions (Continued)

until a target responds. If no target responds before timeout

may or may not follow a PCI bus request, depending on the

and TRDY are asserted.

and TRDY are both sampled asserted, wait states are inserted.

is enabled through bit 6 of the command register.

is enabled in the control register, this signal also pulses, indicating that an

is used for target disconnects and is commonly asserted by target devices that do not

and TRDY are asserted.

and TRDY are asserted, wait states are inserted.

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Terminal Functions (Continued)

multifunction and miscellaneous pins

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

TERMINAL

NAME NO.

MFUNC6 161 I/O Multifunction Terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ.

MFUNC5 160 I/O

MFUNC4 159 I/O

MFUNC3 158 I/O

MFUNC2 157 I/O

MFUNC1 155 I/O

MFUNC0 154 I/O

RI_OUT/PME 163 O

SUSPEND 156 I

SPKROUT 149

I/O

TYPE

FUNCTION

Multifunction Terminal 5. MFUNC5 can be configured as PC/PCI DMA Grant, GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Multifunction Terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Serial Clock (SCL). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC4 terminal provides the SCL signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset.

Multifunction Terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER.

Multifunction Terminal 2. MFUNC2 can be configured as PC/PCI DMA Request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Multifunction Terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Serial Data (SDA). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC1 terminal provides the SDA signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset.

Multifunction Terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE

Ring Indicate Output and Power Management Event. When configured by the PME

, this terminal is used to indicate that a power management event is occuring. If the ring indicate

function is enabled by the Suspend. SUSPEND is used to protect the internal registers from clearing when the PRST signal is

asserted.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1220 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR

//CAUDIO inputs.

Card Control Register

, the ring indicate signal is output on this terminal.

, or a parallel IRQ.

Card Control Register

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PCI1220

FUNCTION

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Terminal Functions (Continued)

16-bit PC Card address and data (slots A and B)

TERMINAL

NO.

NAME

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal 121 is A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal 55 is B_A25.

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12

A11

A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SLOT

†

121 118 116 114

111 109 107 105 103 112 115 108 106 117 100

95 102 104 119 123 125 126 128 131 132 133

84 147 145 142

83 146 144 141

SLOT

I/O

TYPE

‡

55 53 51 49 47 45 42 40 37 48 50 43 41 52 34 29 36 39 54 57 59 60 62 65 66 67

27 25 23 20 18 81 79 77 26 24 21 19 17 80 78 76

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

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FUNCTION

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B)

TERMINAL

28 30

I/O

TYPE

‡

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost.

Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries.

BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost.

Speaker. SPKR been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1220 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1

interface status register.

see Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes.

CE1

enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.

Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address.

DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1220 to enable 16-bit I/O PC Card data output during host I/O read cycles.

DMA write. IORD that supports DMA. The PCI1220 asserts IORD memory.

I/O write. IOWR is driven low by the PCI1220 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

DMA read. IOWR that supports DMA. The PCI1220 asserts IOWR

Output enable. OE is driven low by the PCI1220 to enable 16-bit memory PC Card data output during host memory read cycles.

DMA terminal count. OE that supports DMA. The PCI1220 asserts OE

is used by 16-bit modem cards to indicate a ring detection.

is an optional binary audio signal available only when the card and socket have

and CD2 are pulled low. For signal status,

is used as the DMA write strobe during DMA operations from a 16-bit PC Card

during DMA transfers from the PC Card to host

is used as the DMA write strobe during DMA operations from a 16-bit PC Card

during transfers from host memory to the PC Card.

is used as terminal count (TC) during DMA operations to a 16-bit PC Card

to indicate TC for a DMA write operation.

NO.

NAME

BVD1

(STSCHG

BVD2

(SPKR

CD1 CD2

CE1 CE2

INPACK 127 61 I

IORD

IOWR

OE 98 32 O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal 127 is A_INP ACK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal 61 is B_INPACK

SLOT

138 72 I

/RI)

137 71 I

)

1401674

94 97

99 33 O

101 35 O

SLOT

†

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1220

FUNCTION

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B) (continued)

TERMINAL

NUMBER

NAME

READY

(IREQ

REG

RESET 124 58 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE 110 46 O

(IOIS16

VS1 VS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal 1 10 is A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal 46 is B_WE

SLOT

135 69 I

)

130 63 O

136 70 I

139 73 I

)

134 1226856

SLOT

†

I/O

TYPE

‡

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ the 16-bit I /O PC Card requires service by the host software. IREQ interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE

active). Attribute memory is a separately accessed section of card memory and is generally

IOWR used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1220 asserts REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE DMA. The PC1220 asserts WE

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16 function.

I/O is 16 bits. IOIS16 the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,

I/O

determine the operating voltage of the 16-bit PC Card.

is asserted by a 16-bit I/O PC Card to indicate to the host that a device on

or WE active) and to the I/O space (IORD or

is used as TC during DMA operations to a 16-bit PC Card that supports

to indicate TC for a DMA read operation.

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when

is high (deasserted) when no

to indicate a DMA operation. REG

)

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FUNCTION

Terminal Functions (Continued)

CardBus PC Card interface system (slots A and B)

TERMINAL

NO.

NAME

CCLK 112 48 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal 1 12 is A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal 48 is B_CCLK.

SLOT

†

139 73 O

124 58 I/O

I/O

TYPE

‡

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1220 to indicate that the CCLK frequency is going to be decreased.

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST and the PCI1220 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2:1, and

is asserted, all CardBus PC Card signals must be 3-stated,

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1220

FUNCTION

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Terminal Functions (Continued)

CardBus PC Card address and data (slots A and B)

TERMINAL

NO.

NAME

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR 106 41 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal 106 is A_CP AR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal 41 is B_CPAR.

SLOT

†

147 145 144 142 141 133 132 131 128 126 125 123 121

119

118 103 101 102

100

98 97 95 93 92 89 90 87 88 84 85 83

130

117 104

SLOT

I/O

TYPE

‡

81 79 78 77 76 67 66 65 62 60 59 57 55 54 53 37 35 36 33 34 32 30 29 27 26 23 24 20 21 18 19 17

63 52 39 28

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit

I/O

address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3 During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte

I/O

paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and CC/BE3 applies to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1220 calculates even parity across the CAD and CC/BE delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

buses. As an initiator during CardBus cycles, the PCI1220 outputs CPAR with a one-CCLK

–CC/BE0 defines the bus command.

applies to byte 0 (CAD7–CAD0), CC/BE1

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FUNCTION

I/O

CCD1

CCD2

Terminal Functions (Continued)

CardBus PC Card interface control (slots A and B)

TERMINAL

NO.

NAME

CAUDIO 137 71 I

CBLOCK

CCD1 CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 134 68 CVS2 122 56

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal 137 is A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal 71 is B_CAUDIO.

SLOT

†

107 42 I/O

82 16

140 74

111 47 I/O

116 51 I/O

110 46 I

135 69 I

115 50 I/O

108 43 I/O

127 61 I

136 70 I

109 45 I/O

138 72 I

114 49 I/O

I/O

TYPE

‡

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1220 supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and

CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.

CardBus device select. The PCI1220 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1220 monitors CDEVSEL If no target responds before timeout occurs, the PCI1220 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME

CardBus bus grant. CGNT is driven by the PCI1220 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY CTRDY

are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR pullup, and may take several CCLK periods. The PCI1220 can report CSERR assertion of SERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status, and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with voltage and card type.

and

is deasserted, the CardBus bus transaction is in the final data phase.

is driven by the card synchronous to CCLK, but deasserted by a weak

on the PCI interface.

is used for target disconnects, and is commonly asserted by target

to identify card insertion and interrogate cards to determine the operating

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

until a target responds.

and

to the system by

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

absolute maximum ratings over operating temperature ranges (unless otherwise noted)

Supply voltage range, V Supply voltage range, V Input voltage range, V

Output voltage range, V

Input clamp current, I Output clamp current, I Storage temperature range, T Virtual junction temperature, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with

respect to V measured with respect to V

2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to V measured with respect to V

instead of VCC. PC Card terminals are measured with respect to V

CCP

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CCP,

: PCI –0.5 V to V

CCA,

CCB,

–0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CCI

Card A –0.5 to V Card B –0.5 to V MISC –0.5 to V Fail safe –0.5 V to V

: PCI –0.5 V to V

Card A –0.5 to V Card B –0.5 to V MISC –0.5 to V Fail safe –0.5 V to V

(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO < 0 or VO > VCC) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

instead of VCC. PC Card terminals are measured with respect to V

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. The limit specified applies for a dc condition.

CCI

. The limit specified applies for a dc condition.

CCI

CCA

or V

. Miscellaneous signals are

CCB

or V

. Miscellaneous signals are

CCB

†

CCP CCA CCB

CCI

CC CCP CCA CCB

CCI

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI I/O

Commercial

PC Card I/O

Commercial

I/O

Commercial

PCI

VIIn ut voltage

Out ut voltage

In ut transition time

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

recommended operating conditions (see Note 3)

OPERATION MIN NOM MAX UNIT

CCP

CC(A/B)

CCI

†

NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. †

Applies to external inputs and bidirectional buffers without hysteresis

‡

Miscellaneous pins are 149, 150, 151, 152, 154, 155, 156, 157, 158, 159, 161, 163 (SUSPEND (MFUNC0–6), and power switch control pins).

Fail-safe pins are 16, 56, 68, 74, 82, 122, 134, and 140 (card detect and voltage sense pins).

Applies to external output buffers

These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.

Core voltage

voltage

scellaneous

High-level input voltage

Low-level input voltage

(tr and tf)

Operating ambient temperature range 0 25 70 °C Virtual junction temperature 0 25 115 °C

voltage

Commercial 3.3 V 3 3.3 3.6 V

3.3 V 3 3.3 3.6 5 V 4.75 5 5.25

3.3 V 0.5 V 5 V 2 V

PC Card

‡

MISC Fail safe

PC Card

MISC Fail safe PCI 0 V PC Card 0 V MISC Fail safe PCI 0 V PC Card 0 V MISC Fail safe PCI and PC Card 1 4 ZV , miscellaneous, and

fail safe

‡

3.3 V 5 V 2.4 V

3.3 V 0 0.3 V 5 V 0 0.8

3.3 V 0 5 V 0 0.8

CCP

0.475

CCA/B

2 V 2 V

0 0.8 0 0.8

0 V 0 V

0 6

, SPKROUT, RI_OUT, multifunction terminals

CCA/B CCA/B

0.325

CCA/B

CCP CCP

CCI

CCP

CCI

CCP

CCI

PCI1220

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1220

Output pi

I/O pi

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER PINS OPERATION TEST CONDITIONS MIN MAX UNIT

PCI

High-level output voltage

Low-level output voltage PC Card

OZL

OZH

†

For PCI pins, VI = V

‡

For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output.

3-state output, high-impedance state current

Low-level input current

High-level input current

. For PC Card pins, VI = V

CCP

PC Card

MISC ZV

PCI

MISC SERR

Input pins VI = GND –1 I/O pins

nput pins

Fail-safe pins 3.6 V VI = V

. For miscellaneous pins, VI = V

CC(A/B)

3.3 V 5 V

3.6 V VI = V

5.25 V VI = V

3.6 V

5.25 V

3.6 V

5.25 V

3.6 V VI = V

5.25 V VI = V

IOH = –0.5 mA 0.9 V IOH = –2 mA 2.4 IOH = –0.15 mA 0.9 V IOH = –0.15 mA 2.4 IOH = –4 mA VCC–0.6 IOH = –4 mA VCC–0.6 IOL = 1.5 mA 0.1 V IOL = 6 mA 0.55 IOL = 0.7 mA 0.1 V IOL = 0.7 mA 0.55 IOL = 4 mA 0.5 IOL = 12 mA 0.5

CC CC

CC CC CC

CCI

† †

‡ ‡

VI = V VI = V

VI = GND –10 VI = V VI = V

–1 –1 10 25

10 20 10 25

µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

gy,

50 pF

PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 1 and Figure 2)

PARAMETER

∆v/∆t Slew rate, PCLK tr, t t

Cycle time, PCLK t Pulse duration, PCLK high t Pulse duration, PCLK low t

Pulse duration, RSTIN t Setup time, PCLK active at end of RSTIN t

ALTERNATE

SYMBOL

cyc

high

low

rst

rst-clk

PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 1 thru Figure 4 and Note 4)

PARAMETER

PCLK-to-shared signal

dis

NOTES: 4. PCI shared signals are AD31–0, C/BE3–0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL , and PAR.

Propagation delay time, See Note 5

Enable time, high impedance-to-active delay time from PCLK

Disable time, active-to-high impedance delay time from PCLK

Setup time before PCLK valid t Hold time after PCLK high t

5. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time.

valid delay time PCLK-to-shared signal

invalid delay time

ALTERNATE

SYMBOL

val

inv

off su

TEST CONDITIONS MIN MAX UNIT

TEST

CONDITIONS

MIN MAX UNIT

30 ns 11 ns 11 ns

1 4 V/ns 1 ms

100

2 ns

28 ns

7 ns 0 ns

subscript A

indicates the

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PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT PARAMETERS

†

PARAMETER

dis

†

LOAD

LOAD–VOL

‡

TIMING

PZH

PZL

PHZ

PLZ

includes the typical load-circuit distributed capacitance

LOAD

(pF)

50 8 –8 50 8

= 50 Ω, where VOL = 0.6 V, IOL = 8 mA

(mA)

–8

LOAD

(V)

1.5

0 3

From Output

Under Test

‡

Test

Point

LOAD

LOAD CIRCUIT

LOAD

Timing

Input

(see Note A)

Data

Input

(see Note A)

Out-of-Phase

90% V

10% V

Input

In-Phase

Output

50% V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

INPUT RISE AND FALL TIMES

50% V

0 V

High-Level

Input

Low-Level

Input

Output

Control (low-level enabling)

Waveform 1

(see Notes

B and C)

Waveform 2

(see Notes

B and C)

50% V

VOLTAGE WAVEFORMS

PULSE DURATION

50% V

PZL

PZH

PLZ

50% V

PHZ

50% V

VOL+ 0.3 V

VOH– 0.3 V

0 V

≅ 50% V V

≅ 50% V 0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the

following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr = 6 ns.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. For t

PLZ

and t

, VOL and VOH are measured values.

PHZ

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

Figure 1. Load Circuit and Voltage Waveforms

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PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

PCI BUS PARAMETER MEASUREMENT INFORMATION

high

low

2 V MIN Peak-to-Peak

rst

PCLK

RSTIN

0.8 V

2 V

cyc

Figure 2. PCLK Timing Waveform

PCLK

PCI Output

PCI Input

srst-clk

Figure 3. RSTIN Timing Waveforms

1.5 V t

val

1.5 V

Valid

inv

off

Figure 4. Shared Signals Timing Waveforms

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PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

PC Card cycle timing

The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput.

The PC Card address setup and hold times are a function of the wait-state bits. Table 1 shows address setup time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 2 and Table 3 show command active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 4 shows address hold time in PCLK cycles and nanoseconds for I/O and memory cycles.

Table 1. PC Card Address Setup Time, t

WAIT-STATE BITS

I/O 3/90 Memory WS1 0 2/60 Memory WS1 1 4/120

Table 2. PC Card Command Active Time, t

WAIT-STATE BITS

WS ZWS

0 0 19/570

I/O

Memory

1 X 23/690

0 1 7/210 00 0 19/570 01 X 23/690 10 X 23/690 11 X 23/690 00 1 7/210

Table 3. PC Card Command Active Time, t

WAIT-STATE BITS

WS ZWS

0 0 7/210

I/O

Memory

1 X 11/330

0 1 N/A 00 0 9/270 01 X 13/390 10 X 17/510 11 X 23/630 00 1 5/150

, 8-Bit and 16-Bit PCI Cycles

su(A)

TS1 – 0 = 01

(PCLK/ns)

, 8-Bit PCI Cycles

c(A)

TS1 – 0 = 01

(PCLK/ns)

, 16-Bit PCI Cycles

c(A)

TS1 – 0 = 01

(PCLK/ns)

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PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

Table 4. PC Card Address Hold Time, t

WAIT-STATE BITS

I/O 2/60 Memory WS1 0 2/60 Memory WS1 1 3/90

, 8-Bit and 16-Bit PCI Cycles

h(A)

TS1 – 0 = 01

(PCLK/ns)

timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see Note 5 and Figure 5)

ALTERNATE

SYMBOL

NOTE 6: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle

Setup time, CE1 and CE2 before WE/OE low T1 60 ns Setup time, CA25–CA0 before WE/OE low T2 t Setup time, REG before WE/OE low T3 90 ns Propagation delay time, WE/OE low to WAIT low T4 ns Pulse duration, WE/OE low T5 200 ns Hold time, WE/OE low after WAIT high T6 ns Hold time, CE1 and CE2 after WE/OE high T7 120 ns Setup time (read), CDATA15–CDATA0 valid before OE high T8 ns Hold time (read), CDATA15–CDATA0 valid after OE high T9 0 ns Hold time, CA25–CA0 and REG after WE/OE high T10 t Setup time (write), CDATA15–CDATA0 valid before WE low T11 60 ns Hold time (write), CDATA15–CDATA0 valid after WE low T12 240 ns

type (read/write, memory/I/O) and WAIT observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.

from PC Card. The times listed here represent absolute minimums (the times that would be

su(A)

h(A)

MIN MAX UNIT

+2PCLK ns

+1PCLK ns

timing requirements over recommended ranges of supply voltage and operating free-air temperature, I/O cycles (see Figure 6)

ALTERNATE

SYMBOL

Setup time, REG before IORD/IOWR low T13 60 ns Setup time, CE1 and CE2 before IORD/IOWR low T14 60 ns Setup time, CA25–CA0 valid before IORD/IOWR low T15 t Propagation delay time, IOIS16 low after CA25–CA0 valid T16 35 ns Propagation delay time, IORD low to WAIT low T17 35 ns Pulse duration, IORD/IOWR low T18 T Hold time, IORD low after WAIT high T19 ns Hold time, REG low after IORD high T20 0 ns Hold time, CE1 and CE2 after IORD/IOWR high T21 120 ns Hold time, CA25–CA0 after IORD/IOWR high T22 t Setup time (read), CDATA15–CDATA0 valid before IORD high T23 10 ns Hold time (read), CDATA15–CDATA0 valid after IORD high T24 0 ns Setup time (write), CDATA15–CDATA0 valid before IOWR low T25 90 ns Hold time (write), CDATA15–CDATA0 valid after IOWR high T26 90 ns

su(A)

h(A)

MIN MAX UNIT

+2PCLK ns

+1PCLK ns

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PCI1220

T27

tpdP

T28

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see Figure 7)

ALTERNATE

SYMBOL

T10

MIN MAX UNIT

30 30

ropagation delay time

PC Card PARAMETER MEASUREMENT INFORMATION

CA25–CA0

REG

PARAMETER

BVD2 low to SPKROUT low BVD2 high to SPKROUT high IREQ

to IRQ15–IRQ3

STSCHG to IRQ15–IRQ3

CE1, CE2

WE, OE

WAIT

CDATA15–CDATA0

(write)

CDATA15–CDATA0

(read)

With no wait state With wait state

T11

Figure 5. PC Card Memory Cycle

T12

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PCI1220

PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

PC Card PARAMETER MEASUREMENT INFORMATION

CA25–CA0

IOIS16

REG

CE1, CE2

T16

T14

T18

T22

T20

T21

IORD, IOWR

WAIT

CDATA15–CDATA0

(write)

CDATA15–CDATA0

(read)

With no wait state With wait state

T15

BVD2

SPKROUT

IREQ

T13

T17

T25

Figure 6. PC Card I/O Cycle

T27

T28

T19

T26

T23

T24

IRQ15–IRQ3

Figure 7. Miscellaneous PC Card Delay Times

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1220 PC CARD CONTROLLER

XCPS016 – DECEMBER 1997

MECHANICAL DATA

PDV (S-PQFP-G208) PLASTIC QUAD FLATPACK

157

208

156

105

104

0,27 0,17

0,50

0,08

0,13 NOM

Gage Plane

25,50 TYP

28,05

27,95 30,10

29,90

1,45

1,35

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136

0,05 MIN

0,25

0°–7°

0,75 0,45

Seating Plane

0,08

4087729/B 06/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TEXAS INSTRUMENTS PCI1220 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual