HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
D Compliant With PCI Hot-Plug Specification,
Revision 1.0
D Supports up to Four Independently
Controlled Hot-Plug Slots
D Provides Register Accessing Through Both
Generic Parallel Bus and Two-Wire Serial
Interface
D Provides Interrupt and Event Status/Enable
State Compliant With ACPI Specification
1.0
D Provides an Automatic Bus Connection
Sequencing Feature
D Supports 66-MHz PCI Clock Frequency
D Features Two Attention Indicators With
Variable LED Blinking Rates per Slot
Table of Contents
Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 MHz PCI Support 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Control Registers 25. . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments (120-Pin) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments (128-Pin) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions 33. . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments (144-Pin) 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Interface 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Name/Pin Number Sort Table (120-Pin) 6. . . . . . . . . . . . . . . . . Electrical Characteristics 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Name/Pin Number Sort Table (128-Pin) 8. . . . . . . . . . . . . . . . . PCI Clock/Reset Timing Requirements 35. . . . . . . . . . . . . . . . . . . . . . .
Signal Name/Pin Number Sort Table (144-Pin) 10. . . . . . . . . . . . . . . . PCI Timing Requirements 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Functions 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data (120-Pin) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPC3130A Applications 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data (128-Pin) 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-Bit Implementation 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data (144-Pin) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D Provides an Easy Scheme to Cascade the
HPC3130A for Compact PCI Applications
D Provides Card Detection Mechanism
Independent of PCI Present Signals for
Advanced Card Protection
D Provides Path to Guarantee Idle State
During PCI Bus Connections
D Fabricated in Advanced Low-Power CMOS
Process
D Features a CBT Switch
†
Control Feature for
REQ64 Implementation
D Package Options:
– 120-pin QFP Package
– 128-pin LQFP Package
– 144-pin LQFP Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Contact Texas Instrument’s Bus Interface product group for information related to CBT switches.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
description
The T exas Instruments HPC3130A is a peripheral component interconnect (PCI) hot-plug controller , compliant
with
PCI Hot-Plug Specification, Revision 1.0
slots on a PCI bus, provides a 64-bit data path in any of the four hot-plug slots, and supports 66-MHz systems
for two slots.
The primary function of the HPC3130A is to allow noninterfering hot-plug slot connection/disconnection with
the other PCI devices on the bus. The HPC3130A provides automatic bus connection sequencing and supports
a protocol for connection during bus idle conditions. It also supports an interrupt pin to report hot-plug slot
events. The interrupt event status and enable state are compliant with the
Interface (ACPI) Specification
.
Internal registers may be accessed through either a two-signal serial interface or a generic parallel bus. The
serial interface slave decoding circuit supports up to eight different controllers or other serial bus devices with
the same system base. Decoding through the parallel interface supports multiple controllers with external
chip-select logic. Two double-words of configuration and control registers are provided per slot. As a result, the
HPC3130A decodes an address range of 32 bytes.
An advanced complementary metal-oxide semiconductor (CMOS) process provides low system power
consumption while operating at PCI clock rates up to 66 MHz.
. This device supports hot insertion/removal of up to four hot-plug
Advanced Configuration and Power
functional block diagram
A simplified block diagram of the HPC3130A is provided below. The block diagram illustrates the HPC3130A
functionality on a per slot basis. The SMODE chip input, not shown, is used for terminal multiplexing of the serial
and parallel bus slave interfaces.
SYSTEM INTERFACE SLOT INTERFACE
CS
RD
WR
DATA 7–0
A 4–0
SDA
SCL
ADD 6–0
SYSM66EN
INTR
PRST
IDLEREQ
IDLEGNT
FRAME
IRDY
SREQ
SGNT
PCLK
Parallel
Bus
Slave
Interface
Serial Bus
Slave I/F
Switch
Timing
Control
and
Status
Registers
Slot
Power I/F
Card
Detection
CBT-Switch
Control
and
Slot Reset
Attention
Indicators
PWRON/OFF
PWRFAULT
PWRGOOD
PRSNT1
PRSNT2
DETECT
M66EN
BUSON
REQ64ON
REQ64ON
CLKON
SLOTRST
SLOTREQ64
ATTN0
ATTN1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
terminal assignments (120-terminal package)
PBM QUAD FLAT PACKAGE
PWRON/OFF[3]
PWRFAULT[3]
GND
PWRGOOD[3]
109
110
111
112
42
41
40
39
ATTN0[3]
ATTN1[3]
M66EN[3]
DETECT0[3]
DETECT1[3]
V
CC
SLOTREQ64[3]
SLOTREQ64[2]
SLOTREQ64[1]
SLOTREQ64[0]
GND
SREQ
SGNT
PRST
V
CC5V
PCLK
GND
IDLEREQ
IDLEGNT
FRAME
IRDY
V
CCP
INTR
INTR
SYSM66EN
GND
SMODE
V
CC5V
RD/SDA
WR/SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CLKON[3]
BUSON[3]
REQ64ON[3]
GND
117
118
119
120
34
33
32
31
REQ64ON[3]
SLOTRST[3]
PRSNT2[3]
PRSNT1[3]
113
114
115
116
38
37
36
35
TOP VIEW
5V
CC
DETECT1[2]
DETECT0[2]
M66EN[2]
V
105
106
107
108
46
45
44
43
ATTN1[2]
ATTN0[2]
CLKON[2]
102
103
104
49
48
47
GND
BUSON[2]
REQ640N[2]
99
100
101
52
51
50
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
REQ64ON[2]
98
53
CC
SLOTRST[2]
PRSNT2[2]
PRSNT1[2]
PWRGOOD[2]
V
93
94
95
96
97
58
57
56
55
54
PWRFAULT[2]
PWRON/OFF[2]
91
92
59
RSVD
90
RSVD
89
DETECT1[1]
88
DETECT0[1]
87
M66EN[1]
86
V
85
84
ATTN1[1]
83
ATTN0[1]
82
CLKON[1]
81
BUSON[1]
80
REQ64ON[1]
79
GND
78
REQ64ON[1]
77
SLOTRST[1]
76
PRSNT2[1]
PRSNT1[1]
75
V
74
PWRGOOD[1]
73
PWRFAULT[1]
72
PWRON/OFF[1]
71
70
DETECT1[0]
69
DETECT0[0]
68
GND
67
M66EN[0]
66
ATTN1[0]
65
ATTN0[0]
64
CLKON[0]
63
BUSON[0]
62
RSVD
RSVD
61
60
CC
CC5V
RSVD
RSVD
CS
RSVD
CC
V
DATA7
DATA5
DATA6
GND
DATA4
DATA3
DATA2
DATA1/ADD6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5V
CC
V
A4/ADD4
DATA0/ADD5
A3/ADD3
A2/ADD2
A1/ADD1
GND
A0/ADD0
PWRFAULT[0]
PWRON/OFF[0]
CC
V
PRSNT1[0]
PRSNT2[0]
PWRGOOD[0]
SLOTRST[0]
REQ64ON[0]
REQ64ON[0]
3
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
terminal assignments (128-terminal package)
PBK LOW-PROFILE QUAD FLAT PACKAGE
NC
CLKON[3]
BUSON[3]
REQ64ON[3]
GND
REQ64ON[3]
SLOTRST[3]
PRSNT2[3]
PRSNT1[3]
GND
PWRGOOD[3]
PWRON/OFF[3]
PWRFAULT[3]
116
117
118
119
120
121
122
123
124
125
126
127
128
1
NC
CC
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
ATTN0[3]
ATTN1[3]
M66EN[3]
DETECT0[3]
DETECT1[3]
V
SLOTREQ64[3]
SLOTREQ64[2]
SLOTREQ64[1]
SLOTREQ64[0]
GND
SREQ
SGNT
PRST
V
CC5V
PCLK
GND
IDLEREQ
IDLEGNT
FRAME
IRDY
V
CCP
INTR
INTR
SYSM66EN
GND
SMODE
V
CC5V
RD/SDA
WR/SCL
TOP VIEW
5V
CC
DETECT1[2]
DETECT0[2]
M66EN[2]
47
113
48
ATTN1[2]
111
112
50
49
V
114
115
46
ATTN0[2]
CLKON[2]
GND
110
108
109
53
52
51
BUSON[2]
REQ64ON[2]
REQ64ON[2]
SLOTRST[2]
104
105
106
107
57
56
55
54
CC
PRSNT2[2]
PRSNT1[2]
PWRGOOD[2]
V
101
102
103
58
59
60
100
61
PWRFAULT[2]
PWRON/OFF[2]
NC
97
98
62
99
63
NC
96
RSVD
95
RSVD
94
DETECT1[1]
93
DETECT0[1]
92
M66EN[1]
91
V
90
89
ATTN1[1]
88
ATTN0[1]
87
CLKON[1]
86
BUSON[1]
85
REQ64ON[1]
84
GND
83
REQ64ON[1]
82
SLOTRST[1]
81
PRSNT2[1]
80
PRSNT1[1]
V
79
PWRGOOD[1]
78
77
PWRFAULT[1
76
PWRON/OFF[1]
75
DETECT1[0]
74
DETECT0[0]
73
GND
72
M66EN[0]
71
ATTN1[0]
70
ATTN0[0]
69
CLKON[0]
68
BUSON[0]
RSVD
67
66
RSVD
NC
65
64
CC
CC5V
]
5V
CC
V
A4/ADD4
DATA0/ADD5
A3/ADD3
A2/ADD2
A1/ADD1
GND
A0/ADD0
PWRFAULT[0]
PWRON/OFF[0]
CC
V
PRSNT1[0]
PRSNT2[0]
SLOTRS[0]
PWRGOOD[0]
REQ64ON[0]
NC
REQ64ON[0]
RSVD
RSVD
CS
CC
V
DATA7
DATA6
GND
DATA5
DATA4
DATA3
DATA2
NC
RSVD
DATA1/ADD6
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
terminal assignments (144-terminal package)
PGE LOW-PROFILE QUAD FLAT PACKAGE
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
TOP VIEW
PWRON/OFF
PWRFAULT[2]
PWRGOOD
PRSNT1[2]
PRSNT2[2]
SLOTRST[2]
REQ64ON
REQ64ON[2]
BUSON[2]
GND
CLKON[2]
ATTN0[2]
ATTN1[2]
M66EN[2]
DETECT0
V
CC5V
DETECT1
PWRON/OFF
PWRFAULT[3]
PWRGOOD
GND
PRSNT1
PRSNT2[3]
SLOTRST
REQ64ON
GND
REQ64ON[3]
BUSON
CLKON[3]
CC
DETECT0[1]
NC
107
106
105
DETECT1[1]
101
102
103
104
RSVD
108
109
[2]
110
NC
111
112
NC
[2]
113
114
NC
CC
NC
NC
NC
115
116
117
118
[2]
119
120
121
122
123
124
125
126
[2]
127
128
[2]
129
[3]
130
131
132
[3]
133
134
[3]
135
[3]
136
[3]
137
138
139
140
141
142
[3]
143
144
1234567891011121314151617181920212223242526272829303132333435
V
100
99
CLKON[1]
97
98
V
ATTN0[1]
ATTN1[1]
M66EN[1]
NC
NC
RSVD
GND
REQ64ON[1]
BUSON[1]
94
95
96
REQ64ON[1]
93
CC5V
V
SLOTRST[1]
PRSNT1[1]
PRSNT2[1]
89
90
91
92
PWRON/OFF[1]
DETECT0[0]
DETECT1[0]
PWRFAULT[1]
PWRGOOD[1]
84
85
86
87
88
M66EN[0]
GND
82
83
ATTN0[0]
ATTN1[0]
80
81
NC
BUSON[0]
CLKON[0]
77
78
79
NC
76
NC
RSVD
74
75
RSVD
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
REQ64ON[0]
NC
REQ64ON[0]
NC
SLOTRST[0]
NC
PRSNT2[0]
V
CC
PRSNT1[0]
PWRGOOD
PWRFAULT[0]
PWRON/OFF
GND
A0/ADD0
A1/ADD1
A2/ADD2
A3/ADD3
V
CC5V
A4/ADD4
DATA0/ADD5
DATA1/ADD6
DATA2
GND
DATA3
DATA4
DATA5
DATA6
V
CC
DATA7
CS
NC
RSVD
NC
RSVD
NC
RSVD
[0]
[0]
NC
ATTN0[3]
ATTN1[3]
NC
M66EN[3]
CC
NC
V
DETECT0[3]
DETECT1[3]
SLOTREQ64[3]
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GND
SREQ
SLOTREQ64[2]
SLOTREQ64[1]
SLOTREQ64[0]
PRST
SGNT
CC5V
V
PCLK
GND
IDLEREQ
IRDY
FRAME
IDLEGNT
CCP
V
INTR
INTR
NC
GND
SMODE
SYSM66EN
CC5V
V
NC
NC
RD/SDA
WR/SCL
5
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
signal names by terminal name
Table 1. Signals Sorted Alphabetically by Terminal Name (120-Terminal Package)
TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.
A0/ADD0 50 GND 17 RD/SDA 29
A1/ADD1 49 GND 26 REQ64ON[0] 59
A2/ADD2 48 GND 41 REQ64ON[1] 78
A3/ADD3 47 GND 51 REQ64ON[2] 98
A4/ADD4 45 GND 68 REQ64ON[3] 116
ATTN0[0] 65 GND 79 REQ64ON[0] 60
ATTN0[1] 83 GND 101 REQ64ON[1] 80
ATTN0[2] 103 GND 112 REQ64ON[2] 99
ATTN0[3] 1 GND 117 REQ64ON[3] 118
ATTN1[0] 66 IDLEGNT 19 RSVD 31
ATTN1[1] 84 IDLEREQ 18 RSVD 32
ATTN1[2] 104 INTR 24 RSVD 33
ATTN1[3] 2 INTR 23 RSVD 61
BUSON[0] 63 IRDY 21 RSVD 62
BUSON[1] 81 M66EN[0] 67 RSVD 89
BUSON[2] 100 M66EN[1] 86 RSVD 90
BUSON[3] 119 M66EN[2] 105 SGNT 13
CLKON[0] 64 M66EN[3] 3 SLOTREQ64[0] 10
CLKON[1] 82 PCLK 16 SLOTREQ64[1] 9
CLKON[2] 102 PRSNT1[0] 55 SLOTREQ64[2] 8
CLKON[3] 120 PRSNT1[1] 75 SLOTREQ64[3] 7
CS 34 PRSNT1[2] 94 SLOTRST[0] 58
DATA0/ADD5 44 PRSNT1[3] 113 SLOTRST[1] 77
DATA1/ADD6 43 PRSNT2[0] 57 SLOTRST[2] 97
DATA2 42 PRSNT2[1] 76 SLOTRST[3] 115
DATA3 40 PRSNT2[2] 96 SMODE 27
DATA4 39 PRSNT2[3] 114 SREQ 12
DATA5 38 PRST 14 SYSM66EN 25
DATA6 37 PWRFAULT[0] 53 V
DATA7 35 PWRFAULT[1] 72 V
DETECT0[0] 69 PWRFAULT[2] 92 V
DETECT0[1] 87 PWRFAULT[3] 110 V
DETECT0[2] 106 PWRGOOD[0] 54 V
DETECT0[3] 4 PWRGOOD[1] 73 V
DETECT1[0] 70 PWRGOOD[2] 93 V
DETECT1[1] 88 PWRGOOD[3] 111 V
DETECT1[2] 108 PWRON/OFF[0] 52 V
DETECT1[3] 5 PWRON/OFF[1] 71 V
FRAME 20 PWRON/OFF[2] 91 V
GND 11 PWRON/OFF[3] 109 WR/SCL 30
CC
CC
CC
CC
CC
CC5V
CC5V
CC5V
CC5V
CC5V
CCP
6
36
56
85
95
15
28
46
74
107
22
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
signal names by terminal number
Table 2. Signals Sorted Numerically by Terminal Number (120-Terminal Package)
NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME
1 ATTN0[3] 41 GND 81 BUSON[1]
2 ATTN1[3] 42 DATA2 82 CLKON[1]
3 M66EN[3] 43 DATA1/ADD6 83 ATTN0[1]
4 DETECT0[3] 44 DATA0/ADD5 84 ATTN1[1]
5 DETECT1[3] 45 A4/ADD4 85 V
6 V
7 SLOTREQ64[3] 47 A3/ADD3 87 DETECT0[1]
8 SLOTREQ64[2] 48 A2/ADD2 88 DETECT1[1]
9 SLOTREQ64[1] 49 A1/ADD1 89 RSVD
10 SLOTREQ64[0] 50 A0/ADD0 90 RSVD
11 GND 51 GND 91 PWRON/OFF[2]
12 SREQ 52 PWRON/OFF[0] 92 PWRFAULT[2]
13 SGNT 53 PWRFAULT[0] 93 PWRGOOD[2]
14 PRST 54 PWRGOOD[0] 94 PRSNT1[2]
15 V
16 PCLK 56 V
17 GND 57 PRSNT2[0] 97 SLOTRST[2]
18 IDLEREQ 58 SLOTRST[0] 98 REQ64ON[2]
19 IDLEGNT 59 REQ64ON[0] 99 REQ64ON[2]
20 FRAME 60 REQ64ON[0] 100 BUSON[2]
21 IRDY 61 RSVD 101 GND
22 V
23 INTR 63 BUSON[0] 103 ATTN0[2]
24 INTR 64 CLKON[0] 104 ATTN1[2]
25 SYSM66EN 65 ATTN0[0] 105 M66EN[2]
26 GND 66 ATTN1[0] 106 DETECT0[2]
27 SMODE 67 M66EN[0] 107 V
28 V
29 RD/SDA 69 DETECT0[0] 109 PWRON/OFF[3]
30 WR/SCL 70 DETECT1[0] 110 PWRFAULT[3]
31 RSVD 71 PWRON/OFF[1] 111 PWRGOOD[3]
32 RSVD 72 PWRFAULT[1] 112 GND
33 RSVD 73 PWRGOOD[1] 113 PRSNT1[3]
34 CS 74 V
35 DATA7 75 PRSNT1[1] 115 SLOTRST[3]
36 V
37 DATA6 77 SLOTRST[1] 117 GND
38 DATA5 78 REQ64ON[1] 118 REQ64ON[3]
39 DATA4 79 GND 119 BUSON[3]
40 DATA3 80 REQ64ON[1] 120 CLKON[3]
CC
CC5V
CCP
CC5V
CC
PCI HOT PLUG CONTROLLER
CC
46 V
55 PRSNT1[0] 95 V
62 RSVD 102 CLKON[2]
68 GND 108 DETECT1[2]
76 PRSNT2[1] 116 REQ64ON[3]
CC5V
CC
CC5V
86 M66EN[1]
CC
96 PRSNT2[2]
CC5V
114 PRSNT2[3]
HPC3130A
SCPS055 – NOVEMBER 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
signal names by terminal name
Table 3. Signals Sorted Alphabetically by Terminal Name (128-Terminal Package)
TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.
A0/ADD0 53 DETECT0[2] 113 NC 97 REQ64ON[3] 125
A1/ADD1 52 DETECT0[3] 5NC128 RSVD 34
A2/ADD2 51 DETECT1[0] 75 PCLK 17 RSVD 35
A3/ADD3 50 DETECT1[1] 93 PRSNT1[0] 58 RSVD 36
A4/ADD4 48 DETECT1[2] 115 PRSNT1[1] 80 RSVD 66
ATTN0[0] 70 DETECT1[3] 6 PRSNT1[2] 101 RSVD 67
ATTN0[1] 88 FRAME 21 PRSNT1[3] 120 RSVD 94
ATTN0[2] 110 GND 12 PRSNT2[0] 60 RSVD 95
ATTN0[3] 2 GND 18 PRSNT2[1] 81 SGNT 14
ATTN1[0] 71 GND 27 PRSNT2[2] 103 SLOTREQ64[0] 11
ATTN1[1] 89 GND 44 PRSNT2[3] 121 SLOTREQ64[1] 10
ATTN1[2] 111 GND 54 PRST 15 SLOTREQ64[2] 9
ATTN1[3] 3 GND 73 PWRFAULT[0] 56 SLOTREQ64[3] 8
BUSON[0] 68 GND 84 PWRFAULT[1] 77 SLOTRST[0] 61
BUSON[1] 86 GND 108 PWRFAULT[2] 99 SLOTRST[1] 82
BUSON[2] 107 GND 119 PWRFAULT[3] 117 SLOTRST[2] 104
BUSON[3] 126 GND 124 PWRGOOD[0] 57 SLOTRST[3] 122
CLKON[0] 69 IDLEGNT 20 PWRGOOD[1] 78 SMODE 28
CLKON[1] 87 IDLEREQ 19 PWRGOOD[2] 100 SREQ 13
CLKON[2] 109 INTR 25 PWRGOOD[3] 118 SYSM66EN 26
CLKON[3] 127 INTR 24 PWRON/OFF[0] 55 V
CS 37 IRDY 22 PWRON/OFF[1] 76 V
DATA0/ADD5 47 M66EN[0] 72 PWRON/OFF[2] 98 V
DATA1/ADD6 46 M66EN[1] 91 PWRON/OFF[3] 116 V
DATA2 45 M66EN[2] 112 RD/SDA 30 V
DATA3 43 M66EN[3] 4 REQ64ON[0] 62 V
DATA4 42 NC 1 REQ64ON[1] 83 V
DATA5 41 NC 32 REQ64ON[2] 105 V
DATA6 40 NC 33 REQ64ON[3] 123 V
DATA7 38 NC 64 REQ64ON[0] 63 V
DETECT0[0] 74 NC 65 REQ64ON[1] 85 V
DETECT0[1] 92 NC 96 REQ64ON[2] 106 WR/SCL 31
CC
CC
CC
CC
CC
CC5V
CC5V
CC5V
CC5V
CC5V
CCP
7
39
59
90
102
16
29
49
79
114
23
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
signal names by terminal number
Table 4. Signals Sorted Numerically by Terminal Number (128-Terminal Package)
NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME
1 NC 33 NC 65 NC 97 NC
2 ATTN0[3] 34 RSVD 66 RSVD 98 PWRON/OFF[2]
3 ATTN1[3] 35 RSVD 67 RSVD 99 PWRFAULT[2]
4 M66EN[3] 36 RSVD 68 BUSON[0] 100 PWRGOOD[2]
5 DETECT0[3] 37 CS 69 CLKON[0] 101 PRSNT1[2]
6 DETECT1[3] 38 DATA7 70 ATTN0[0] 102 V
7 V
8 SLOTREQ64[3] 40 DATA6 72 M66EN[0] 104 SLOTRST[2]
9 SLOTREQ64[2 41 DATA5 73 GND 105 REQ64ON[2]
10 SLOTREQ64[1] 42 DATA4 74 DETECT0[0] 106 REQ64ON[2]
11 SLOTREQ64[0] 43 DATA3 75 DETECT1[0] 107 BUSON[2]
12 GND 44 GND 76 PWRON/OFF[1] 108 GND
13 SREQ 45 DATA2 77 PWRFAULT[1] 109 CLKON[2]
14 SGNT 46 DATA1/ADD6 78 PWRGOOD[1] 110 ATTN0[2]
15 PRST 47 DATA0/ADD5 79 V
16 V
17 PCLK 49 V
18 GND 50 A3/ADD3 82 SLOTRST[1] 114 V
19 IDLEREQ 51 A2/ADD2 83 REQ64ON[1] 115 DETECT1[2]
20 IDLEGNT 52 A1/ADD1 84 GND 116 PWRON/OFF[3]
21 FRAME 53 A0/ADD0 85 REQ64ON[1] 117 PWRFAULT[3]
22 IRDY 54 GND 86 BUSON[1] 118 PWRGOOD[3]
23 V
24 INTR 56 PWRFAULT[0] 88 ATTN0[1] 120 PRSNT1[3]
25 INTR 57 PWRGOOD[0] 89 ATTN1[1] 121 PRSNT2[3
26 SYSM66EN 58 PRSNT1[0] 90 V
27 GND 59 V
28 SMODE 60 PRSNT2[0] 92 DETECT0[1] 124 GND
29 V
30 RD/SDA 62 REQ64ON[0] 94 RSVD 126 BUSON[3]
31 WR/SCL 63 REQ64ON[0] 95 RSVD 127 CLKON[3]
32 NC 64 NC 96 NC 128 NC
CC
CC5V
CCP
CC5V
39 V
48 A4/ADD4 80 PRSNT1[1] 112 M66EN[2]
55 PWRON/OFF[0] 87 CLKON[1] 119 GND
61 SLOTRST[0] 93 DETECT1[1] 125 REQ64ON[3]
CC
CC5V
CC
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
CC
71 ATTN1[0] 103 PRSNT2[2]
CC5V
81 PRSNT2[1] 113 DETECT0[2]
CC
91 M66EN[1] 123 REQ64ON[3]
111 ATTN1[2]
CC5V
122 SLOTRST[3]
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
signal names by terminal name
Table 5. Signals Sorted Alphabetically by Terminal Name (144-Terminal Package)
TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.
A0/ADD0 59 DETECT1[2] 129 NC 78 REQ64ON[3] 137
A1/ADD1 58 DETECT1[3] 8NC103 REQ64ON[0] 72
A2/ADD2 57 FRAME 23 NC 105 REQ64ON[1] 95
A3/ADD3 56 GND 14 NC 107 REQ64ON[2] 120
A4/ADD4 54 GND 20 NC 110 REQ64ON[3] 140
ATTN0[0] 80 GND 29 NC 112 RSVD 37
ATTN0[1] 98 GND 50 NC 114 RSVD 39
ATTN0[2] 124 GND 60 NC 139 RSVD 41
ATTN0[3] 1 GND 83 NC 141 RSVD 73
ATTN1[0] 81 GND 94 NC 143 RSVD 75
ATTN1[1] 99 GND 122 PCLK 19 RSVD 106
ATTN1[2] 125 GND 133 PRSNT1[0] 64 RSVD 108
ATTN1[3] 3 GND 138 PRSNT1[1] 90 SGNT 16
BUSON[0] 77 IDLEGNT 22 PRSNT1[2] 115 SLOTREQ64[0] 13
BUSON[1] 96 IDLEREQ 21 PRSNT1[3] 134 SLOTREQ64[1] 12
BUSON[2] 121 INTR 27 PRSNT2[0] 66 SLOTREQ64[2] 11
BUSON[3] 142 INTR 26 PRSNT2[1] 91 SLOTREQ64[3] 10
CLKON[0] 79 IRDY 24 PRSNT2[2] 117 SLOTRST[0] 68
CLKON[1] 97 M66EN[0] 82 PRSNT2[3] 135 SLOTRST[1] 92
CLKON[2] 123 M66EN[1] 101 PRST 17 SLOTRST[2] 118
CLKON[3] 144 M66EN[2] 126 PWRFAULT[0] 62 SLOTRST[3] 136
CS 43 M66EN[3] 5 PWRFAULT[1] 87 SMODE 30
DATA0/ADD5 53 NC 2 PWRFAULT[2] 11 1 SREQ 15
DATA1/ADD6 52 NC 4 PWRFAULT[3] 131 SYSM66EN 28
DATA2 51 NC 6 PWRGOOD[0] 63 V
DATA3 49 NC 31 PWRGOOD[1] 88 V
DATA4 48 NC 33 PWRGOOD[2] 113 V
DATA5 47 NC 35 PWRGOOD[3] 132 V
DATA6 46 NC 38 PWRON/OFF[0] 61 V
DATA7 44 NC 40 PWRON/OFF[1] 86 V
DETECT0[0] 84 NC 42 PWRON/OFF[2] 109 V
DETECT0[1] 102 NC 67 PWRON/OFF[3] 130 V
DETECT0[2] 127 NC 69 RD/SDA 34 V
DETECT0[3] 7NC71 REQ64ON[0] 70 V
DETECT1[0] 85 NC 74 REQ64ON[1] 93 V
DETECT1[1] 104 NC 76 REQ64ON[2] 119 WR/SCL 36
CC
CC
CC
CC
CC
CC5V
CC5V
CC5V
CC5V
CC5V
CCP
9
45
65
100
116
18
32
55
89
128
25
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
signal names by terminal number
Table 6. Signals Sorted Numerically by Terminal Number (144-Terminal Package)
NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME
1 ATTN0[3] 37 RSVD 73 RSVD 109 PWRON/OFF[2]
2 NC 38 NC 74 NC 110 NC
3 ATTN1[3] 39 RSVD 75 RSVD 111 PWRFAULT[2]
4 NC 40 NC 76 NC 112 NC
5 M66EN[3] 41 RSVD 77 BUSON[0] 113 PWRGOOD[2]
6 NC 42 NC 78 NC 114 NC
7 DETECT0[3] 43 CS 79 CLKON[0] 115 PRSNT1[2]
8 DETECT1[3] 44 DATA7 80 ATTN0[0] 116 V
9 V
10 SLOTREQ64[3] 46 DATA6 82 M66EN[0] 118 SLOTRST[2]
11 SLOTREQ64[2] 47 DATA5 83 GND 119 REQ64ON[2]
12 SLOTREQ64[1] 48 DATA4 84 DETECT0[0] 120 REQ64ON[2]
13 SLOTREQ64[0] 49 DATA3 85 DETECT1[0] 121 BUSON[2]
14 GND 50 GND 86 PWRON/OFF[1] 122 GND
15 SREQ 51 DATA2 87 PWRFAULT[1] 123 CLKON[2]
16 SGNT 52 DATA1/ADD6 88 PWRGOOD[1] 124 ATTN0[2]
17 PRST 53 DATA0/ADD5 89 V
18 V
19 PCLK 55 V
20 GND 56 A3/ADD3 92 SLOTRST[1] 128 V
21 IDLEREQ 57 A2/ADD2 93 REQ64ON[1] 129 DETECT1[2]
22 IDLEGNT 58 A1/ADD1 94 GND 130 PWRON/OFF[3]
23 FRAME 59 A0/ADD0 95 REQ64ON[1] 131 PWRFAULT[3]
24 IRDY 60 GND 96 BUSON[1] 132 PWRGOOD[3]
25 V
26 INTR 62 PWRFAULT[0] 98 ATTN0[1] 134 PRSNT1[3]
27 INTR 63 PWRGOOD[0] 99 ATTN1[1] 135 PRSNT2[3]
28 SYSM66EN 64 PRSNT1[0] 100 V
29 GND 65 V
30 SMODE 66 PRSNT2[0] 102 DETECT0[1] 138 GND
31 NC 67 NC 103 NC 139 NC
32 V
33 NC 69 NC 105 NC 141 NC
34 RD/SDA 70 REQ64ON[0] 106 RSVD 142 BUSON[3]
35 NC 71 NC 107 NC 143 NC
36 WR/SCL 72 REQ64ON[0] 108 RSVD 144 CLKON[3]
CC
CC5V
CCP
CC5V
45 V
54 A4/ADD4 90 PRSNT1[1] 126 M66EN[2]
61 PWRON/OFF[0] 97 CLKON[1] 133 GND
68 SLOTRST[0] 104 DETECT1[1] 140 REQ64ON[3]
CC
CC5V
CC
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
CC
81 ATTN1[0] 117 PRSNT2[2]
CC5V
91 PRSNT2[1] 127 DETECT0[2]
CC
101 M66EN[1] 137 REQ64ON[3]
125 ATTN1[2]
CC5V
136 SLOTRST[3]
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
Terminal Functions
This section describes the HPC3130A terminal functions. The terminals are grouped in tables by function.
power supply terminal functions
TERMINAL
NAME
GND 11, 17, 26, 41, 51,
V
CC
V
CC5V
V
CCP
NO.
120
68, 79, 101, 112, 117
6, 36, 56, 85, 95 7, 39, 59, 90, 102 9, 45, 65, 100, 116 I 3.3-V power supply
15, 28, 46, 74, 107 16, 29, 49, 79, 114 18, 32, 55, 89, 128 I 5-V clamp-rail voltage supply
22 23 25 I Clamp rail voltage for PCI signaling (5V or 3.3V)
12, 18, 27, 44, 54,
73, 84, 108, 119, 124
control bus interface
TERMINAL
NO.
NO.
NAME
A2/ADD2
A1/ADD1
A0/ADD0
A4/ADD4
A3/ADD3
CS 34 37 43 I
DATA1/ADD6
DATA0/ADD5434446475253
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
RD/SDA 29 30 34 I/O
WR/SCL 30 31 36 I
120
48
49
50
4547485054
35
37
38
39
40
42
128
51
52
53
38
40
41
42
43
45
NO.
144
57
58
59
56
44
46
47
48
49
51
NO.
128
83, 94, 122, 133, 138
I/O FUNCTION
Parallel bus address. These terminals are address inputs in generic parallel bus cycles and are
only used when the SMODE is input low. These lower address terminals select one of the eight
registers for read/write access.
I
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A
when the SMODE is input high.
Parallel bus address. These terminals are address inputs in generic parallel bus cycles, and are
only used when SMODE is input low. These upper address terminals select one of four hot-plug
slots supported by the HPC3130A.
I
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A
when the SMODE is input high.
Chip selection. This active low input selects the HPC3130A chip as addressed in the current
generic parallel bus cycle. This chip input is only valid if the SMODE is input low. Multiple
HPC3130A chips may exist in a system with external logic driving this signal.
Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the
SMODE is input low. The data path is used during both read and write transactions to internal
registers when the parallel control bus interface is implemented.
I/O
Serial bus address selection. These terminals indicate the full serial bus address of the
HPC3130A when the SMODE is input high.
Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the
SMODE is input low. The data path is used during both read and write transactions to internal
I/O
registers when the parallel control bus interface is implemented.
Read selection. This terminal indicates a register read cycle when the SMODE input is low and
the CS
terminal input is asserted. This is used to read an internal HPC3130A register.
Serial bus data. This terminal signals the serial bus data when the SMODE input is high. It is used
during internal register read and write transactions.
Write selection. This terminal indicates a register write cycle when the SMODE input is low and
the CS
terminal input is asserted. This input is used to write to an internal HPC3130A register.
Serial bus clock. This terminal inputs serial bus clock in when the SMODE input is high. It is used
during internal register read and write transactions.
NO.
144
14, 20, 29, 50, 60,
I/O FUNCTION
I Device ground terminals
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
system interface
TERMINAL
NO.
NAME
FRAME 20 21 23 I
IDLEGNT 19 20 22 I
IDLEREQ 18 19 21 O
INTR 24 25 27 O
INTR 23 24 26 O
IRDY 21 22 24 I
PCLK 16 17 19 I
PRST 14 15 17 I
SGNT 13 14 16 O
SMODE 27 28 30 I
SREQ 12 13 15 I
SYSM66EN 25 26 28 I/O
NO.
120
128
NO.
144
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
Terminal Functions (Continued)
I/O FUNCTION
Frame. This input and the IRDY input indicate that the PCI bus is idle. When the HPC3130A
senses the PCI bus is idle after IDLEGNT
bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented.
Idle grant. This input indicates when the PCI bus is idled by the HOST-PCI bridge after a
request is made by IDLEREQ
wired to a valid logic level if the bus idling procedure is not implemented.
Idle request. This output is driven to request the HOST-PCI bridge to idle the PCI bus before
connecting a hot-plug slot. The protocol is identical to PCI request/grant. A pullup resistor must
be implemented on this terminal if the bus idling procedure is not implemented.
System interrupt. This output provides a system interrupt. The HPC3130A can be programmed
to assert this interrupt under various conditions, which may be serviced by the hot-plug service.
Furthermore, the event status/enable state is compliant with the
result, supports ACPI control methods for switching the HPC3130A.
System interrupt. This open drain output provides a system interrupt. The HPC3130A can be
programmed to assert this interrupt under various conditions, which may be serviced by the
hot-plug. Furthermore, the event status/enable state is compliant with the
and, as a result, supports ACPI control methods for switching the HPC3130A.
Initiator ready . This and the FRAME input indicate that the PCI bus is idle. When the HPC3130A
senses the PCI bus is idle after IDLEGNT
bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented.
PCI clock input. These terminals provide the PCI clock to the HPC3130A, which uses it only for
activity indicator timing, IDLEREQ
PCI reset. This signal provides the PCI reset to the HPC3130A. After a PCI reset, the
HPC3130A resides in a state where all slots are enabled, as in a non-hot-plug system. The
HPC3130A passes PCI resets from the host to all hot-plug slots.
Secondary grant. This output provides a scheme to cascade a secondary HPC3130A device in
order to provide more than four slots. The SGNT
the IDLEGNT
the primary HPC3130A to idle the bus, the primary HPC3130A arbitrates for the bus using
IDLEREQ
indicates to the secondary HPC3130A device that it can connect to the bus.
Serial bus mode. When this input is asserted high, the internal HPC3130A registers are
accessible through the serial bus interface; otherwise, they are accessed through the generic
parallel bus interface. This input selects the control bus interface.
Secondary request. This input provides a scheme to cascade a second HPC3130A device in
order to provide more than four slots. The IDLEREQ
input to the SREQ
arbitrates for the bus by asserting its IDLEREQ
HPC3130A to assert its IDLEREQ
PCI bus frequency indicator. This signal indicates the PCI clock frequency requirements of the
hot-plug slots, and must be tied to the system PCI bus M66EN signal. The output from this
terminal only changes state after a PCI reset and is only required in a 66-MHz system.
terminal for the secondary HPC3130A. After the secondary HPC3130A requests
. Once IDLEGNT is asserted, the primary HPC3130A asserts its SGNT output. This
terminal of the primary HPC3130A. If the second HPC3130A device
. The protocol is identical to PCI request/grant. This input must be
is low, a hot-plug slot can be connected to the PCI
ACPI Specification
ACPI Specification
is low, a hot-plug slot may be connected to the PCI
/IDLEGNT protocol, and connection sequencing.
output from the primary HPC3130A is input to
from the second HPC3130A device is
output, this scheme causes the primary
. If cascading is not used, this input is pulled high.
HPC3130A
and, as a
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
slot control and status functions
TERMINAL
NAME
ATTN0[3]
ATTN0[2]
ATTN0[1]
ATTN0[0]
ATTN1[3]
ATTN1[2]
ATTN1[1]
ATTN1[0]
BUSON[3]
BUSON
[2]
[1]
BUSON
BUSON
[0]
CLKON[3]
CLKON
[2]
CLKON
[1]
CLKON
[0]
DETECT0[3]
DETECT0
DETECT0
DETECT0
DETECT1
DETECT1
DETECT1
DETECT1
M66EN[3]
M66EN[2]
M66EN[1]
M66EN[0]
PRSNT1[3]
PRSNT1
PRSNT1
PRSNT1
PRSNT2
PRSNT2
PRSNT2
PRSNT2
PWRFAULT[3]
PWRFAULT
PWRFAULT
PWRFAULT
PWRGOOD[3]
PWRGOOD
PWRGOOD
PWRGOOD
[2]
[1]
[0]
[3]
[2]
[1]
[0]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
[2]
[1]
[0]
[2]
[1]
[0]
NO.
120
1
103
83
65
2
104
84
66
119
100
81
63
120
102
82
64
4
106
87
69
5
108
88
70
3
105
86
67
113
94
75
55
114
96
76
57
110
92
72
53
111
93
73
54
NO.
128
2
110
88
70
3
111
89
71
126
107
86
68
127
109
87
69
5
113
92
74
6
115
93
75
4
112
91
72
120
101
80
58
121
103
81
60
117
99
77
56
118
100
78
57
NO.
I/O FUNCTION
144
1
124
98
80
3
125
99
81
142
121
96
77
144
123
97
79
7
127
102
84
8
129
104
85
5
126
101
82
134
115
90
64
135
117
91
66
131
111
87
62
132
113
88
63
Terminal Functions (Continued)
Attention indicators. These two outputs are provided per slot as attention indicators and can
be independently programmed to drive high, low, fast blink, and slow blink. The timer is
O
based on the PCI clock frequency and the state of SYSM66EN.
CBT switch control for PCI bus. This output controls the CBT switch that connects the
hot-plug slot to the system PCI bus. This output is only driven by the HPC3130A under
O
programmed control.
PCI clock connection control. This output is used to control the CBT switch or clock driver
that connects the hot-plug slot to the system PCI clock. This output is only driven by the
O
HPC3130A under programmed control.
Card detection signals. These two card detect input signals, DETECT0 and DETECT1, are
provided as additional card detection signals to the PRSNT1
present input must be tied to ground to indicate a card is present per the
these optional inputs are provided for designers of a more mechanically robust system. If the
protection enable bit is set to 1 in the general configuration register, the HPC3130A does not
I
power a hot-plug slot unless DETECT0
implementing additional card detection must tie these signals to ground. When this feature is
utilized, the HPC3130A guarantees that power can not be applied to an empty slot or a slot
with a partially inserted card.
PCI bus frequency indicator. This signal indicates the PCI clock frequency requirements of
the hot-plug slots and is only required in a 66-MHz system (two slot maximum electrical
I
loading limits). The two slot interfaces that provide the M66EN terminals are sensed at PCI
reset and are driven afterwards.
Present signals. These inputs are provided by hot-plug slots to indicate that an add-in card is
physically present in the slot and to power requirements to the system. Only one of these
I
signals must be tied to ground to indicate a card is present in an expansion slot. A set of
PRSNT1
Power fault. This input is provided per slot power switch to indicate if there is a power fault.
The HPC3130A can be programmed to generate an interrupt through INTR
I
is asserted.
Power good. This input is provided per slot power switch to indicate when power is
successfully switched. The HPC3130A can be programmed to generate an interrupt through
I
INTR
and PRSNT2 inputs are provided for each hot-plug slot.
when this input is asserted.
and DETECT1 are input low. A design not
and PRSNT2. Since only one
PCI Specification
when this input
,
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
slot control and status functions (continued)
TERMINAL
NAME
PWRON/OFF[3]
PWRON/OFF
PWRON/OFF
PWRON/OFF
REQ64ON[3]
REQ64ON
REQ64ON
REQ64ON
REQ64ON[3]
REQ64ON[2]
REQ64ON[1]
REQ64ON[0]
SLOTREQ64[3]
SLOTREQ64
SLOTREQ64
SLOTREQ64
SLOTRST[3]
SLOTRST
SLOTRST
SLOTRST
[2]
[1]
[0]
[2]
[1]
[0]
[2]
[1]
[0]
[2]
[1]
[0]
NO.
120
109
91
71
52
116
98
78
59
118
99
80
60
7
8
9
10
115
97
77
58
NO.
128
116
98
76
55
123
105
83
62
125
106
85
63
8
9
10
11
122
104
82
61
NO.
144
130
109
137
119
140
120
136
118
I/O FUNCTION
Power ON/OFF . This output is provided per slot and is driven to the power switch to control
O
86
61
93
70
95
72
10
11
12
13
92
68
the slot power state.
CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace
loading of the additional REQ64
O
can be used to control the CBT switch. This output is only driven by the HPC3130A under
programmed control.
CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace
loading of the additional REQ64
O
can be used to control the CBT switch. This output is only driven by the HPC3130A under
programmed control.
Slot request 64. This output is driven in conjunction with SLOTRST to the hot-plug slot to
indicate to option cards whether or not they are plugged into a 64-bit slot. If a 64-bit device
is plugged into a 32-bit slot, then it must ensure that its high-word path inputs do not
O
oscillate and that there is not a significant power drain through the input buffer. This output
is only driven by the HPC3130A under programmed control.
Slot PCI reset. This output is driven to the hot-plug slot to reset it after power up. When a
card is inserted into a hot-plug slot it must be reset independent of the other PCI devices on
O
the bus. This output is only driven by the HPC3130A under programmed control.
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
signal inherent to the HPC3130A controller. This output
signal inherent to the HPC3130A controller. This output
HPC3130A applications
This section discusses the various features of the HPC3130A in detail, and presents design considerations
including a general connection sequencing guideline.
system implementation
Figure 1 illustrates the HPC3130A implementation. The PCI bus signals are switched to the hot–plug PCI slot
by the BUSON output, which controls a CBT switch. The PCI clock, PCI reset, M66EN, and REQ64 must not
be routed through the CBT switch. The HPC3130A drives the slot PCI reset and SLOTREQ64
controlled by internal HPC3130A registers. The SLOTREQ64 requires special consideration during reset, as
described. The PCI clock to the slot is driven by a clock driver, which is enabled by the HPC3130A CLKON
output.
The HPC3130A also provides other features such as mechanical detection circuits, attention indicators, and
interrupt signaling. The mechanical detection circuitry using the DETECT[1,0] inputs is displayed as a dotted
line and is an optional feature. Two attention indicator outputs, ATTN[1,0], are provided: one indicator to draw
the attention of the user to a particular slot for insertion/removal, and one optional indicator that can be used
to indicate fault conditions. Additional features, such as 66-MHz capability and automatic sequencing, are
discussed in the following sections.
, which can be
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
HOST/PCI
8–BIT
PORT
PCLK
PRST
SYSM66EN
PCI Bus
PCI Bus Less PRST
BUSON CBT–SW
Motherboard
PCI Device
and REQ64
INTR
HPC–PCI
IDLEREQ
IDLEGNT
FRAME
IRDY
CLKON
REQ64ON
SLOTREQ64
PWRON/OFF
PERFAULT
PWRGOOD
DETECT(0–1)
ATTN(0–1)
M66EN
PRSNT
SLOTRST
CBT–SW
CBT–SW
(1–2)
PWR–SW
P
C
I
S
L
O
T
Figure 1. HPC3130A Implementation
The HPC3130A internal registers can be accessed through either a two-wire serial interface or an 8-bit generic
parallel bus (ISA-like). The above figure illustrates the 8-bit port configuration. Not shown in the diagram is the
SMODE chip input that must be wired low to indicate parallel bus interface mode. Also not shown in the diagram
is the external chip-select logic required to select the HPC3130A in ISA bus cycles.
serial interface
The internal registers can be accessed either through a two-wire serial interface or through an 8-bit generic
parallel interface. The SMODE input selects one of these modes.
The HPC3130A implements a two-pin serial slave interface with one clock signal (SCL) and one data signal
(SDA). This serial interface can operate with a serial clock frequency up to 400 kHz. Both SCL and SDA require
pullup resistors for the serial slave interface to function properly.
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a ST AR T
condition (S) when the SDA line transitions to a low state while SCL is in a high state as illustrated in Figure 2.
The end of a requested data transfer is indicated by a STOP condition (P), which is the low-to-high transition
of SDA while SCL is in the high state. Data on SDA must remain stable during the high state of the SCL signal.
Changes on the SDA signal during the high state of SCL will be interpreted as control signals, that is, a ST ART
or STOP condition.
The SCL is an input into the HPC3130A and SDA is bidirectional.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SDA
SCL
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
Start Condition Stop Condition
Data Line Stable, Data Valid
Change of
Data Allowed
Figure 2. Serial Bus Start/Stop Conditions and Bit Transfers
Data is transferred on the bus in 8-bit bytes. The number of bytes that can be transmitted during a data transfer
is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is
indicated by the receiver pulling down the SDA signal so that it remains low during the high state of the SCL
signal as shown in Figure 3.
SCL From
Master
SDA Output
By Transmitter
SDA Output
By Receiver
123 789
Figure 3. Serial Bus Protocol – Acknowledge
The HPC3130A serial bus slave interface protocol for write transactions is illustrated in Figure 4. The R/W
command bit is set to zero to indicate a write transaction. For a write operation, the HPC3130A requires a word
address field after the slave address. This address field is comprised of eight bits. Upon receipt of the word
address, the HPC3130A responds with an acknowledge, and waits for the next eight bits of data, again
responding with an acknowledge. After all the data bytes are transferred, the master then terminates the transfer
by generating a STOP condition. The device automatically increments the address for subsequent data words.
After the receipt of each word, the low order address bits are internally incremented by one.
Slave Address Word Address
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
R/W
S/P = Start/stop conditionA = Slave acknowledgment
b7 b6 b4b5 b3 b2 b1 b0 A P
Data Byte
Figure 4. Serial Bus Protocol – Byte Write
A byte read operation is illustrated in Figure 5. The read protocol is very similar to the write protocol, except the
R/W
command bit must be set to one to indicate a read data transfer. First the master issues a write command
that includes the START condition and the slave address field (with the R/W bit set to write), followed by the
address of the word it is to read. This procedure sets the internal address counter of the HPC3130A to the
desired address. After the word address acknowledgment is received by the master, the master immediately
reissues a ST ART condition followed by another slave address field with the R/W bit set to read. The HPC3130A
responds with an acknowledgment and transmits the eight data bits stored in the addressed location. If the
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HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
master responds with an acknowledge signal, indicating that it requires additional data, the HPC3130A
continues to output data for each received acknowledge signal. The master terminates the sequential read
operation by not responding with an acknowledge signal, and issues a STOP condition.
Slave Address Word Address
R/W
M = Master acknowledgment
Slave Address
b6 b4b5 b3 b2 b1 b0 1 A
S b6 b4b5 b3 b2 b1 b0 M Pb6 b4b5 b3 b2 b1 b0 M P
Restart StopStart
R/W
S/P = Start/stop conditionA = Slave acknowledgment
Data Byte
b7Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Figure 5. Serial Bus Protocol – Byte Read
parallel interface
The HPC3130A also implements an 8-bit parallel interface mode. When this mode is selected, the HPC3130A
internal register addressed by the A[4:0] inputs can be accessed for a read/write transaction using the CS, RD,
WR strobes. The following signals have pullups on the mother board: IO16, M16, NOWS, CHRDY, MEMR,
MEMW
, IOR, IOW, SD[15:0] to implement default states. Figure 6 shows write access using the default 8-bit
standard ISA bus cycle with four wait states. A read cycle is similar.
BCLK
CS
WR
A(0–4)
D(0–7)
Figure 6. Parallel Bus Write Cycle
connection sequencing
Before an add-in card is hot plugged and made available to the slot, the various pins in the HPC3130A have
to be controlled in a specific sequence. The HPC3130A provides the software interface to sequence the power
to the slot, clocks, and signals to the add-in cards that are being live inserted. The switch-timing block is used
to control the exact timing when the CBT switches are enabled.
The initial software sequencing is done by setting individual bits in the hot plug control register in the following
sequence. First, the SL TPWR_CTL bit is set high to drive the PWRON/OFF signal high. After the power to the
slot is applied, the SLOTRST_O bit is set low to drive the SLOTRST output. Next the CLKON_O bit is set low
to enable the PCI clock to the slot. Also, the REQ64_O bit is set to a value of 0 and the SLOTREQ64 bit is set
to indicate to the add-in card whether it is inserted into a 64-bit or 32-bit slot. SLOTREQ64 is set low for a 64-bit
slot and is set high for a 32-bit slot.
After initial software sequencing of the above signals is complete, the next step is to enable the CBT switches.
This can be done either by using the software to manually set the BUS_CTL bit or using the HPC3130A via the
automatic connection sequence mode located in the general configuration register.
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HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
connection sequencing (continued)
If automatic sequencing mode 1 is selected, then the BUS_CTL bit controls the sequencing by using idling
protocol. When this bit is set to zero, the switch–timing block will arbitrate for the PCI bus by asserting IDLEREQ
Subsequently , IDLEGNT
are deasserted, the CBT switches are enabled. Following this, the SLOTRST , SLOTREQ64 and REQ64ON are
deasserted. Figure 7 depicts the sequencing of events when automatic sequencing mode 1 is enabled.
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
IDLEREQ
is asserted and the HPC3130A waits for bus idle condition. When FRAME and IRDY
.
IDLEGNT
FRAME
IRDY
BUSON
Figure 7. Automatic Connection Sequencing Mode 1
If automatic sequencing mode 2 is selected, then the BUS_CTL bit controls the sequencing by using idling
protocol. When this bit is set to zero, the switch timing block arbitrates for the PCI bus by asserting IDLEREQ.
Subsequently, IDLEGNT is asserted and the HPC3130A waits for the bus idle condition. When FRAME and
IRDY are deasserted, the SLOTRST is deasserted. Following this, the SLOTREQ64 and REQ64ON are
deasserted and the CBT switches are enabled. Figure 8 depicts the sequencing of events when automatic
sequencing mode 2 is enabled.
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HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
connection sequencing (continued)
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
IDLEREQ
IDLEGNT
FRAME
IRDY
BUSON
Figure 8. Automatic Connection Sequencing Mode 2
The protocol described above is identical to the PCI REQ
/GNT protocol used by PCI bus masters, which also
must wait for bus idle through PCI FRAME and IRDY before initiating a PCI cycle. If the HPC3130A is connected
to PCI FRAME and IRDY , the HPC3130A arbitrates for the bus; although it does not drive the PCI bus or assert
FRAME to start a cycle.
There are some issues with this implementation such as bus parking and additional loading on the PCI FRAME
and IRDY signals, which need to be considered when designing a system. The system designer may have a
level of confidence that PCI adapter cards can tolerate connection to a non-idle bus. In the scenario where the
HPC3130A is not connected to the bus, then the FRAME, IRDY , and IDLEGNT must be wired to valid logic levels
and the automatic sequencing will start without any relationship to the bus.
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connection sequencing (continued)
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
IDLEREQ
, IDLEGNT , FRAME, and IRDY pins are not connected in manual mode. In contrast, during automatic
connection, the HPC3130A requests the PCIBus to make sure it is idle before it sequences through the
connection sequence.
In manual mode, software has to perform each part of the connection sequence. Figure 9 is an example of the
manual connection sequence. There could be several other ways to implement this protocol.
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
BUSON
Figure 9. Manual Connection Sequencing
disconnecting sequence
The HPC3130A provides two mechanisms to isolate a PCI slot from the PCI bus so an add–in card can be
removed. One of the mechanisms is called manual sequencing and is enabled by default. This mechanism
allows the software to control the entire disconnect sequence. This means it is the software’s responsibility to
remove a powered slot from the PCI bus without any impact to the system.
The second mechanism is called autosequencing and can be enabled by programming either Auto-Sequence
1 or Auto-Sequence 2 in the general configuration register. Unlike the connection sequence, which has two
different autoconnection sequencing modes, the autodisconnect sequence has only one mode of operation.
The steps in the autodisconnect sequence are as follows:
1. Software may assert SLOTRST to the appropriate slot by writing a 0 to the SLOTRST_O bit in the hot-plug
control register. This is optional.
2. Next the software must set the BUS_CTL bit in the hot-plug control register to a 1.
3. Once the BUS_CTL bit is set to a 1, the HPC3130A asserts IDLEREQ.
4. Once IDLEGNT is asserted and FRAME and IRDY are deasserted, the HPC3130A deasserts BUSON and
CLKON and asserts REQ64ON to isolate the slot from the PCI bus.
5. The HPC3130A then drives PWRON/OFF
low to power off the slot.
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HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
disconnecting sequence (continued)
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
IDLEREQ
IDLEGNT
FRAME
IRDY
BUSON
Figure 10. Automatic Disconnect Sequencing Mode
In manual disconnect mode, software has to perform each part of the disconnection sequence. Figure 1 1 is an
example of the manual disconnection sequence. There could be several other ways to implement this protocol.
During manual disconnection, the PCI bus may or may not idle; it will depend on the software implementation
of the system.
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
BUSON
22
Figure 11. Manual Disconnect Sequencing Mode
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64-bit implementation
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
When inserted into a slot, a 64-bit PCI card tests whether that slot is 64-bit or 32-bit. If REQ64
is low when
PCI_RST is deasserted, that signals the card that the slot is 64-bit; otherwise, the slot is 32-bit. The HPC3130A
provides a mechanism to notify the PCI card it is connected to a 64-bit PCI slot. The mechanism uses REQ64ON
and REQ64ON
as CBT switch enables and SLOTREQ64 as the slot specific REQ64 signal. As depicted in
figures 12 and 13, REQ64ON enables the CBT switch that routes SLOTREQ64 to the slot, and REQ64ON
enables the CBT switch that routes SYSTEMREQ64 to the slot. SYSTEMREQ64 will always be routed to the
slot except when the slot is disconnected from the bus or during a connection sequence. It is very important
during a connection sequence that the software clears bit 3 in the
hot plug control register
to drive SLOTREQ64
low. The HPC3130A will deassert SLOTREQ64 during the automatic connection sequence.
In a 32-bit PCI bus implementation, the SLOTREQ64, REQ64ON, and REQ64ON outputs are not connected.
BUSON
HPC_PCI
System PCI Bus
REQ64ON
SYSTEMREQ64
REQ64ON
SLOTREQ64
PCI
SLOT
CBT3306
Figure 12. SLOTREQ64 Implementation Using CBT3306
BUSON
HPC_PCI
SYSTEMREQ64
SLOTREQ64
REQ64ON
System PCI Bus
S OE
CBT3257
Figure 13. SLOTREQ64 Implementation Using CBT3257
PCI
SLOT
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HPC3130A
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66-MHz PCI support
The HPC3130A supports up to two slots in a 66-MHz system: slot 0 and slot 1. These hot-plug slot interfaces
include the M66EN signal and the SYSM66EN signal communicates hot-plug slot capability to the system.
Figure 14 illustrates the 66-MHz support function in the HPC3130A.
HPC–PCI M66EN FUNCTION
CLKON 0 PRST
33 MHz
66 MHz
P
C
CO
SYSM66EN
System PCI Bus
Motherboard
PCI Device
M66EN_I
CB1G1257
M66EN_0
PCI
SLOT
PCLK DRIVER
Figure 14. HPC3130A 66-MHz System Support
When the PCIRST signal is deasserted, the SYSM66EN signal is latched and selects the system frequency.
Before an adapter card can be inserted, the slot is prepared for insertion by deasserting BUSON, deasserting
CLKON, and powering down the slot. When an adapter card is inserted into either hot-plug slot 0 or slot 1,
PWRON/OFF is high, and power is applied, the value M66EN from the card can be read through internal
registers. If the bus is operating at 66-MHz and a 33-MHz adapter card is inserted, then the software ensures
that the card is never connected to the bus. If the bus is operating at 33 MHz and a 66-MHz adapter card is
inserted, then the latched SYSM66EN state can be driven to the slot by enabling the CBT switch using CLKON
SYSM66EN and CLKON
input to a clock driver circuit to control the PCI clock frequency . The 66-MHz support
designed into the HPC3130A allows option cards to indicate PCI clock frequency capabilities upon PCI reset;
however, does not allow an inserted hot-plug card to alter the clock frequency of an operating PCI bus.
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.
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers
The HPC3130A register set is accessible through either a generic parallel bus interface or a two-wire serial
interface. Eight bytes of register space are provided per slot. Since the HPC3130A supports four slots, a total
of 32 bytes of registers is implemented. Register and bit descriptions are provided in the following sections and
indicate the bits that are common to all slots. The bit default values are given, which represent the state of the
HPC3130A after a PCI reset event. After a PCI reset, the HPC3130A drives outputs to a state such that the slots
appear as if they were not a hot-plug platform.
The register map that follows provides the register overview. Byte addressing is required when accessing the
internal registers. Read transactions from reserved registers return zeros.
Table 7. Register Map
SLOT REGISTER NAME ADDRESS SLOT REGISTER NAME ADDRESS
Slot 0 General configuration register 0x00 Slot 2 General configuration register 0x10
Slot 0 Hot-plug slot status register 0x01 Slot 2 Hot-plug slot status register 0x1 1
Slot 0 Hot-plug slot control register 0x02 Slot 2 Hot-plug slot control register 0x12
Slot 0 Attention indicator control 0x03 Slot 2 Attention indicator control 0x13
Slot 0 Reserved 0x04 Slot 2 Reserved 0x14
Slot 0 Reserved 0x05 Slot 2 Reserved 0x15
Slot 0 Interrupt event status register 0x06 Slot 2 Interrupt event status register 0x16
Slot 0 Interrupt event enable register 0x07 Slot 2 Interrupt event enable register 0x17
Slot 1 General configuration register 0x08 Slot 3 General configuration register 0x18
Slot 1 Hot-plug slot status register 0x09 Slot 3 Hot-plug slot status register 0x19
Slot 1 Hot-plug slot control register 0x0A Slot 3 Hot-plug slot control register 0x1A
Slot 1 Attention indicator control 0x0B Slot 3 Attention indicator control 0x1B
Slot 1 Reserved 0x0C Slot 3 Reserved 0x1C
Slot 1 Reserved 0x0D Slot 3 Reserved 0x1D
Slot 1 Interrupt event status register 0x0E Slot 3 Interrupt event status register 0x1E
Slot 1 Interrupt event enable register 0x0F Slot 3 Interrupt event enable register 0x1F
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HPC3130A
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SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
general configuration register
Bit 7 6 5 4 3 2 1 0
Name General configuration register
Type R R R R R/W R/W R R/W
Default 0 0 1 1 0 0 X 0
Register: General configuration
Type: Read-only, Read/Write
Offset: 00h (slot 0), 08h (slot 1), 10h (slot 2), 18h (slot 3)
Default: 0Xh
Description: This register is for general configurations and indications. The automatic PCI bus
connection sequencing is enabled through this register, and the register access mode is
indicated. This register is shared among all four slots.
Table 8. General Configuration Register
BIT TYPE NAME FUNCTION
7–4 R RSVD Reserved for revision ID. These bits return 0011b for this device.
Automatic PCI bus connection sequencing. These bits control the sequencing used to connect the hotplug slot to the PCI bus.
3–2 R/W SEQUENCING
1 R SYSM66STAT
0 R/W PROTECTEN
00 = Manual sequencing through register accesses
01 = Auto–Sequence 1: Enable CBT switches before deasserting RST
10 = Auto–Sequence 2: Enable CBT switches after deasserting RST
11 = Reserved
Status of SYSM66EN. This bit represents the latched value of SYSM66EN during a PCI reset. A value of
1 indicates the PCI bus is operating at a frequency greater than 33 MHz. A value of 0 indicates the PCI
bus is operating at 33 MHz or less.
Protection enable. This bit enables a protection mechanism provided by the HPC3130A. When this bit is
enabled and either of the DETECT[1:0]
outputs high. The HPC3130A also drives PWRON/OFF and REQ64ON outputs low.
inputs are high, the HPC3130A drives the BUS_ON and CLKON
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PCI HOT PLUG CONTROLLER
configuration and control registers (continued)
hot-plug slot status register
Bit 7 6 5 4 3 2 1 0
Name Hot-plug slot status register
Type R R R R R R R R
Default X X X X X X X X
Register: Hot-plug slot status
Type: Read-only
Offset: 01h (slot 0), 09h (slot 1), 11h (slot 2), 19h (slot 3)
Default: XXh
Description: This register reports card detection, power status, and other chip input from the hot-plug
slot interface. All bits in this register are read only, and the data read from each bit
represents the logical value of the data input from the corresponding terminal.
Table 9. Hot-Plug Slot Status Register
BIT TYPE NAME FUNCTION
7 R BUSON Bus on. This bit returns the logical value of the BUSON terminal output.
6 R M66EN_I M66EN input. This bit returns the logical value of the M66EN terminal input.
5 R PWRGOOD_I Power good input. This bit returns the logical value of the PWRGOOD terminal input.
4 R PWRFAULT_I Power fault input. This bit returns the logical value of the PWRFAULT terminal input.
3 R DETECT1_I Mech detect 1 input. This bit returns the logical value of the DETECT1 terminal input.
2 R DETECT0_I Mech detect 0 input. This bit returns the logical value of the DETECT0 terminal input.
1 R PRSNT2_I Card present 2 input. This bit returns the logical value of the PRSNT2 terminal input.
0 R PRSNT1_I Card present 1 input. This bit returns the logical value of the PRSNT1 terminal input.
HPC3130A
SCPS055 – NOVEMBER 1999
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27
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
hot-plug slot control register
Bit 7 6 5 4 3 2 1 0
Name Hot-plug slot control register
Type R R R/W R/W R/W R/W R/W R/W
Default 0 0 1 0 1 1 0 1
Register: Hot-plug slot control
Type: Read-only, Read/Write
Offset: 02 (slot 0), 0Ah (slot 1), 12h (slot 2), 1Ah (slot 3)
Default: 2Dh
Description: This register applies power, resets, and provides general control of a hot-plug slot
connection to the system PCI bus.
Table 10. Hot-Plug Slot Control Register
BIT TYPE NAME FUNCTION
7 R RSVD Reserved. This bit returns 0 when read.
6 R RSVD Reserved. This bit returns 0 when read.
Slot power On/Off control. The data written to this bit represents the logical value of the data to drive the
5 R/W SLTPWR_CTL
4 R/W BUS_CTL
3 R/W SLOTREQ64
2 R/W REQ64_O
1 R/W CLKON_O
0 R/W SLOTRST_O
PWRON/OFF
general configuration register is set to 1, then a logic high can only be driven by the PWRON/OFF
the DETECT[1:0]
PCI bus CBT-switch control. When manual sequencing is enabled, then the value written to this bit
represents the logical value of the data driven to the BUSON
hot-plug slot to/from the PCI bus.
If an auto sequencing mode is enabled in the general configuration register, then this bit functions as follows:
1 = By setting this bit, the hot-plug slot gets disconnected from the PCI bus. This is accomplished by
0 = By clearing this bit, the hot-plug slot gets connected to the PCI bus. This is accomplished by asserting
Slot request 64-bit control. The data written to this bit represents the logical value of the data driven to the
SLOTREQ64
card whether or not it is connected to a 64-bit slot.
REQ64 CBT switch control. The data written to this bit represents the logical value of the data driven to the
REQ64ON
CLKON CBT switch control. The data written to this bit represents the logical value of the data driven to the
CLKON
Slot reset control. The data written to this bit represents the logical value of the data driven to the SLOTRST
output and is used to reset a hot-plug slot after power is applied.
output and is used to control the power state of a hot-plug slot. If the PROTECTEN bit in the
inputs are low.
output, and it is used to connect/disconnect a
asserting IDLEREQ
before driving BUSON high, CLKON high, REQ64ON low, and PWRON/OFF low.
IDLEREQ
BUSON
general configuration register.
output and is used to control the clock driver to the hot-plug slot.
, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY before driving
low. Also verifies assertion of DETECT[1:0] if the protection enable bit is enabled in the
output and is used during reset of a slot after power is applied. This input indicates to an option
output and is used to control the CBT switch that implements the REQ64 PCI signal.
, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY
output if
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PCI HOT PLUG CONTROLLER
configuration and control registers (continued)
attention indicator control register
Bit 7 6 5 4 3 2 1 0
Name Attention indicator control register
Type R R R R R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Register: Attention indicator control
Type: Read-only, Read/Write
Offset: 03 (slot 0), 0Bh (slot 1), 13h (slot 2), 1Bh (slot 3)
Default: 00h
Description: This register controls the attention indicators. The timing for the indicators is based upon
the PCI clock and the M66EN input.
Table 11. Attention Indicator Control Register
BIT TYPE NAME FUNCTION
7 R RSVD Reserved. This bit returns 0 when read.
6 R RSVD Reserved. This bit returns 0 when read.
5 R RSVD Reserved. This bit returns 0 when read.
4 R RSVD Reserved. This bit returns 0 when read.
Attention indicator 1 control. These bits control the state of A TTN1 per slot and are programmed as follows:
00 = Drive low
3–2 R/W ATTN1_CTL
1–0 R/W ATTN0_CTL
01 = Slow blink – 1 cycle per second
10 = Fast blink – 2 cycles per second
11 = Drive high
Attention indicator 0 control. These bits control the state of A TTN0 per slot and are programmed as follows:
00 = Drive low
01 = Slow blink – 1 cycle per second
10 = Fast blink – 2 cycles per second
11 = Drive high
HPC3130A
SCPS055 – NOVEMBER 1999
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29
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
interrupt event status register
Bit 7 6 5 4 3 2 1 0
Name Interrupt event status register
Type R R/C R/C R/C R/C R/C R/C R/C
Default 0 0 0 0 0 0 0 0
Register: Interrupt event status
Type: Read-only, Read/Clear
Offset: 06h (slot 0), 0Eh (slot 1), 16h (slot 2), 1Eh (slot 3)
Default: 00h
Description: This register reads interrupt status, and clears the interrupt. All functional bits in this
register are readable and cleared by a write back of 1. The HPC3130A can be programmed
to generate an interrupt, signaled through the open-drain INTR
events. Each event is individually enabled through the interrupt event enable register.
Table 12. Interrupt Event Status Register
BIT TYPE NAME FUNCTION
7 R RSVD Reserved. This bit returns 0 when read.
6 R/C BUS_S
5 R/C PWRGOOD_S Power good status. This bit is set when the PWRGOOD input changes state.
4 R/C PWRFAULT_S Power fault status. This bit is set when the PWRFAULT input is asserted.
3 R/C DETECT1_S Mechanical detect 1 status. This bit is set when the DETECT1 input changes state.
2 R/C DETECT0_S Mechanical detect 0 status. This bit is set when the DETECT0 input changes state.
1 R/C PRSNT2_S Card present 2 status. This bit is set when the PRSNT2 input changes state.
0 R/C PRSNT1_S Card present 1 status. This bit is set when the PRSNT1 input changes state.
PCI Bus CBT switch status. This bit is set when the BUSON output changes state, and is cleared by a
write back of 1. The BUS event is intended for use with the idling protocol.
, after detecting various
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
interrupt event enable register
Bit 7 6 5 4 3 2 1 0
Name Interrupt event enable register
Type R R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Register: Interrupt event enable
Type: Read-only, Read/Write
Offset: 07h (slot 0), 0Fh (slot 1), 17h (slot 2), 1Fh (slot 3)
Default: 00h
Description: This register is used to enable interrupts, signaled through the open-drain INTR, after
detecting various events. Event status is reported through the interrupt event status
register.
Table 13. Interrupt Event Enable Register
BIT TYPE NAME FUNCTION
7 R RSVD Reserved. This bit returns 0 when read.
6 R/W BUS_E
5 R/W PWRGOOD_E
4 R/W PWRFAULT_E Power fault event enable. When this bit is set, an INTR is signaled when PWRF AUL T input is asserted.
3 R/W DETECT1_E Mechanical detect 1 event enable. Enables INTR events on DETECT1 input state changes.
2 R/W DETECT0_E Mechanical detect 0 event enable. Enables INTR events on DETECT0 input state changes.
1 R/W PRSNT2_E Card present 2 event enable. Enables INTR events on PRSNT2 input state changes.
0 R/W PRSNT1_E Card present 1 event enable. Enables INTR events on PRSNT1 input state changes.
PCI bus CBT switch event enable. When this bit is set, an INTR is signaled when the BUSON output
changes state. The BUS event is intended for use with the idling protocol.
Power good event enable. When this bit is set, an INTR is signaled when the PWRGOOD input changes
state.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
31
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range,VCC –0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
and V
CCP
Input voltage range, VI: PCI –0.5 V to V
SLOT –0.5 V to V
BUSON –0.5 V to V
Parallel –0.5 V to V
Parallel/serial –0.5 V to V
Miscellaneous –0.5 V to V
Output voltage range, VO: PCI –0.5 V to V
SLOT –0.5 V to V
BUSON –0.5 V to V
Parallel –0.5 V to V
Parallel/serial –0.5 V to V
Miscellaneous –0.5 V to V
Input clamp current, IIK (V
Output clamp current, I
< 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(VO < 0 or VO > VCC) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC5V
CCP
CC5V
CC5V
CC5V
CC5V
CC5V
CCP
CC5V
CC5V
CC5V
CC5V
CC5V
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction temperature, TJ 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies to external input and bidirectional buffers. For 5-V tolerant use VI > V
2. Applies to external output and bidirectional buffers. For 5-V tolerant use VO > V
. For universal PCI, use VI > V
CC5V
. For universal PCI, use VO > V
CC5V
CCP
.
CCP
.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI HOT PLUG CONTROLLER
†
ttIn ut transition time (t
r
and tf) (10% to 90%)
ns
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
CCP
V
CC5V
V
CC5V
V
CC5V
V
CC5V
V
I
V
O
V
IH
V
II
t
t
T
A
T
J
†
Applies to external output buffers.
‡
These junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature.
Core voltage Commercial 3 3.3 3.6 V
PCI I/O voltage Commercial 3 5 5.5 V
Slot I/O voltage Commercial 3 5 5.5 V
Parallel I/O voltage Commercial 3 5 5.5 V
Serial I/O voltage Commercial 3 5 5.5 V
Miscellaneous I/O voltage Commercial 3 5 5.5 V
PCI 0 V
Slot 0 V
Input voltage
Output voltage
High-level input voltage
Low-level input voltage
Input transition time (tr and tf) (10% to 90%)
Operating ambient temperature range 0 25 70 °C
Virtual junction temperature
‡
BUSON 0 V
Parallel
Parallel/Serial 0 V
Miscellaneous 0 V
PCI 0 V
Slot 0 V
BUSON 0 V
Parallel 0 V
Parallel/Serial 0 V
Miscellaneous 0 V
PCI 2 V
Slot 2 V
BUSON 2 V
Parallel
Parallel/Serial 2 V
Miscellaneous 2 V
PCI 0 0.8
Slot 0 0.8
BUSON 0
Parallel
Parallel/Serial 0
Miscellaneous 0
PCI 0 6
Slot 0 6
BUSON
Parallel/Serial 0 6
Miscellaneous 0 6
0 V
2 V
0 0.8
0 6
0 25 115 °C
HPC3130A
SCPS055 – NOVEMBER 1999
CCP
CC5V
CC5V
CC5V
CC5V
CC5V
CC
CC
CC
CC
CC
CC
CCP
CC5V
CC5V
CC5V
CC5V
CC5V
0.8
0.8
0.8
V
V
V
V
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
33
HPC3130A
VOHHigh level out ut voltage
V
VOLLow level out ut voltage
V
†
‡
†
‡
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
serial bus interface
STANDARD MODE FAST MODE
MIN MAX MIN MAX
V
V
Low-level input voltage
IL
High-level input voltage
IH
V
V
related:
CC5V
related:00.7 V
CC5V
Fixed:
Fixed:
–0.5
–0.5
CC5V
0.3 V
V
CC5V max
V
CC5V max
1.5
CC5V
+ 0.5
+ 0.530.7 V
–0.5
–0.5
CC5V
0.3 V
V
CC5V max
V
CC5V max
1.5
CC5V
+ 0.5
+ 0.5
electrical characteristics over recommended operating conditions
PARAMETER PINS OPERATION TEST CONDITIONS MIN MAX UNIT
PCIh
§
Slot
¶
V
†
Specifications apply only when pullup terminator is turned off.
‡
For I/O pins, the imput leakage current includes the off state output current IOZ.
High-level output voltage
OH
V
Low-level output voltage
OL
I
Low-level input current
IL
I
High-level input current
IH
High-impedance-state output
I
OZ
current
BUSON
#
Parallel
Parallel/Serial
Miscellaneousk IOH = –8mA VCC – 0.6
PCIh
§
Slot
BUSON
Parallel
Parallel/Serial
Miscellaneousk IOL = 2mA 0.5
PCIh VI = GND –20
§
Slot
BUSON
Parallel
Parallel/Serial
Miscellaneousk VI = GND –20
PCIh VI = V
§
Slot
BUSON
Parallel
Parallel/Serial
Miscellaneousk VI = V
||
¶
#
||
¶
#
||
¶
#
||
3.3 V IOH = –0.5 mA 0.9 V
5 V IOH = –2 mA VCC – 0.6
IOH = –8mA VCC – 0.6
IOH = –8mA VCC – 0.6
IOH = –4mA VCC – 0.6
IOH = –4mA VCC – 0.6
3.3 V IOL = 1.5 mA 0.1 V
5 V IOL = 6 mA 0.55
IOL = 8mA 0.5
IOL = 8mA 0.5
IOL = 4mA 0.5
IOL = 4mA 0.5
VI = GND –20
VI = GND –20
VI = GND –20
VI = GND –20
CC
VI = V
CC
VI = V
CC
VI = V
CC
VI = V
CC
CC
VI = VCC or GND ±20 µA
hPCI terminals: 120 PBM — 12, 13, 14, 16, 18, 19, 20, 21, 23, 24, 25, 27. 128 PBK — 13, 14, 15, 17, 19, 20, 21, 22, 24, 25, 26, 28. 144 PGE —
15, 16, 17, 19, 21, 22, 23, 24, 26, 27, 28, 30.
§
Slot terminals: 120 PBM — 7, 8, 9, 10, 58, 77, 97, 115. 128 PBK — 8, 9, 10, 11, 61, 82, 104, 122. 144 PGE — 10, 11, 12, 13, 68, 92, 1 18, 136.
¶
BUSON terminals: 120 PBM — 63, 81, 100, 119. 128 PBK — 68, 86, 107, 126. 144 PGE — 77, 96, 121, 142
#
Parallel terminals: 120 PBM — 35, 37, 38, 39, 40, 42. 128 PBK — 38, 40, 41, 42, 43, 45. 144 PGE — 44, 46, 47, 48, 49, 51
||
Parallel/serial terminals: 120 PBM — 43, 44, 45, 47, 48, 49, 50. 128 PBK — 46, 47, 48, 50, 51, 52, 53. 144 PGE — 52, 53, 54, 56, 57, 58, 59.
k Miscellaneous terminals: All terminals other than PCI, slot, BUSON, parallel, and parallel/serial.
CC
20
20
20
20
20
20
UNIT
V
V
V
CC
V
µA
µA
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
PCI clock/reset timing requirements over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
t
c
t
wH
t
wL
dv/dt PCLK slew rate tr,
t
w
t
su
PCLK cycle time t
PCLK high time t
PCLK low time t
RSTIN pulse width t
PCLK active time at end of RSTIN t
Pin definitions for 120-pin PBM package
PARAMETER PIN NUMBER
PCI 14, 16, 18, 19, 20, 21, 25, 27
Slot
BUSON 63, 81, 100, 119
Parallel 34, 35, 37, 38, 39, 40, 42
Parallel/serial 23, 24, 29, 30, 43, 44, 45, 47, 48, 49, 50
Miscellaneous 12, 13
ALTERNATE
SYMBOL
cyc
high
low
tf
rst
rst–clk
1, 2, 3, 4, 5, 7, 8, 9, 10, 52, 53, 54, 55, 57, 58, 59, 60, 64, 65, 66, 67, 69,
70, 71, 72, 73, 75, 76, 77, 78, 80, 82, 83, 84, 86, 87, 88, 91, 92, 93, 94,
96, 97, 98, 99, 102, 103, 104, 105, 106, 108, 109, 110, 111, 113, 114,
115, 116, 118, 120
TEST CONDITIONS MIN MAX UNITS
15 ns
6 ns
6 ns
1.5 4 V/ns
1 ms
100 ms
Pin definitions for 128-pin PBK package
PARAMETER PIN NUMBER
PCI 15, 17, 19, 20, 21, 22, 26, 28,
2, 3, 4, 5, 6, 8, 9, 10, 11, 55, 56, 57, 58, 60, 61, 62, 63, 69, 70, 71, 72,
Slot
BUSON 68, 86, 107, 126
Parallel 37, 38, 40, 41, 42, 43, 45,
Parallel/serial 24, 25, 30, 31, 46, 47, 48, 50, 51, 52, 53
Miscellaneous 13, 14
74, 75, 76, 77, 78, 80, 81, 82, 83, 85, 87, 88, 89, 91, 92, 93, 98, 99, 100,
101, 103, 104, 105, 106, 109, 110, 111, 112, 113, 115, 116, 117, 118,
120, 121, 122, 123, 125, 127
Pin definitions for 144-pin PGE package
PARAMETER PIN NUMBER
PCI 17, 19, 21, 22, 23, 24, 28, 30
1, 3, 5, 7, 8, 10, 11, 12, 13, 61, 62, 63, 64, 66, 68, 70, 72, 79, 80, 81, 82,
Slot
BUSON 77, 96, 121, 142
Parallel 43, 44, 46, 47, 48, 49, 51
Parallel/serial 26, 27, 34, 36, 52, 53, 54, 56, 57, 58, 59
Miscellaneous 15, 16
84, 85, 86, 87, 88, 90, 91, 92, 93, 95, 97, 98, 99, 101, 102, 104, 109,
111, 113, 115, 117, 118, 119, 120, 123, 124, 125, 126, 127, 129, 130,
131, 132, 134, 135, 136, 137, 140, 144
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
35
HPC3130A
UNIT
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
PCI timing requirements over recommended ranges of supply voltage and operating free–air
temperature
t
Propagation delay time
pd
t
Enable time, high-impedance-to-active delay time from PCLK t
en
t
Disable time, active-to-high-impedance delay time from PCLK t
dis
t
Valid setup time, before PCLK t
su
t
Hold time, after PCLK high t
h
†
Applies to external output buffers.
NOTES: 3. This data sheet uses the following conventions to describe time ( t ) intervals. The format is: tA, where subscript A indicates the type
serial bus interface
f
SCL
t
BUF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
R
t
F
t
FSU;STO
†
All values refer to serial bus interface VIH
NOTES: 5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
†
(see Note 3)
PARAMETER
PCLK to shared signal valid delay
time
of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time,
and th = hold time.
4. PCI shared signals are AD31–AD0, C/BE3–C/BE0, PCIFRAME, PCITRDY, PCIIRDY, PCISTOP, IDSEL, PCIDEVSEL, and
PCIPAR.
ALTERNATE
SYMBOL
t
val
on
off
su
h
TEST CONDITIONS MIN MAX UNITS
CL = 50 pF,
See Note 4,
1,2,3
3,4 3 ns
4 0 ns
2 11 ns
2 ns
28 ns
†
STANDARD
MODE
MIN MAX MIN MAX
SCL clock frequency (see Note 5) 0 100 0 400 kHz
Bus free time between a STOP and ST ART condition 4.7 1.3 µs
Hold time (repeated) ST ART condition. After this period, the first clock pulse is
generated.
LOW period of the SCL clock 4.7 1.3 µs
HIGH period of the SCL clock 4 0.6 µs
Setup time for a repeated STAR T condition 4.7 0.6 µs
Data hold time (see Note 6)
Data setup time (see Note 7) 250 100
Rise time of both SDA and SCL signals 1000 20 300 µs
Fall time of both SDA and SCL signals 300 20 300 µs
Setup time for STOP condition 4 0.6 µs
and VIL
MIN
to bridge the undefined region of the falling edge of SCL.
6. The maximum t
7. A fast mode serial bus device can be used in a standard mode serial bus system, but the requirement t
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR
(according to the
has only to be met if the device does not stretch the LOW period (t
HD;DAT
Standard Mode Serial Bus Specification
MAX
For CBUS compatible masters: 5
For serial bus devices:
levels
) before the SCL line is released.
4 0.6 µs
0
1
LOW
+ t
MAX
FAST MODE
010.9
3
of the SCL signal) in order
MIN
) of the SDL signal.
SU;DAT
>
SU;DAT
250 ns must then
= 1000 + 250 = 1250 ns
UNIT
µs
2
µs
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
MECHANICAL DATA
PBM (S-PQFP-G***) PLASTIC QUAD FLATPACK
120-PIN SHOWN
91
120
3,60
3,20
90
61
60
0,45
0,30
0,80
31
1
A
28,20
SQ
27,80
31,45
SQ
30,95
30
0,25 MIN
NO. OF
PINS***
120QFP
0,20
1,03
0,73
A
23,20 TYP
M
0,16 NOM
Gage Plane
0,25
0°–ā7°
4,10 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Seating Plane
0,10
4040023/D 06/96
37
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
MECHANICAL DATA
PBK (S-PQFP-G128) PLASTIC QUAD FLATPACK
128-PIN SHOWN
97
128
0,40
96
1
12,40 TYP
14,20
SQ
13,80
16,20
SQ
15,80
0,23
0,13
65
32
0,07
64
33
M
0,05 MIN
NO. OF
PINS***
128 LQFP 24,80 TYP
Gage Plane
0,25
A
0,13 NOM
0°–ā7°
1,45
1,35
1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
0,75
0,45
Seating Plane
0,08
4040279-3/C 11/96
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
MECHANICAL DATA
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK
144-PIN SHOWN
109
144
1,45
1,35
108
73
72
0,27
0,17
0,50
37
1
17,50 TYP
20,20
SQ
19,80
22,20
SQ
21,80
36
0,05 MIN
0,08
0,25
0,75
0,45
M
0,13 NOM
Gage Plane
0°–ā7°
1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Seating Plane
0,08
4040147/C 11/96
39
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
IMPORTANT NOTICE
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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