Texas Instruments CD74FCT573SM96, CD74FCT573SM, CD74FCT573M96, CD74FCT573M, CD74FCT573E Datasheet

8-1

Data sheet acquired from Harris Semiconductor
SCHS260A

Features

• Buffered Inputs

• Typical Propagation Delay: 3.9ns at V

CC

= 5V,

T

A

= 25oC, CL = 50pF (CD74FCT573AT)

• SCR Latchup Resistant BiCMOS Process and
Circuit Design

• FCTXXX Types

- Speed of Bipolar FAST™/AS/S

• FCTXXXAT Types

- 30% Faster than FAST™/AS/S with Significantly

Reduced Power Consumption

• 48mA Output Sink Current

• Output Voltage Swing Limited to 3.7V at V

CC

= 5V

• Controlled Output Edge Rates

• Input/Output Isolation to V

CC

• BiCMOS Technology with Low Quiescent Power

Description

The CD74FCT573 and CD74FCT573AT octal transparent
latches use a small geometry BiCMOS technology. The out­put stage is a combination of bipolar and CMOS transistors
that limits the output HIGH level to two diode drops below
V

CC

. This resultant lowering of output swing (0V to 3.7V)
reduces power bus ringing (a source of EMI) and minimizes
V

CC

bounce and ground bounce and their effects during
simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking
48 milliamperes.

The CD74FCT573 and CD74FCT573AT outputs are trans­parent to the inputs when the Latch Enable (

LE) is HIGH.

When the Latch Enable (

LE) goes LOW,thedataislatched.

The Output Enable (

OE) controls the three-state outputs.

When the Output Enable (

OE) is HIGH, the outputs are in
the high impedance state. The latch operation is indepen­dent of the state of the Output Enable.

Ordering Information

Pinout

PART NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74FCT573ATE 0 to 70 20 Ld PDIP E20.3
CD74FCT573M 0 to 70 20 Ld SOIC M20.3
CD74FCT573SM 0 to 70 20 Ld SSOP M20.209

NOTE: When ordering the suffix M and SM packages, use the entire
part number.Add the suffix 96 to obtain the variant in the tape and reel.

CD74FCT573, CD74FCT573AT

(PDIP, SOIC, SSOP)

TOP VIEW

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

OE

D0
D1
D2
D3
D4

D6

D5

D7

GND

V

CC

Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE

Q0

January 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1997

CD74FCT573,

CD74FCT573AT

BiCMOS FCT Interface Logic,

Octal Transparent Latches, Three-State

NOT RECOMMENDED

FOR NEW DESIGNS

Use CMOS Technology

File Number 2304.2

CD74FCT573AT was not acquired from Harris Semiconductor.

8-2

Functional Diagram

IEC Logic Symbol

TRUTH TABLE (Note 1)

OUTPUT
ENABLE

LATCH

ENABLE DATA OUTPUT

LHHH
LHLL
LLlL
LLhH
HXXZ

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level
l = Low voltage level one set up time prior to the high to low latch enable transition.
h = High voltage level one set up time prior to the high to low latch enable transition.
X = Irrelevant
Z = High Impedance

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

D0

D1

D2

D3

D4

D5

D6

D7

11

GND = PIN 10
V

CC

= PIN 20

1

LE

OE

12

CD74FCT573, CD74FCT573AT

19
18
17
16

EN

1

2

3

4
5

15
14
13
12

6

7

8
9

C1

11

1D

CD74FCT573, CD74FCT573AT

8-3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . -20mA

DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA

DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA

DC Output Source Current per Output Pin, IO. . . . . . . . . . . . -30mA

DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140mA

DC Ground Current (I

GND

). . . . . . . . . . . . . . . . . . . . . . . . . . .400mA

Operating Conditions

Operating Temperature Range (TA) . . . . . . . . . . . . . . . .0oC to 70oC

Supply Voltage Range, VCC. . . . . . . . . . . . . . . . . . . .4.75V to 5.25V

DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V

CC

DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V

CC

Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC and SSOP-Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Commercial Temperature Range 0

o

C to 70oC, VCC Max = 5.25V, VCC Min = 4.75V (Note 5)

PARAMETER SYMBOL

TEST CONDITIONS

V

CC

(V)

AMBIENT TEMPERATURE (TA)

UNITS

25oC0

o

C TO 70oC

VI (V) IO (mA) MIN MAX MIN MAX

High Level Input Voltage V

IH

4.75 to 5.25 2 - 2 - V

Low Level Input Voltage V

IL

4.75 to 5.25 - 0.8 - 0.8 V

High Level Output Voltage V

OH

VIH or V

IL

-15 Min 2.4 - 2.4 - V

Low Level Output Voltage V

OL

VIH or V

IL

48 Min - 0.55 - 0.55 V

High Level Input Current I

IH

V

CC

Max - 0.1 - 1 µA

Low Level Input Current I

IL

GND Max - -0.1 - -1 µA

Three-State Leakage Current I

OZH

V

CC

Max - 0.5 - 10 µA

I

OZL

GND Max - -0.5 - -10 µA

Input Clamp Voltage V

IK

VCC or

GND

-18 Min - -1.2 - -1.2 V

Short Circuit Output Current
(Note 3)

I

OS

VO = 0
VCC or

GND

Max -60 - -60 - mA

Quiescent Supply Current,
MSI

I

CC

VCC or

GND

0 Max - 8 - 80 µA

Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load

∆I

CC

3.4V

(Note 4)

Max - 1.6 - 1.6 mA

NOTES:

3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.

4. Inputs that are not measured are at VCC or GND.

5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICClimit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC.

CD74FCT573, CD74FCT573AT