SUMMIT S93WD662P-2.7, S93WD662P-2.7T, S93WD662P-A, S93WD662P-AT, S93WD662P-B Datasheet

SUMMIT

MICROELECTRONICS, Inc. S93WD662/S93WD663

Precision Supply-Voltage Monitor and Reset Controller

With a Watchdog Timer and 4k-bit Microwire Memory

FEATURES

•Precision Monitor & RESET Controller

—RESET and RESET# Outputs

—Guaranteed RESET Assertion to VCC = 1V

—200ms Reset Pulse Width

—Internal 1.26V Reference with ±1% Accuracy

—ZERO External Components Required

•Watchdog Timer

—Nominal 1.6 Second Time-out Period

—Reset by Any Transition of CS

•Memory

—4K-bit Microwire Memory

—S93WD662

–Internally Ties ORG Low

–100% Compatible With all 8-bit Implementations

–Sixteen Byte Page Write Capability

—S93WD663

–Internally Ties ORG High

–100% Compatible With all 16-bit Implementations

–Eight Word Page Write Capability

OVERVIEW

The S93WD662 and S93WD663 are precision power supervisory circuits providing both active high and active low reset outputs. Both devices incorporate a watchdog timer with a nominal time-out value of 1.6 seconds.

Both devices have 4k-bits of E2PROM memory that is accessible via the industry standard microwire bus. The S93WD662 is configured with an internal ORG pin tied low providing a 8-bit byte organization and the S93WD663 is configured with an internal ORG pin tied high providing a 16-bit word organization. Both the S93WD662 and S93WD663 have page write capability. The devices are designed for a minimum 100,000 program/erase cycles and have data retention in excess of 100 years.

BLOCK DIAGRAM

VCC

8

5kHz

RESET

6

RESET#

PULSE

OSCILLATOR

GENERATOR

+

VTRIP

RESET

–

CONTROL

7

RESET

1.26V

WATCHDOG

CS

1

TIMER

SK

2

MODE

ADDRESS

WRITE

DI

3

DECODE

DECODER

CONTROL

DATA I/O

E2PROM

MEMORY

ARRAY

5

GND

2013 T BD 2.0

SUMMIT MICROELECTRONICS, Inc.

•

300 Orchard City Drive, Suite 131

• Campbell, CA 95008

• Telephone [phone]

•

Fax [phone]

•

www.summitmicro.com

© SUMMIT MICROELECTRONICS, Inc. 2000		Characteristics subject to change without notice
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S93WD662/S93WD663

PIN CONFIGURATION

8-Pin PDIP or 8-Pin SOIC

CS				1	8		VCC
SK				2	7		RESET
DI				3	6		RESET#
DO				4	5		GND

2014 T PCon 2.0

PIN FUNCTIONS

Pin Name	Function
CS	Chip Select
SK	Clock Input
DI	Serial Data Input
DO	Serial Data Output
VCC	+2.7 to 6.0V Power Supply
GND	Ground
RESET/RESET#	RESET I/O

DEVICE OPERATION

APPLICATIONS

The S93WD662/WD663 is ideal for applications requiring low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable.

RESET CONTROLLER DESCRIPTION

The S93WD662/WD663 provides a precision reset controller that ensures correct system operation during brownout and power-up/-down conditions. It is configured with two open drain reset outputs: pin 7 is an active high output and pin 6 is an active low output.

During power-up, the reset outputs remain active until VCC reaches the VTRIP threshold. The outputs will continue to be driven for approximately 200ms after reach-

ing VTRIP. The reset outputs will be valid so long as VCC is ≥ 1.0V. During power-down, the reset outputs will

begin driving active when VCC falls below VTRIP.

The reset pins are I/Os; therefore, the S93WD662/ WD663 can act as a stabilization circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset time-out after detecting a low to high transition and the RESET# input will initiate a reset time-out after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/reset extender circuit.

It should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET#) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET#) and pulled down (RESET). If the signals are not being used the pins may be left unconnected.

WATCHDOG TIMER DESCRIPTION

The S93WD662/WD663 has a watchdog timer with a nominal time-out period of 1.6 seconds. Whenever the

watchdog times out, it will generate a reset output to both pins 6 and 7. The watchdog timer is reset by any transition on CS.

The watchdog timer will be held in a reset state during power-on while VCC is less than VTRIP. Once VCC exceeds VTRIP the watchdog will continue to be held in a reset state for the tPURST period. After tPURST it will be released and the timer will begin operation. If either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either tPURST has expired or the reset input is released, whichever is longer.

GENERAL OPERATION

The S93WD662/WD663 is a 4096-bit nonvolatile memory intended for use with industry standard microprocessors. The S93WD663 is organized as X16, seven 11-bit instructions control the reading, writing and erase operations of the device. The S93WD662 is organized as X8, seven 12-bit instructions control the reading, writing and erase operations of the device. The device operates on a single 3V or 5V supply and will generate on chip, the high voltage required during any write operation.

Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation.

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S93WD662/S93WD663

The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. See the Applications Aid section for detailed use of the ready busy status.

The format for all instructions is: one start bit; two op code bits and either eight (x16) or nine (x8) address or instruction bits.

Read

Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the S93WD662/ WD663 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (MSB first). The output

data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1).

Write

After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start automatic erase and write cycle to the memory location specified in the instruction. The ready/busy status of the S93WD662/WD663 can be determined by selecting the device and polling the DO pin.

Erase

Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the auto erase cycle of the selected memory location. The ready/busy status of the S93WD662/WD663 can be

	tSKHI	t SKLOW	t CSH
SK
	tDIS		tDIH
DI	VALID		VALID
	tCSS
CS
		t DIS	tPD0,t PD1	tCSMIN
DO			DATA VALID
	Figure 1. Sychronous Data Timing			2013 ILL 3 1.0

SK
								tCS
CS
								STANDBY
			AN	AN–1	A0
DI	1	1	0
					tPD0			tHZ
DO			HIGH-Z					HIGH-Z
					0
					DN	DN–1	D1	D0
								2013 ILL4 1.0
				Figure 2. Read Instruction Timing
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S93WD662/S93WD663

determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state.

Erase/Write Enable and Disable

The S93WD662/WD663 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all S93WD662/WD663 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status.

Erase All

Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of 250ns

(tCSMIN). The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the S93WD662/WD663 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the S93WD662/WD663 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.

Page Write

93WD662 - Assume WEN has been issued. The host will then take CS high, and begin clocking in the start bit, write command and 9-bit byte address immediately followed by the first byte of data to be written. The host can then continue clocking in 8-bit bytes of data with each byte to be written to the next higher address. Internally the address pointer is incremented after receiving each group of eight clocks; however, once the address counter reaches x xxxx 1111 it will roll over to x xxxx 0000 with the next clock. After the last bit is clocked in no internal write operation will occur until CS is brought low.

93WD663 - Assume WEN has been issued. The host will then take CS high, and begin clocking in the start bit, write command and 8-bit byte address immediately followed by the first 16-bit word of data to be written. The host can then continue clocking in 16-bit words of data with each word to be written to the next higher

address. Internally the address pointer is incremented after receiving each group of sixteen clocks; however, once the address counter reaches xxxx x111 it will roll over to xxxx x000 with the next clock. After the last bit is clocked in no internal write operation will occur until CS is brought low.

Continuous Read

This begins just like a standard read with the host issuing a read instruction and clocking out the data byte [word]. If the host then keeps CS high and continues generating clocks on SK, the S93WD662/ WD663 will output data from the next higher address location. The S93WD662/WD663 will continue incrementing the address and outputting data so long as CS stays high. If the highest address is reached, the address counter will roll over to address 0000. . CS going low will reset the instruction register and any subsequent read must be initiated in the normal manner of issuing the command and address.

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						S93WD662/S93WD663
SK
							tCS
CS							STATUS	STANDBY
							VERIFY
			AN	AN-1	A0 DN	D0
DI	1	0	1
				HIGH-Z		tSV	BUSY	tHZ
DO							READY
								HIGH-Z
							tEW
								2013 ILL 5 1.0
				Figure 3. Write Instruction Timing
SK
CS							STATUS VERIFY	STANDBY
			AN	AN-1	A0		tCS
DI	1	1	1

tSV

tHZ

HIGH-Z

DO

BUSY READY

HIGH-Z tEW

2013 ILL6 1.0

Figure 4. Erase Instruction Timing

SK
CS					STANDBY
DI	1	0	0	*
			* ENABLE=1		1
			DISABLE=00		2013 ILL 7 1.0
				Figure 5. EWEN/EWDS Instruction Timing
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					5