SUMMIT |
SMP9210, -11, -12 |
MICROELECTRONICS, Inc. |
Dual 10-Bit Nonvolatile DAC
Preliminary
FEATURES
!Two 10-Bit Nonvolatile DACs
"INL ±1LSB
"DNL ±1LSB
!Programmable Configuration
!Programmable Power On Reset Options
"Recall Full Scale Value
"Recall Zero Scale Value
"Recall Mid-Scale Value
"Recall NV Register Value
!Tandem or Independent Operation of DACs
!Programmable Power Down Mode (Short VOUT to GND or Float VOUT)
!I2C Interface
!Low Noise Outputs
!2.7V to 5.5V Operation
!–40ºC to 85ºC Temperature Range
APPLICATIONS
! ATE Set and Forget Calibration |
! RFPA Biasing |
! Laser Biasing |
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SIMPLIFIED APPLICATION DRAWING |
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I2C
IN+
IN–
GND
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SMP9210 |
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VOUT1 |
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3.3V |
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MONITOR |
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DIODE |
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LASER |
MODMON |
APCSET |
CC |
DIODE |
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MD |
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Laser Driver |
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RDAMP |
MODSET |
BIASSET |
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IMOD |
APC |
IBIAS |
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VOUT1 |
VOUT2 |
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RFILT |
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CAPC |
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1nF |
SMP9210 |
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2048 SAD
©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378-6586 • www.summitmicro.com
Characteristics subject to change without notice |
2048 3.3 10/03/01 |
1 |
SMP9210, SMP9211, SMP9212
Preliminary
INTRODUCTION
The SMP9210, -11, -12 trio are serial input, voltage output, dual 10-Bit digital to analog converters. They can operate from a single 2.7V to 5.5V supply. Internal precision buffers swing rail-to-rail with an input reference range from ground to the positive supply.
They integrate two 10-Bit DACs and their associated circuits: an enhanced unity gain operational amplifier
output, a 10-Bit volatile data latch, a 10-bit nonvolatile data register and an industry standard 2-wire serial interface.
Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics.
RECOMMENDED OPERATING CONDITIONS
Temperature |
–40ºC to 85ºC. |
Voltage |
2.7V to 5.5V |
FUNCTIONAL BLOCK DIAGRAMS
Note: Pinouts for these three drawings reflect the 14 pin SOIC package.
A0 3
A1 2
A2 1
SDA 14
SCL 12
CS 8
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VDD |
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13 |
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VOLATILE REGISTER |
VOLATILE CONTROL REGISTER |
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VREFH2 |
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10-BIT |
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VOUT2 |
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DAC |
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INTERFACE CONTROL& |
LOGIC |
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VREFL2 |
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CONFIGURATION |
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REGISTER |
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VOLATILE REGISTER |
VOLATILE CONTROL REGISTER |
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VREFH1 |
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10-BIT |
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VOUT1 |
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DAC |
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SMP9210 |
10 VREFL1 |
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7 |
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GND |
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2048 BD10 2.2 |
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2 |
2048 3.3 10/03/01 |
SUMMIT MICROELECTRONICS, Inc. |
SMP9210, SMP9211, SMP9212
Preliminary
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VDD |
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VOLATILE REGISTER |
VOLATILE CONTROL REGISTER |
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VREFH2 |
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NON- |
10-BIT |
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VOUT2 |
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DAC |
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A0 |
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A1 |
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INTERFACE CONTROL& |
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VREFL2 |
A2 |
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LOGIC |
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CONFIGURATION |
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REGISTER |
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SDA |
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11 |
VREFH1 |
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SCL |
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VOLATILE REGISTER |
VOLATILE CONTROL REGISTER |
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NON- |
10-BIT |
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VOUT1 |
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DAC |
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8 |
MUTE# |
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10 VREFL1 |
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SMP9211 |
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7 |
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GND |
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2048 BD11 2.2 |
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VDD |
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13 |
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VOLATILE REGISTER |
VOLATILE CONTROL REGISTER |
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VREFH2 |
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NON- |
10-BIT |
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VOUT2 |
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DAC |
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A0 |
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A1 |
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INTERFACE CONTROL& |
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VREFL2 |
A2 |
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LOGIC |
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CONFIGURATION |
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REGISTER |
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SDA |
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VREFH1 |
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SCL |
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VOLATILE REGISTER |
VOLATILE CONTROL REGISTER |
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NON- |
10-BIT |
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VOUT1 |
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DAC |
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VREF |
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PRECISION |
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10 VREFL1 |
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SMP9212 |
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REFERENCE |
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7 |
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GND |
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2048 BD12 3.0 |
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SUMMIT MICROELECTRONICS, Inc. |
2048 3.3 10/03/01 |
3 |
SMP9210, SMP9211, SMP9212
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Preliminary |
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PIN CONFIGURATIONS |
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14-Pin SOIC |
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SMP9210 |
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SMP9211 |
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SMP9212 |
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A2 |
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SDA |
A2 |
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SDA |
A2 |
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SDA |
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A1 |
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VDD |
A1 |
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VDD |
A1 |
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VDD |
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A0 |
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SCL |
A0 |
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SCL |
A0 |
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SCL |
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VREFH2 |
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VREFH1 |
VREFH2 |
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11 |
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VREFH1 |
VREFH2 |
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4 |
11 |
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VREFH1 |
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VREFL2 |
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VREFL1 |
VREFL2 |
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VREFL1 |
VREFL2 |
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VREFL1 |
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VOUT2 |
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VOUT1 |
VOUT2 |
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VOUT1 |
VOUT2 |
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VOUT1 |
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GND |
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CS |
GND |
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MUTE# |
GND |
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7 |
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VREF |
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2048 14-PCon |
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16-Pin SSOP |
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SMP9210 |
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SMP9211 |
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SMP9212 |
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A2 |
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SDA |
A2 |
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SDA |
A2 |
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SDA |
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NC |
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NC |
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NC |
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NC |
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A1 |
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VDD |
A1 |
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VDD |
A1 |
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VDD |
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A0 |
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SCL |
A0 |
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SCL |
A0 |
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SCL |
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VREFH2 |
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VREFH1 |
VREFH2 |
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VREFH1 |
VREFH2 |
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VREFH1 |
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VREFL2 |
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VREFL1 |
VREFL2 |
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VREFL1 |
VREFL2 |
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VREFL1 |
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VOUT2 |
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VOUT1 |
VOUT2 |
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VOUT1 |
VOUT2 |
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VOUT1 |
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GND |
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CS |
GND |
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MUTE# |
GND |
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8 |
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VREF |
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2048 16-PCon
PIN DESCRIPTIONS
VDD
Power supply input.
GND
Power supply return.
VOUT1, VOUT2
The voltage output of the DACs. It is buffered by a unitygain follower that can slew up to 1V/µs.
VREFL1, VREFL2
The lower of the voltage reference inputs. VREFL must be equal to or greater than ground and less than VREFH.
VREFH1, VREFH2
The higher of the voltage reference inputs. VREFHmustbe equal to or less than VCC and greater than VREFL.
A0, A1, A2
The address inputs for the serial interface logic. Biasing the address inputs will determine the device’s bus address that is contained within the serial data stream when communicating over the serial bus.
SCL
The serial interface clock. It is used to clock the data in and out. When writing to the device data must remain stable while SCL is high. When reading from the device data is clocked out on the falling edge of SCL.
SDA
The bidirectional pin used to transfer data in and out of the device.
CS
Chip Select input (VIH = selected) in the 9210. See the Block Diagrams.
MUTE#
Mute input (VIL = mute) in the 9211. See the Block Diagrams.
VREF
VREF output (1.25V) in the 9212. See the Block Diagrams.
Note: NC pins are not connected.
4 |
2048 3.3 10/03/01 |
SUMMIT MICROELECTRONICS, Inc. |