SUMMIT S4242P, S4242PA, S4242PB, S4242S, S4242SA Datasheet

S4242/S42WD42/S4261/S42WD61

Dual Voltage Supervisory Circuit

With Watchdog Timer(S42WD61) (S42WD42)

FEATURES

•Precision Dual Voltage Monitor

–VCC Supply Monitor

-Dual reset outputs for complex microcontroller systems

-Integrated memory write lockout function

-No external components required

•Second Voltage Monitor Output

–Separate VLOW output

–Generates interrupt to MCU

–Generates RESET for dual supply systems

-Guaranteed output assertion to VCC - 1V

•Watchdog Timer (S42WD42, S42WD61)

–1.6s

•High Reliability

–Endurance: 100,000 erase/write cycles

–Data retention: 100 years

OVERVIEW

The S42xxx are a precision power supervisory circuit. It automatically monitors the device’s VCC level and will generate a reset output on two complementary open drain outputs. In addition to the VCC monitoring, the S42xxx also provides a second voltage comparator input. This input has an independent open drain output that can be wireOR’ed with the RESET I/O or it can be used as a system interrupt.

	•	Memory Internally Organized 2 x8	The S42xxx also has an integrated 4k/16k-bit nonvolatile
	•	Extended Programmable Functions	memory. The memory conforms to the industry standard
			two-wire serial interface. In addition to the reset circuitry,

	Available on SMS24			the S42WD42/S42WD61 also has a watchdog timer.
BLOCK DIAGRAM
	VCC
		8

SCL	6		NONVOLATILE
SDA	5		MEMORY
			ARRAY
			WRITE
			CONTROL
			PROGRAMMABLE
			RESET PULSE
			GENERATOR
	+	VTRIP	RESET
	–		CONTROL
			PROGRAMMABLE
			WATCHDOG
			TIMER

	UV
VSENSE 3	+
	–
	OV
	1.26V
	4

2 RESET#

7 RESET

(S42WD42,

S42WD61)

1 VLOW#

GND	2025 T BD 2.0
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131	• Campbell, CA 95008 • Telephone [phone] • Fax [phone] • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000	Characteristics subject to change without notice
2025 6.0 4/17/00	1

			S4242/S42WD42/S4261/S42WD61
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ...............................................................................................................................			-40°C to +85°C
Storage Temperature .....................................................................................................................................			-65°C to +125°C
Soldering Temperature (less than 10 seconds) ...................................................................................................................			300°C
Supply Voltage .............................................................................................................................................................			0 to 6.5V
Voltage on Any Pin .......................................................................................................................................			-0.3V to VCC+0.3V
ESD Voltage (JEDEC method) ..........................................................................................................................................			2,000V

NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature	Min	Max
Commercial	0°C	+70°C
Industrial	-40°C	+85°C

2025 PGM T1.0

DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)

Symbol	Parameter	Conditions		Min	Max	Units
		SCL = CMOS Levels @ 100KHz	VCC =5.5V		3	mA
ICC	Supply Current (CMOS)	SDA = Open
		All other inputs = GND or VCC	VCC =3.3V		2	mA
ISB	Standby Current (CMOS)	SCL = SDA = VCC	VCC =5.5V		50	µA
		All other inputs = GND	VCC =3.3V		25	µA
ILI	Input Leakage	VIN = 0 To VCC			10	µA
ILO	Output Leakage	VOUT = 0 To VCC			10	µA
VIL	Input Low Voltage	SCL, SDA, RESET# (pin 2)			0.3xVCC	V
VIH	Input High Voltage	SCL, SDA, RESET (pin7)			0.7xVCC	V
VOL	Output Low Voltage	IOL = 3mA SDA			0.4	V

2025 PGM T2.0

AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)			2.7V to 4.5V		4.5V to 5.5V
Symbol	Parameter	Conditions	Min	Max	Min	Max	Units
fSCL	SCL Clock Frequency		0	100		400	KHz
tLOW	Clock Low Period		4.7		1.3		µs
tHIGH	Clock High Period		4.0		0.6		µs
tBUF	Bus Free Time	Before New Transmission	4.7		1.3		µs
tSU:STA	Start Condition Setup Time		4.7		0.6		µs
tHD:STA	Start Condition Hold Time		4.0		0.6		µs
tSU:STO	Stop Condition Setup Time		4.7		0.6		µs
tAA	Clock to Output	SCL Low to SDA Data Out Valid	0.3	3.5	0.2	0.9	µs
tDH	Data Out Hold Time	SCL Low to SDA Data Out Change	0.3		0.2		µs
tR	SCL and SDA Rise Time			1000		300	ns
tF	SCL and SDA Fall Time			300		300	ns
tSU:DAT	Data In Setup Time		250		100		ns
tHD:DAT	Data In Hold Time		0		0		ns
TI	Noise Spike Width	Noise Suppression Time Constant		100		100	ns
	@ SCL, SDA Inputs
tWR	Write Cycle Time			10		10	ms
						2025 PGM T3.0
2025 6.0 4/17/00		2

S4242/S42WD42/S4261/S42WD61

CAPACITANCE

TA = 25°C, f = 100KHz

Symbol		Parameter		Max	Units
CIN		Input Capacitance		5	pF
COUT	Output Capacitance			8	pF
					2025 PGM T4.0
tR	tF	tHIGH	tLOW
SCL
tSU:SDA	tHD:SDA	tHD:DAT	tSU:DAT	tSU:STO	tBUF
SDA In
tAA			tDH
SDA Out
					2025 Fig01 1.0
		FIGURE 1. BUS TIMING

START	STOP
Condition	Condition

SCL

SDA In

2025 Fig02 1.0

FIGURE 2. START AND STOP CONDITIONS

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3

	S4242/S42WD42/S4261/S42WD61
	tGLITCH
VTRIP
VCC
VRVALID	tRPD
	tPURST	tPURST
RESET#
		tRPD
RESET
	FIGURE 3. RESET OUTPUT TIMING	2025 T fig03 2.0

RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS

TA=-40°C to +85°C

Symbol	Parameter	Part no.	Min.	Typ.	Max.	Unit
		Suffix
VTRIP	Reset Trip Point	A (or) Blank	4.250	4.375	4.5	V
		B	4.50	4.625	4.75	V
		2.7	2.7	2.9	3.10	V
tPURST	Reset Timeout			200		ms
tRPD	VTRIP to RESET Output Delay				5	µs
VRVALID	RESET Output Valid to VCC min. Guarantee		1			V
tGLITCH	Glitch Reject Pulse Width note 1			30		ns
VOLRS	RESET Output Low Voltage IOL = 1mA				0.4	V
VOHRS	RESET High Voltage Output IOH = 800µA		VCC-.75			V
VULH	VSENSE Under-voltage threshold low to high		1.20	1.25	1.30	V
VUHL	VSENSE Under-voltage threshold high to low		1.20	1.25	1.30	V
VOLH	VSENSE Over-voltage threshold low to high		1.20	1.25	1.30	V
VOHL	VSENSE Over-voltage threshold high to low		1.20	1.25	1.30	V
tVD1	Delay to VLOW Active				5	µs
tVD2	Delay to VLOW Released				5	µs
tWDTO	Watchdog timeout Period (S42WD61)			1600		ms
	(S42WD42)
						2025 PGM T5.2

2025 6.0 4/17/00

4

S4242/S42WD42/S4261/S42WD61

VULH									VUHL
					(Under-voltage detect)
VSENSE
					tVD1
										tVD2

VLOW#

2025 T fig04 2.0

FIGURE 4. VSENSE UNDER-VOLTAGE FUNCTION

RESET# (in)

RESET# (out)

tPURST

tPURST

RESET (out)

2025 T fig05 2.0

FIGURE 5. RESET AS AN INPUT

2025 6.0 4/17/00

5