STMicroelectronics M48T128Y, M48T128V Technical data
5.0 or 3.3V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
FEAT URES SUMMARY
■ INTEGRATED, ULT RA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS
■ AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECT ION
■ WRITE PROTECT VOLTAGES
= Power-fail Deselect Voltage):
(V
PFD
– M48T128Y: V
4.1V ≤ V
PFD
– M48T128V*: V
2.7V ≤ V
■ CONVENTIONAL SRAM OPERATION;
PFD
UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
■ 10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE O F
POWER
■ SELF-CONTAINED BATTERY AND
CRYSTAL IN THE DIP PACKAGE
■ PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
= 4.5 to 5.5V
CC
≤ 4.5V
= 3.0 to 3.6V
CC
≤ 3.0V
M48T128Y
M48T128V*
Figure 1. 32-pi n PMDIP Mo du le
32
1
PMDIP32 (PM)
Module
* Contact local ST sales office for availability of 3.3V version.
1/22February 2005
M48T128Y, M48T128V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Figure 10.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10.Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/22
M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 19
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
M48T128Y, M48T128V*
SUMMARY DESCRIPTION
The M48T128Y/V TIMEKEEPER® RAM is a
128Kb x 8 non-vol atile static RAM and real time
clock. The special DIP package provides a fully integrated battery back-up memory and real time
clock solution. The M48T 128Y /V d irectly replaces
industry standard 128Kb x 8 SRAM.
Figure 2. Logic Diagram Table 1. Signal Names
It also provides the non-vol atility of Flash without
any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600mil DIP Hybrid houses a
controller chip, SRAM, quartz crystal, and a l ong
life lithium button cell in a single package.
V
CC
17
A0-A16 DQ0-DQ7
W
E
G
M48T128Y
M48T128V
V
SS
8
Figure 3. DIP C on ne ctions
1
NC V
2
A16
A14
3
A12
4
5
A7
6
A6
7
A5
A4
A3
A2
A1
A0
DQ0
DQ2
SS
M48T128Y
8
M48T128V
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI02245
CC
A15
NC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI02244
A0-A16 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
CC
V
SS
NC Not Connected Internally
Chip Enable
Output Enable
WRITE Enable
Supply Voltage
Ground
4/22
Figure 4. Block Diagram
M48T128Y, M48T128V*
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
POWER
V
PFD
8 x 8
TIMEKEEPER
REGISTERS
131,064 x 8
SRAM ARRAY
V
SS
A0-A16
DQ0-DQ7
E
W
G
AI01804
5/22
M48T128Y, M48T128V*
OPERATION MODES
Figure 4., page 5 illus tra tes the s tatic mem ory ar-
ray and the quartz controlled clock o scillator. The
clock locations contain the year, month, date, day,
hour, minute, and sec ond in 24 hour BCD form at.
Corrections for 28, 29 (leap year - valid until 2100),
30, and 31 day months are made a utomatically.
Byte 1FFF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1F FF8h) are not the actual
clock counters, they are memory locations consisting of BiPORT™ READ/WRITE memory cells
within the static RAM array. T he M48T128Y /V includes a clock control circuit which updates the
clock bytes with current information once per sec-
Table 2. Operating Modes
4.5 to 5.5V
3.0 to 3.6V
to V
SO
≤ V
V
or
PFD
CC
SO
(min)
(1)
(1)
E G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
X X High Z Standby
X
V
V
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Battery B ack-up Switc hover Voltage.
1. See Table 11., page 18 for details.
V
ond. The information can be accessed by the user
in the same manner as any other location in the
static memory array. The M48T128Y/V also has its
own Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When V
is out of toler-
CC
ance, th e cir cuit wri te pro tect s the TIMEK EEPER
Register data and external SRAM, providin g data
security in the midst of unpredictable system operation. As V
Switchover Voltage (V
falls below the Battery Back-up
CC
), the control circuitry au-
SO
tomatically switches to the battery, maintaining
data and clock operation until valid power is restored.
V
IL
IL
IH
V
IH
V
IH
D
IN
D
OUT
High Z Active
Active
Active
®
6/22
READ Mode
The M48T128Y/V is in the READ Mode whenever
(WRITE Enable) is high and E (Chip Enable) is
W
low. The unique address specified by the 17 Address Inputs defines which one of the 131,072
bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within t
address input signal is stable, providing the E
access times are also satisfied. If the E and G
G
(Address Access Time) after the last
AVQV
and
access t imes are n ot me t, v alid d ata w ill be av ail-
Figure 5. READ Mode AC Waveforms
M48T128Y, M48T128V*
able after the latter of the Chip Enable Access
Times (t
). The state of the eight three-state Data I/O
(t
GLQV
signals is controlled by E
activated before t
to an indeterminate state until t
dress Inputs are changed while E
active, output data will remain valid for t
put Data Hold Time) but will go indeterminate until
the next Address Acce ss.
tAVAV
) or Output Enable Access Time
ELQV
and G. If the outputs are
, the data lines will be driven
AVQV
AVQV
and G remain
. If the Ad-
(Out-
AXQX
A0-A16
tAVQV tAXQX
tELQV
E
tELQX
G
tGLQX
DQ0-DQ7
Note: WE = High.
tGLQV
VALID
tEHQZ
tGHQZ
DATA OUT
AI01197
Table 3. READ Mode AC Characteristics
M48T128Y M48T128V
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. Valid for Ambient Operating Tem perature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where noted ).
2. C
READ Cycle Time 70 85 ns
Address Valid to Output Valid 70 85 ns
Chip Enable Low to Output Valid 70 85 ns
Output Enable Low to Output Valid 40 55 ns
(2)
Chip Enable Low to Output Transition 5 5 ns
(2)
Output Enable Low to Output Transition 5 5 ns
(2)
Chip Enable High to Output Hi-Z 25 30 ns
(2)
Output Enable High to Output Hi-Z 25 30 ns
Address Transition to Output Transition 10 5 ns
= 5pF.
L
Parameter
(1)
Min Max Min Max
Unit–70 –85
7/22
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