Page 1
Serial real-time clock with 44 bytes NVRAM and reset
Features
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ 32 KHz crystal oscillator integrating load
capacitance (12.5 pF) providing exceptional
oscillator stability and high crystal series
resistance operation
■ Serial peripheral interface (2 MHz SPI)
■ Ultralow battery supply current of 500 nA (max)
■ 2.7 to 5.5 V operating voltage
■ 2.5 to 5.5 V oscillator operating voltage
■ Battery low flag
■ Automatic switchover and deselect circuitry
■ 44 bytes of general purpose RAM
■ Programmable alarm and interrupt function
(valid even during battery backup mode)
■ Accurate programmable watchdog timer (from
62.5 ms to 128 s)
■ Microprocessor power-on reset
■ Choice of power-fail deselect voltages
(V
= 2.7 to 5.5 V):
CC
–THS = V
–THS = V
■ Packaging includes a 28-lead SOIC and
SNAPHAT
16-lead SOIC
■ 28-lead SOIC package provides direct
connection for a SNAPHAT
contains the battery and crystal
■ RoHS compliant
– Lead-free second level interconnect
; 2.55 V ≤ V
SS
; 4.20 V ≤ V
CC
®
top (to be ordered separately) or
≤ 2.70 V
PFD
≤ 4.50 V
PFD
®
top which
M41T94
16
1
SO16 (MQ)
SNAPHAT® (SH)
battery & crystal
28
1
SOH28 (MH)
January 2009 Rev 6 1/41
www.st.com
1
Page 2
Contents M41T94
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Chip enable (E
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7 Reset inputs (RSTIN1
4.8 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
& RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.10 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.11 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.12 t
4.13 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REC
5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/41
Page 3
M41T94 Contents
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3/41
Page 4
List of figures M41T94
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. 16-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Alarm interrupt reset waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Backup mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. RSTIN1
Figure 14. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. SO16 – 16-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT
Figure 20. SH – 4-pin SNAPHAT
Figure 21. SH – 4-pin SNAPHAT
Figure 22. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
and RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
®
®
housing for 48 mAh battery & crystal, package outline. . . . . . . . . 35
®
housing for 120 mAh battery & crystal, package outline. . . . . . . . 36
, package outline . . . . . . . . . . 34
4/41
Page 5
M41T94 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Alarm repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. t
Table 9. Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. SO16 – 16-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . 33
Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT
Table 18. SH – 4-pin SNAPHAT
Table 19. SH – 4-pin SNAPHAT
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. SNAPHAT
Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REC
®
®
housing for 48 mAh battery & crystal, package mechanical data. 35
®
housing for 120 mAh battery & crystal, package mech. data . . . . 36
®
battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
, package mechanical data . . 34
5/41
Page 6
Description M41T94
1 Description
The M41T94 is a serial real-time clock with 44 bytes of NVRAM and a RESET output. A
built-in 32,768 Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see
Table 4 on page 18) are used for the clock/calendar function and are configured in binary
coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/control of alarm, watchdog and square wave
functions. Addresses and data are transferred serially via a serial SPI interface. The built-in
address register is incremented automatically after each WRITE or READ data byte. The
M41T94 has a built-in power sense circuit which detects power failures and automatically
switches to the battery supply when a power failure occurs. The energy needed to sustain
the SRAM and clock operations can be supplied by a small lithium button-cell supply when a
power failure occurs. Functions available to the user include a non-volatile, time-of-day
clock/calendar, alarm interrupts, watchdog timer and programmable square wave output.
Other features include a power-on reset as well as two additional debounced inputs
(RSTIN1
address locations contain the century, year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year valid until year 2100), 30 and 31 day months are made automatically. The ninth clock
address location controls user access to the clock information and also stores the clock
software calibration setting.
and RSTIN2) which can also generate an output reset (RST). The eight clock
The M41T94 is supplied in either a 16-lead plastic SOIC (requiring user supplied crystal and
battery) or a 28-lead SOIC SNAPHAT
in a single SNAPHAT top). The 28-pin, 330 mil SOIC provides sockets with gold plated
contacts at both ends for direct connection to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be
mounted on top of the SOIC package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal
damage due to the high temperatures required for device surface-mounting. The SNAPHAT
housing is also keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part
number is “M4TXX-BR12SH” (see Table 21 on page 37).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the
lithium button-cell battery.
®
package (which integrates both crystal and battery
6/41
Page 7
M41T94 Description
Figure 1. Logic diagram
(1)
XI
(1)
XO
SCL
SDI
E
RSTIN1
RSTIN2
WDI
THS
1. For SO16 package only.
Figure 2. 16-pin SOIC connections
V
CC
M41T94
V
SS
V
BAT
(1)
RST
IRQ/FT/OUT
SQW
SDO
AI03683
XI V
1
XO
RST
WDI
RSTIN1
RSTIN2
V
BAT
V
SS
2
3
4
5
6
7
8
M41T94
16
15
14
13
12
11
10
9
AI03684
CC
E
IRQ/FT/OUT
THS
SDI
SQW
SCL
SDO
7/41
Page 8
Description M41T94
Table 1. Signal names
E Chip enable
/FT/OUT
IRQ
RST
RSTIN1
Interrupt/frequency test/out
output (open drain)
Reset output (open drain)
Reset 1 input
RSTIN2
Reset 2 input
SCL Serial clock input
SDI Serial data input
SDO Serial data output
SQW Square wave output
THS Threshold select pin
WDI Watchdog input
(1)
XI
(1)
XO
(1)
V
BAT
V
CC
V
SS
1. For SO16 package only.
Oscillator input
Oscillator output
Battery supply voltage
Supply voltage
Ground
Figure 3. 28-pin SOIC connections
SQW V
NC
NC
NC
NC
NC
NC
WDI
RSTIN1
RSTIN2
NC
NC
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M41T94
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI03685
CC
E
IRQ/FT/OUT
NC
NC
THS
NC
NC
SCL
NC
RST
SDINC
SDO
NC
8/41
Page 9
M41T94 Description
Figure 4. Block diagram
E
SDO
SDI
SCL
Crystal
WDI
V
CC
RSTIN1
RSTIN2
1. Open drain output
V
BAT
SPI
INTERFACE
32KHz
OSCILLATOR
VBL= 2.5V
V
SO
V
PFD
= 2.5V
= 4.4V
(2.65V if THS = VSS)
COMPARE
COMPARE
COMPARE
REAL TIME CLOCK
CALENDAR
44 BYTES
USER RAM
RTC w/ALARM
& CALIBRATION
WATCHDOG
SQUARE WAVE
BL
POR
AF
WDF
IRQ/FT/OUT
SQW
(1)
RST
AI04785
(1)
Figure 5. Hardware hookup
SPI Interface with
(CPOL, CPHA)
('0','0') or ('1','1')
Master
(ST6, ST7, ST9,
ST10, Others)
CS3
CS2
1. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
(1)
=
CS1
D
Q
C
CQD
M41T94
E
CQD
XXXXX
E E
CQD
XXXXX
AI03686
9/41
Page 10
Description M41T94
Table 2. Function table
Mode E SCL SDI SDO
Disable reset H Input disabled Input disabled High Z
WRITE L Data bit latch High Z
AI04630
READ L X Next data bit shift
AI04631
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 6. Data and clock timing
CPOL
CPHA
0
1
0
1
C
C
(1)
SDI
SDO
MSB
MSB
LSB
LSB
AI04632
10/41
Page 11
M41T94 Signal description
2 Signal description
2.1 Serial data output (SDO)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the
falling edge of the serial clock.
2.2 Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and
the data to be written, are each received this way. Input is latched on the rising edge of the
serial clock.
2.3 Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 7 on page 13
and Figure 8 on page 14). The W/R bit, addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output data on the SDO pin changes state after the
falling edge of the clock input.
The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
● (CPOL, CPHA) = ('0', '0') or
● (CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock
SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Ta bl e 2
on page 10 and Figure 6 on page 10).
2.4 Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high
impedance state. After power-on, a high-to-low transition on E
any operation.
is required prior to the start of
11/41
Page 12
Operation M41T94
3 Operation
The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL,
SDI and SDO (see Table 1 on page 8 and Figure 5 on page 9). The device is selected when
the chip enable input (E
in and out of the chip. The most significant bit is presented first, with the data input (SDI)
sampled on the first rising edge of the clock (SCL) after the chip enable (E
bytes contained in the device can then be accessed sequentially in the following order:
st
● 1
● 2
● 3
● 4
● 5
● 6
● 7
● 8
● 9
● 10
● 11
● 17
● 20
● 21
byte: tenths/hundredths of a second register
nd
byte: seconds register
rd
byte: minutes register
th
byte: century/hours register
th
byte: day register
th
byte: date register
th
byte: month register
th
byte: year register
th
byte: control register
th
byte: watchdog register
th
- 16th bytes: Alarm registers
th
- 19th bytes: reserved
th
byte: square wave register
st
- 64th bytes: user RAM
) is held low. All instructions, addresses and data are shifted serially
) goes low. The 64
The M41T94 clock continually monitors V
fall below V
, the device terminates an access in progress and resets the device address
PFD
for an out-of tolerance condition. Should VCC
CC
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. When V
V
, the device automatically switches over to the battery and powers down into an ultra low
SO
current mode of operation to conserve battery life. As system power returns and V
above V
Write protection continues until V
, the battery is disconnected, and the power supply is switched to external VCC.
SO
reaches V
CC
(min) plus t
PFD
(min). For more
REC
falls below
CC
CC
rises
information on battery storage life refer to application note AN1012.
12/41
Page 13
M41T94 Operation
3.1 SPI bus characteristics
The serial peripheral interface (SPI) bus is intended for synchronous communication
between different ICs. It consists of four signal lines: serial data input (SDI), serial data
output (SDO), serial clock (SCL) and a chip enable (E
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
The E
input is used to initiate and terminate a data transfer. The SCL input is used to
synchronize data transfer between the master (micro) and the slave (M41T94) devices.
The SCL input, which is generated by the microcontroller, is active only during address and
data transfer to any device on the SPI bus (see Figure 5 on page 9).
The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
● (CPOL, CPHA) = ('0', '0') or
● (CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock
SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Ta bl e 2
on page 10 and Figure 6 on page 10).
).
There is one clock for each bit transferred. Address and data bits are transferred in groups
of eight bits. Due to memory size the second most significant address bit is a Don’t Care
(address bit 6).
Figure 7. Input timing requirements
E
tELCH
SCL
tDVCH
SDI
SDO
MSB IN
HIGH IMPEDANCE
tCHDX
tDLDH
tDHDL
tCHEH
tCLCH
tEHEL
tEHCH
tCHCL
LSB IN
AI04633
13/41
Page 14
Operation M41T94
Figure 8. Output timing requirements
E
tCH
SCL
SDO
ADDR. LSB IN
SDI
tCLQV
tCLQX
MSB OUT
tCL
LSB OUT
tQLQH
tQHQL
tEHQZ
AI04634
Table 3. AC characteristics
Symbol Parameter
(1)
Min Max Unit
f
SCL
(2)
t
CH
(3)
t
CHCL
t
CHDX
t
CHEH
(2)
t
CL
(3)
t
CLCH
t
CLQV
t
CLQX
(3)
t
DHDL
(3)
t
DLDH
t
DVC H
t
EHCH
t
EHEL
(3)
t
EHQZ
t
ELCH
(3)
t
QHQL
(3)
t
QLQH
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
+ tCL ≥ 1/f
2. t
CH
3. Value guaranteed by design, not 100% tested in production.
Serial clock input frequency DC 2 MHz
Clock high 200 ns
Clock transition (fall time) 1 µs
Serial clock input high to input data transition 50 ns
Serial clock input high to chip enable high 200 ns
Clock low 200 ns
Clock transition (rise time) 1 µs
Serial clock input low to output valid 150 ns
Serial clock input low to output data transition 0 ns
Input data transition (fall time) 1 µs
Input data transition (rise time) 1 µs
Input data to serial clock input high 40 ns
Chip enable high to serial clock input high 200 ns
Chip enable high to chip enable low 200 ns
Chip enable high to output high-z 250 ns
Chip enable low to serial clock input high 200 ns
Output data transition (fall time) 100 ns
Output data transition (rise time) 100 ns
SCL
14/41
Page 15
M41T94 Operation
3.2 Read and write cycles
Address and data are shifted MSB first into the serial data input (SDI) and out of the serial
data output (SDO). Any data transfer considers the first bit to define whether a READ or
WRITE will occur. This is followed by seven bits defining the address to be read or written.
Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE
operation. The address is always the second through the eighth bit written after the Enable
(E
) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a
'0,' one or more READ cycles will occur (see Figure Figure 9 on page 16 and Figure 10 on
page 16).
Data transfers can occur one byte at a time or in multiple byte burst mode, during which the
address pointer will be automatically incremented. For a single byte transfer, one byte is
read or written and then E
that E
continue to remain low. Under this condition, the address pointer will continue to
increment as stated previously. Incrementing will continue until the device is deselected by
taking E
high. The address will wrap to 00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). Although the clock continues to maintain the correct time, this
will prevent updates of time and date during either a READ or WRITE of these address
locations by the user. The update will resume either due to a deselect condition or when the
pointer increments to an non-clock or RAM address (08h to 3Fh).
is driven high. For a multiple byte transfer all that is required is
Note: This is true both in READ and WRITE mode.
3.3 Data retention mode
With valid VCC applied, the M41T94 can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T94 will automatically deselect,
write protecting itself when V
page 31). At this time, the reset pin (RST
returns to nominal levels. When V
switched from the V
pin to the SNAPHAT battery (or external battery for SO16) at this
CC
time, and the clock registers are maintained from the attached battery supply. All outputs
become high impedance. On power-up, when V
protection continues for t
during this time (see Figure 17 on page 31). Before the next active cycle, chip enable should
be taken high for at least t
For a further more detailed review of battery lifetime calculations, please see application
note AN1012.
falls between V
CC
) is driven active and will remain active until VCC
falls below the switchover voltage (VSO), power input is
CC
by internally inhibiting E. The RST signal also remains active
REC
, then low.
EHEL
(max) and V
PFD
returns to a nominal value, write
CC
(min) (see Figure 17 on
PFD
15/41
Page 16
Operation M41T94
Figure 9. Read mode sequence
E
7
SCL
1
6
5
3
4
2
0
9
8
12 13
14
15 16
17 22
7 BIT ADDRESS
3
4
6
5
HIGH IMPEDANCE
SDI
SDO
W/R BIT
7
MSB
Figure 10. Write mode sequence
E
1
2
0
SCL
SDI
W/R BIT
7
MSB
665
7 BIT ADDR
443321
201
5
DATA OUT
(BYTE 1)
3
201
5
6
9
10
DATA BYTE
65
4
4321
7
MSB
7
8
0
7
MSB
7
MSB
15
0
7
6
DATA OUT
(BYTE 2)
4
5
3
201
AI04635
SDO
HIGH IMPEDANCE
16/41
AI04636
Page 17
M41T94 Clock operations
4 Clock operations
The eight byte clock register (see Table 4 on page 18) is used to both set the clock and to
read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths
of seconds, seconds, minutes, and hours are contained within the first four registers. Bits D6
and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit
(CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from
'0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is
set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month and years. The
ninth clock register is the control register (this is described in the clock calibration section).
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. If the device is expected to spend a significant amount of time on the shelf,
the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator
restarts within one second.
The eight clock registers may be read one byte at a time, or in a sequential block. The
control register (address location 08h) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the eight clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
halted. This will prevent a transition of data during the READ.
4.1 Power-down time-stamp
When a power failure occurs, the halt update bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the clock registers, and will allow the user to read the
exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to
update the clock registers with the current time. For more information, see application note
AN1572.
4.2 Clock registers
The M41T94 offers 20 internal registers which contain clock, alarm, watchdog, flag, square
wave and control data (see Table 4 on page 18). These registers are memory locations
which contain external (user accessible) and internal copies of the data (usually referred to
as BiPORT
they are updated periodically by the simultaneous transfer of the incremented internal copy.
The internal divider (or clock) chain will be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be halted whenever the clock addresses (00h
to 07h) are being written. The update will resume either due to a deselect condition or when
the pointer increments to a non-clock or RAM address.
Clock and alarm registers store data in BCD. Control, watchdog and square wave registers
store data in binary format.
™
cells). The external copies are independent of internal functions except that
17/41
Page 18
Clock operations M41T94
Table 4. Clock register map
Addr
D7 D6 D5 D4 D3 D2 D1 D0
(1)
Function/range
BCD format
00h 0.1 seconds 0.01 seconds Seconds 00-99
01h ST 10 seconds Seconds Seconds 00-59
02h 0 10 minutes Minutes Minutes 00-59
03h CEB CB 10 Hours Hours (24 hour format) Century/hours 0-1/00-23
04h TR 0 0 0 0 Day of week Day 01-7
05h 0 0 10 date Date: day of month Date 01-31
06h 0 0 0 10M Month Month 01-12
07h 10 Years Year Year 00-99
08h OUT FT S Calibration Control
09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
0Ah AFE SQWE ABE Al 10M Alarm month Al month 01-12
0Bh RPT4 RPT5 AI 10 date Alarm date Al date 01-31
0Ch RPT3 HT AI 10 hour Alarm hour Al hour 00-23
0Dh RPT2 Alarm 10 minutes Alarm minutes Al min 00-59
0Eh RPT1 Alarm 10 seconds Alarm seconds Al sec 00-59
0FhWDFAF0BL0000 Flags
10h 0 0 0 0 0 0 0 0 Reserved
11h 0 0 0 0 0 0 0 0 Reserved
12h 0 0 0 0 0 0 0 0 Reserved
13h RS3 RS2 RS1 RS0 0 0 0 0 SQW
1. Keys:
S = Sign bit
FT = Frequency test bit
ST = Stop bit
0 = Must be set to zero
BL = Battery low flag (read only)
BMB0-BMB4 = Watchdog multiplier bits
CEB = Century enable bit
CB = Century bit
OUT = Output level
AFE = Alarm flag enable flag
RB0-RB1 = Watchdog resolution bits
WDS = Watchdog steering bit
ABE = Alarm in battery back-up mode enable bit
RPT1-RPT5 = Alarm repeat mode bits
WDF = Watchdog flag (read only)
WDF = Watchdog flag (read only)
AF = Alarm flag (read only)
SQWE = Square wave enable
RS0-RS3 = SQW frequency
HT = Halt update bit
TR = t
REC
bit
18/41
Page 19
M41T94 Clock operations
4.3 Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every
year, month, day, hour, minute, or second. It can also be programmed to go off while the
M41T94 is in the battery backup to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 5 on page 19 shows
the possible configurations. Codes not listed in the table default to the once per second
mode to quickly alert the user of an incorrect alarm setting.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the
alarm condition activates the IRQ
Note: If the address pointer is allowed to increment to the flag register address, an alarm condition
will not cause the interrupt/flag to occur until the address pointer is moved to a different
address. It should also be noted that if the last address written is the “Alarm Seconds,” the
address pointer will increment to the flag address, causing this situation to occur.
/FT/OUT pin.
To disable the alarm, write '0' to the alarm date register and to RPT1–5. The IRQ
/FT/OUT
output is cleared by a READ to the flags register. This READ of the flags register will also
reset the alarm flag (D6; register 0Fh). See Figure 11 on page 19.
The IRQ
/FT/OUT pin can also be activated in the battery backup mode. The IRQ/FT/OUT
will go low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE
are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated
during power-up will only set AF. The user can read the flag register at system boot-up to
determine if an alarm was generated while the M41T94 was in the deselect mode during
power-up. Figure 12 on page 20 illustrates the backup mode alarm timing.
Table 5. Alarm repeat mode
RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting
1 1 1 1 1 Once per second
1 1 1 1 0 Once per minute
1 1 1 0 0 Once per hour
1 1 0 0 0 Once per day
1 0 0 0 0 Once per month
0 0 0 0 0 Once per year
Figure 11. Alarm interrupt reset waveforms
ACTIVE FLAG
IRQ/FT/OUT
0Fh0Eh 10h
HIGH-Z
AI03664
19/41
Page 20
Clock operations M41T94
Figure 12. Backup mode alarm waveforms
V
CC
V
PFD
V
SO
tREC
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
HIGH-Z
HIGH-Z
AI03920
20/41
Page 21
M41T94 Clock operations
4.4 Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the Watchdog
register, address 09h. bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00 =
and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
Watchdog register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M41T94 sets the
WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. WDF
is reset by reading the flags register (0Fh).
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0,' the watchdog will activate the IRQ
set to a '1,' the watchdog will output a negative pulse on the RST pin for t
register and the AFE, ABE, SQWE, and FT bits will reset to a '0' at the end of a watchdog
time-out when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI),
or
2. the microprocessor can perform a WRITE of the watchdog register.
1
/16 second, 01 =1/4 second, 10 = 1 second,
/FT/OUT pin when timed-out. When WDS is
. The watchdog
REC
The time-out period then starts over. The WDI pin should be tied to V
to perform a software reset of the watchdog timer, the original time-out period can be written
into the watchdog register, effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt,
a value of 00h needs to be written to the watchdog register in order to clear the IRQ
pin. This will also disable the watchdog function until it is again programmed correctly. A
READ of the flags register will reset the watchdog flag (bit D7; register 0Fh).
The watchdog function is automatically disabled upon power-up and the watchdog register
is cleared. If the watchdog function is set to output to the IRQ
test (FT) function is activated, the watchdog function prevails and the frequency test function
is denied.
4.5 Square wave output
The M41T94 offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These
frequencies are listed in Table Table 6 on page 22. Once the selection of the SQW
frequency has been completed, the SQW pin can be turned on and off under software
control with the square wave enable bit (SQWE) located in register 0Ah.
if not used. In order
SS
/FT/OUT
/FT/OUT pin and the frequency
21/41
Page 22
Clock operations M41T94
Table 6. Square wave output frequency
Square wave bits Square wave
RS3 RS2 RS1 RS0 Frequency Units
0000None–
000132.768kHz
00108.192kHz
00114.096kHz
01002.048kHz
01011.024kHz
0110512Hz
0111256Hz
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
11102Hz
11111Hz
4.6 Power-on reset
The M41T94 continuously monitors VCC. When VCC falls to the power fail detect trip point,
the RST
(max). The RST
pulls low (open drain) and remains low on power-up for t
pin is an open drain output and an appropriate pull-up resistor should be
chosen to control rise time.
4.7 Reset inputs (RSTIN1 & RSTIN2)
The M41T94 provides two independent inputs which can generate an output reset. The
duration and function of these resets is identical to a reset generated by a power cycle.
Table 7 on page 23 and Figure 13 on page 23 illustrate the AC reset characteristics of this
function. Pulses shorter than t
and RSTIN2
are each internally pulled up to VCC through a 100 kΩ resistor.
RLRH1
and t
RLRH2
after VCC passes V
REC
PFD
will not generate a reset condition. RSTIN1
22/41
Page 23
M41T94 Clock operations
Figure 13. RSTIN1 and RSTIN2 timing waveforms
RSTIN1
tRLRH1
RSTIN2
tRLRH2
(1)
RST
tR1HRH tR2HRH
AI03665
Table 7. Reset AC characteristics
Symbol Parameter Min Max Unit
(2)
t
RLRH1
(3)
t
RLRH2
(4)
t
R1HRH
(4)
t
R2HRH
1. Valid for ambient operating temperature: T
2. Pulse width less than 50 ns will result in no RESET (for noise immunity).
3. Pulse width less than 20 ms will result in no RESET (for noise immunity).
4. Programmable (see Table on page 27).
RSTIN1 low to RSTIN1 high 200 ns
RSTIN2 low to RSTIN2 high 100 ms
RSTIN1 high to RST high 40 200 ms
RSTIN2 high to RST high 40 200 ms
4.8 Calibrating the clock
The M41T94 is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. Uncalibrated clock accuracy will not exceed ±35 ppm (parts per million)
oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. When
the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at
25°C.
The oscillation rate of crystals changes with temperature (see Figure 14 on page 25).
Therefore, the M41T94 design employs periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as
shown in Figure 15 on page 25. The number of times pulses are blanked (subtracted,
negative calibration) or split (added, positive calibration) depends upon the value loaded into
the five calibration bits found in the control register. Adding counts speeds the clock up,
subtracting counts slows the clock down.
(1)
= –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
A
The calibration bits occupy the five lower order bits (D4-D0) in the control register (8h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
23/41
Page 24
Clock operations M41T94
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is
running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T94 may
require.
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in application
note AN934: TIMEKEEPER
®
calibration. This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ
/FT/OUT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 1h) is '0,'
the frequency test bit (FT, D6 of 8h) is '1,' the alarm flag enable bit (AFE, D7 of Ah) is '0,' and
the watchdog steering bit (WDS, D7 of 9h) is '1' or the watchdog register (9h = 0) is reset.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction.
Note: Setting or changing the calibration byte does not affect the frequency test output frequency.
The IRQ
/FT/OUT pin is an open drain output which requires a pull-up resistor for proper
operation. A 500 to 10 kΩ resistor is recommended in order to control the rise time. The FT
bit is cleared on power-down.
24/41
Page 25
M41T94 Clock operations
Figure 14. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
ΔF
= K x (T –T
F
K = –0.036 ppm/°C2 ± 0.006 ppm/°C
TO = 25°C ± 5°C
0 10203040506070
Temperature °C
2
)
O
2
80–10–20–30–40
AI00999b
Figure 15. Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
4.9 Century bit
Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
AI00594B
25/41
Page 26
Clock operations M41T94
4.10 Output driver pin
When the FT bit, AFE bit and watchdog register are not set, the IRQ/FT/OUT pin becomes
an output driver that reflects the contents of D7 of the control register. In other words, when
D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ
be driven low.
/FT/OUT pin will
Note: The IRQ
/FT/OUT pin is an open drain which requires an external pull-up resistor.
4.11 Battery low warning
The M41T94 automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
battery backup mode, the battery should be replaced. The SNAPHAT
while V
Note: This will cause the clock to lose time during the interval the SNAPHAT
disconnected.
The M41T94 only monitors the battery when a nominal V
applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
is supplied. In order to insure data integrity during subsequent periods of
CC
is applied to the device.
CC
is applied to the device. Thus
CC
®
top may be replaced
®
battery/crystal top is
4.12 t
REC
bit
Bit D7 of clock register 04h contains the t
continuation of the deselect time after V
time before WRITEs may again be performed to the device after a power-down condition.
The t
bit will allow the user to set the length of this deselect time as defined by Tab l e 8
REC
on page 27.
26/41
bit (TR). t
REC
reaches V
CC
refers to the automatic
REC
. This allows for a voltage setting
PFD
Page 27
M41T94 Clock operations
4.13 Initial power-on defaults
Upon initial application of power to the device, the following register bits are set to a '0' state:
Watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state:
ST, OUT, and HT (see Table 9: Default values).
Table 8. t
t
bit (TR) STOP bit (ST)
REC
009698ms
0140200
1 X 50 2000 µs
1. Default setting
Table 9. Default values
definitions
REC
t
time
REC
Min Max
(1)
Units
ms
Condition TR ST HT Out FT AFE ABE SQWE
Initial power-up
(battery attach for
SNAPHAT
Subsequent power-up
(with battery backup)
1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
®)(2)
(3)
0111000 0 0
UC UC 1 UC 0 0 0 0 0
WATCHDOG
register
(1)
27/41
Page 28
Maximum ratings M41T94
5 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 10. Absolute maximum ratings
Symbol Parameter Value Unit
®
–40 to 85 °C
SOIC –55 to 125 °C
T
STG
Storage temperature (VCC off, oscillator off)
SNAPHAT
V
CC
T
SLD
V
I
O
P
1. For SO16 and SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (the
time above 255°C must not exceed 30 seconds).
Supply voltage –0.3 to 7 V
(1)
Lead solder temperature for 10 seconds 260 °C
Input or output voltage –0.3 to VCC+0.3 V
IO
Output current 20 mA
Power dissipation 1 W
D
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT
®
sockets.
28/41
Page 29
M41T94 DC and AC parameters
6 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 11. DC and AC measurement conditions
Parameter M41T94
V
supply voltage 2.7 to 5.5 V
CC
Ambient operating temperature –40 to 85°C
Load capacitance (CL) 100 pF
Input rise and fall times ≤ 50 ns
(1)
Input pulse voltages 0.2 to 0.8V
Input and output timing ref. voltages 0.3 to 0.7V
1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 16. AC testing input/output waveforms
0.8V
CC
0.2V
CC
Table 12. Capacitance
Symbol Parameter
C
IN
C
OUT
t
LP
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs are deselected.
Input capacitance 7 pF
(3)
Output capacitance 10 pF
Low-pass filter input time constant (SDA and SCL) 50 ns
(1)(2)
0.7V
CC
0.3V
CC
AI02568
Min Max Unit
CC
CC
29/41
Page 30
DC and AC parameters M41T94
Table 13. DC characteristics
Symb. Parameter Test condition
I
BAT
I
CC1
I
CC2
(2)
I
LI
(3)
I
LO
V
IH
V
IL
V
BAT
V
OH
V
OL
(1)
Battery current OSC on
Battery current OSC off 50 nA
T
= 25°C, VCC = 0 V,
A
V
= 3 V
BAT
Min Typ Max Unit
400 500 nA
Supply current f = 2 MHz 2 mA
Supply current (standby) SCL, SDI = V
Input leakage current 0 V ≤ VIN ≤ V
Output leakage current 0 V ≤ V
Input high voltage 0.7V
– 0.3 V 1.4 mA
CC
CC
≤ V
OUT
CC
CC
Input low voltage –0.3 0.3V
Battery voltage 2.5 3.5
(5)
(5)
(6)
IOH = –1.0 mA 2.4 V
IOL = 3.0 mA 0.4
IOL = 10 mA 0.4
, IRQ/FT/OUT 5.5 V
Output high voltage
Output low voltage
Output low voltage (open drain)
Pull-up supply voltage (open drain) RST
Power fail deselect (THS = VCC) 4.20 4.40 4.50
V
PFD
Power fail deselect (THS = V
V
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
2. RSTIN1
3. Outputs deselected.
4. For rechargeable back-up, V
5. For SQW pin (CMOS).
6. For IRQ
Table 14. Crystal electrical characteristics (externally supplied)
Battery backup switchover 2.5 V
SO
and RSTIN2 internally pulled up to VCC through 100 KΩ resistor. WDI internally pulled-down to VSS through
100 KΩ resistor.
(max) may be considered VCC.
BAT
/FT/OUT, RST pins (open drain): if pulled up to supply other than VCC, this supply must be equal to, or less than
3.0 V when VCC = 0 V (during battery backup mode).
Symbol Parameter
) 2.55 2.60 2.70
SS
(1)(2)
Typ M in Max Uni t
±1 µA
±1 µA
VCC + 0.3 V
CC
(4)
V
V
V
V
f
0
R
S
C
L
1. Load capacitors are integrated within the M41T94. Circuit board layout considerations for the 32.768 kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account. These characteristics are
externally supplied.
2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. For contact information on this crystal type,
see Section 10: References on page 39.
Resonant frequency 32.768 kHz
Series resistance 50 kΩ
Load capacitance 12.5 pF
30/41
Page 31
M41T94 DC and AC parameters
Figure 17. Power down/up mode AC waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
tF
INPUTS
RST
OUTPUTS
Table 15. Power down/up AC characteristics
VALID VALID
(PER CONTROL INPUT)
Symbol Parameter
(2)
V
(max) to V
PFD
V
(min) to VSS VCC fall time 10 µs
PFD
V
(min) to V
PFD
VSS to V
PFD
PFD
PFD
(min) VCC rise time 1 µs
Power up deselect time 40 200 ms
Expected data retention time 10
t
t
REC
t
FB
t
t
F
DR
t
RB
(3)
R
(4)
tFB
tDR
(1)
(min) VCC fall time 300 µs
(max) VCC rise time 10 µs
tRB
DON'T CARE
HIGH-Z
Min Typ Max Unit
(5)
tR
tREC
RECOGNIZEDRECOGNIZED
(PER CONTROL INPUT)
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
2. V
3. V
(max) to V
PFD
until 200 µs after V
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring
PFD
passes V
CC
PFD
(min).
4. Programmable (see Table 8 on page 27).
5. At 25°C, VCC = 0 V (when using SOH28 + M4T28-BR12SH SNAPHAT® top).
AI03687
YEARS
31/41
Page 32
Package mechanical data M41T94
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
32/41
Page 33
M41T94 Package mechanical data
Figure 18. SO16 – 16-lead plastic small outline package outline
B
SO-b
Note: Drawing is not to scale.
Table 16. SO16 – 16-lead plastic small outline package mechanical data
Symbol
Typ Min Max Typ Min Max
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.60 0.063
α 0° 8° 0° 8°
A2
e
D
N
1
CP
E
H
A
millimeters inches
C
LA1 α
B 0.35 0.46 0.014 0.018
C 0.19 0.25 0.007 0.010
CP 0.10 0.004
D 9.80 10.00 0.386 0.394
e1.27––0.050– –
E 3.80 4.00 0.150 0.157
L 0.40 1.27 0.016 0.050
N16 16
33/41
Page 34
Package mechanical data M41T94
Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package
outline
Be
N
1
SOH-A
Note: Drawing is not to scale.
Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package
mechanical data
Symbol
Typ Min Max Typ Min Max
A––3.05––0.120
A2
CP
D
E
H
A
C
eB
LA1 α
millimeters inches
A1 – 0.05 0.36 – 0.002 0.014
A2 – 2.34 2.69 – 0.092 0.106
B – 0.36 0.51 – 0.014 0.020
C – 0.15 0.32 – 0.006 0.012
D – 17.71 18.49 – 0.697 0.728
E – 8.23 8.89 – 0.324 0.350
e1.27– –0.050– –
eB – 3.20 3.61 – 0.126 0.142
H – 11.51 12.70 – 0.453 0.500
L – 0.41 1.27 – 0.016 0.050
α – 0° 8° – 0° 8°
N28 28
CP – – 0.10 – – 0.004
34/41
Page 35
M41T94 Package mechanical data
Figure 20. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package
outline
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package
mechanical data
Symbol
Typ Min Max Typ Min Max
A––9.78––0.385
A1 – 6.73 7.24 – 0.265 0.285
A2 – 6.48 6.99 – 0.255 0.275
A1
A
eA
D
E
B
eB
SHTK-A
millimeters inches
A3
A2
L
A3 – – 0.38 – – 0.015
B – 0.46 0.56 – 0.018 0.022
D – 21.21 21.84 – 0.835 0.8560
E – 14.22 14.99 – 0.556 0.590
eA – 15.55 15.95 – 0.612 0.628
eB – 3.20 3.61 – 0.126 0.142
L – 2.03 2.29 – 0.080 0.090
35/41
Page 36
Package mechanical data M41T94
Figure 21. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package
outline
Note: Drawing is not to scale.
Table 19. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package
mech. data
Symbol
Typ Min Max Typ Min Max
A – – 10.54 – – 0.415
A1 – 8.00 8.51 – 0.315 0.335
A2 – 7.24 8.00 – 0.285 0.315
A1
A
eA
D
E
B
eB
SHTK-A
millimeters inches
A3
A2
L
A3 – – 0.38 – – 0.015
B – 0.46 0.56 – 0.018 0.022
D – 21.21 21.84 – 0.835 0.860
E – 17.27 18.03 – 0.680 0.710
eA – 15.55 15.95 – 0.612 0.628
eB – 3.20 3.61 – 0.126 0.142
L – 2.03 2.29 – 0.080 0.090
36/41
Page 37
M41T94 Part numbering
8 Part numbering
Table 20. Ordering information scheme
Example: M41T 94 MH 6 E
Device type
M41T
Supply voltage and write protect voltage
94 = V
THS = V
THS = VSS; 2.55 V ≤ V
Package
MQ = SO16
MH
Temperature range
6 = –40 to 85°C
= 2.7 to 5.5 V
CC
CC
(1)
= SOH28
; 4.20 V ≤ V
PFD
PFD
≤ 4.50 V
≤ 2.70 V
Shipping method
E = Lead-free package (ECOPACK
F = Lead-free package (ECOPACK
1. The 28-pin SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered
separately under the part number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in tape &
reel form (see Table Table 21 on page 37).
Caution: Do not place the SNAPHAT
will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 21. SNAPHAT® battery table
Part number Description Package
M4T28-BR12SH1 Lithium battery (48 mAh) and crystal SNAPHAT
M4T32-BR12SHx Lithium battery (120 mAh) and crystal SNAPHAT
®
), tubes
®
), tape & reel
®
battery package “M4TXX-BR12SH” in conductive foam as it
®
®
SH
SH
37/41
Page 38
Environmental information M41T94
9 Environmental information
Figure 22. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
38/41
Page 39
M41T94 References
10 References
The crystal supplier KDS as cited in Table 14: Crystal electrical characteristics (externally
39/41
Page 40
Revision history M41T94
11 Revision history
Table 22. Document revision history
Date Revision Changes
Apr-2002 1 First edition
Adjust graphic (Figure 4 on page 9); fix table text (Table 10 on page 28,
25-Apr-2002 1.1
Table 20 on page 37); adjust characteristics (Table 13 on page 30,
Table 14 on page 30)
03-Jul-2002 1.2
06-Nov-2002 1.3 Correct dimensions (Table 19 on page 36)
26-Mar-2003 1.4 Update test condition (Table 15 on page 31)
28-Apr-2003 2
15-Jun-2004 3
29-Aug-2006 4
09-Nov-2007 5
13-Jan-2009 6
Modify DC, Crystal Electrical Characteristics footnotes, Default Value
table (Table 13 on page 30, Table 14 on page 30, Table 9 on page 27)
New Si changes (Figure 4 on page 9; Table 15 on page 31, Ta bl e 7 on
page 23, Table 8 on page 27, Table 9 on page 27)
Reformatted; added Lead-free information; update characteristics
(Figure 14 on page 25; Table 10 on page 28, Table 13 on page 30,
Table 20 on page 37)
Changed document to new template; amalgamated diagrams in
Features on page 1; updated Package mechanical data in Section 7:
Package mechanical data; small text changes for entire document,
ECOPACK compliant
Added lead-free second level interconnect information to cover page and
Section 7: Package mechanical data; minor formatting changes
throughout document; updated Ta b le 1 0 , footnote 1 in Ta bl e 1 4 ,
Ta bl e 2 0 , 21; addition of Section 10: References.
Updated Ta b le 1 0; updated text in Section 7: Package mechanical data;
added Section 9: Environmental information.
40/41
Page 41
M41T94
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2009 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
41/41
Loading...