Datasheet M48T35AV Datasheet (ST)

M48T35AV

3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM

Features

■ Integrated, ultra low power SRAM, real-time

clock, power-fail control circuit and battery

■ BYTEWIDE

■ BCD coded year, month, day, date, hours,

minutes, and seconds

■ Battery low flag (BOK)

■ Frequency test output for real-time clock

■ Automatic power-fail chip deselect and WRITE

protection

■ WRITE protect voltage

(V

PFD

–M48T35AV: V

2.7 V ≤ V

■ Self-contained battery and crystal in the

CAPHAT

■ SOIC package provides direct connection for a

SNAPHAT
crystal

■ SNAPHAT

replaceable

■ Pin and function compatible with JEDEC

standard 32 Kbit x 8 SRAMs

■ RoHS compliant

– Lead-free second level interconnect

™

RAM-like clock access

= power-fail deselect voltage):

= 3.0 to 3.6 V;

CC

≤ 3.0 V

PFD

™

DIP package

®

housing containing the battery and

®

housing (battery and crystal) is

28

1

PCDIP28

battery/crystal

CAPHAT™

SNAPHAT

battery/crystal

2

8

®

1

SOH28

June 2011 Doc ID 6845 Rev 9 1/29

www.st.com

1

Contents M48T35AV

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 V

noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 17

CC

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/29 Doc ID 6845 Rev 9

M48T35AV List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data . . . . . . . . . . . . . . . . 22

Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
Table 14. SH – 4-pin SNAPHAT
Table 15. SH – 4-pin SNAPHAT

Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 17. SNAPHAT

®

battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

®

housing for 48 mAh battery & crystal, pack. mech. data . . . . . . . 24

®

housing for 120 mAh battery & crystal, pack. mech. data . . . . . . 25

Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

®

, pack. mech. data . . 23

Doc ID 6845 Rev 9 3/29

List of figures M48T35AV

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 22

Figure 15. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
Figure 16. SH – 4-pin SNAPHAT
Figure 17. SH – 4-pin SNAPHAT

Figure 18. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

®

housing for 48 mAh battery & crystal, pack. outline . . . . . . . . . . . 24

®

housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 25

®

, package outline . . . 23

4/29 Doc ID 6845 Rev 9

M48T35AV Description

1 Description

The M48T35AV TIMEKEEPER® RAM is a 32 Kbit x 8 non-volatile static RAM and real-time
clock. The monolithic chip is available in two special packages to provide a highly integrated
battery-backed memory and real-time clock solution.

The M48T35AV is a non-volatile pin and function equivalent to any JEDEC standard
32 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed.

The 28-pin, 600 mil DIP CAPHAT
a long-life lithium button cell in a single package.

™

houses the M48T35AV silicon with a quartz crystal and

The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT

®

housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion.

The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in tape & reel form.

For the 28-lead SOIC, the battery/crystal package part numbers are M4T28-BR12SH1 (48
mAh lithium battery SNAPHAT), M4T32-BR12SH1 (120 mAh lithium battery SNAPHAT),
and M4T32-BR12SH6 (120 mAh lithium battery SNAPHAT, –40 to +85 °C crystal).

Figure 1. Logic diagram

V

CC

15

A0-A14

W

M48T35AV

E

8

DQ0-DQ7

G

V

SS

Doc ID 6845 Rev 9 5/29

AI02797B

Description M48T35AV

Table 1. Signal names

A0-A14 Address inputs

DQ0-DQ7 Data inputs / outputs

E Chip enable

G Output enable

W WRITE enable

V

CC

V

SS

Figure 2. DIP connections

DQ0

DQ2

Figure 3. SOIC connections

Supply voltage

Ground

A14 V

1

A12

2

A7

3

A6

4

A5

5

A4

6

A3

7

M48T35AV

8

A2
A1

9

A0

10
11
12
13
14

SS

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

AI02798B

A7
A6
A5
A4
A3
A2
A1
A0

1

2

3

4

5

6

7

M48T35AV

8

9

10

11

A14 V
A12

DQ0

12

DQ2

SS

13

14

6/29 Doc ID 6845 Rev 9

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

AI02799

M48T35AV Description

Figure 4. Block diagram

32,768 Hz
CRYSTAL

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

V

CC

POWER

V

PFD

8 x 8 BiPORT

SRAM ARRAY

32,760 x 8

SRAM ARRAY

V

SS

A0-A14

DQ0-DQ7

E

W

G

AI01623

Doc ID 6845 Rev 9 7/29

Operation modes M48T35AV

2 Operation modes

As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock
oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 7FF8h-7FFFh.

The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 7FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35AV includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.

The M48T35AV also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 3 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
battery backup switchover voltage (V

), the control circuitry connects the battery which

SO

. As VCC falls below the

CC

maintains data and clock operation until valid power returns.

is out of

CC

Table 2. Operating modes

Mode V

Deselect

WRITE V

READ V

READ V

Deselect VSO to V

Deselect ≤ V

1. See Table 11 on page 21 for details.

Note: X = V

or VIL; VSO = Battery backup switchover voltage.

IH

2.1 READ mode

The M48T35AV is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 15 address inputs defines which one of
the 32,768 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within address access time (t
the E

and G access times are also satisfied.

If the E
enable access time (t

and G access times are not met, valid data will be available after the latter of the chip

CC

3.0 to 3.6 V

(min)

PFD

(1)

SO

) or output enable access time (t

ELQV

E G W DQ0-DQ7 Power

V

IH

IL

IL

(1)

AVQ V

IL

XXXHigh ZCMOS standby

XXXHigh Z

) after the last address input signal is stable, providing that

X X High Z Standby

XVILD

V

IL

V

IH

V

IH

V

IH

GLQV

IN

D

OUT

High Z Active

).

Active

Active

Battery backup
mode

8/29 Doc ID 6845 Rev 9

M48T35AV Operation modes

The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the Address Inputs are changed while E
for output data hold time (t

, the data lines will be driven to an indeterminate state until t

AVQ V

and G remain active, output data will remain valid

) but will go indeterminate until the next address access.

AXQX

AVQ V

. If

Figure 5. READ mode AC waveforms

tAVAV

A0-A14

E

G

DQ0-DQ7

Note: WRITE enable (W

Table 3. READ mode AC characteristics

Symbol Parameter

t

AVAV

t

AVQ V

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).

2. CL = 5 pF.

READ cycle time 100 ns

Address valid to output valid 100 ns

Chip enable low to output valid 100 ns

Output enable low to output valid 50 ns

(2)

Chip enable low to output transition 10 ns

(2)

Output enable low to output transition 5 ns

(2)

Chip enable high to output Hi-Z 50 ns

(2)

Output enable high to output Hi-Z 40 ns

Address transition to output transition 10 ns

) = High.

VAL ID

tAVQV tAXQX

tELQV

tELQX

tGLQX

tGLQV

tGHQZ

VAL ID

tEHQZ

M48T35AV

(1)

Unit–100

Min Max

AI00925

Doc ID 6845 Rev 9 9/29

Operation modes M48T35AV

2.2 WRITE mode

The M48T35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W
earlier rising edge of W
must return high for a minimum of t

or E. The addresses must be held valid throughout the cycle. E or W

from chip enable or t

EHAX

to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t

afterward. G should be kept high during WRITE

WHDX

cycles to avoid bus contention; however, if the output bus has been activated by a low on E
and G

, a low on W will disable the outputs t

WLQZ

Figure 6. WRITE enable controlled, WRITE mode AC waveform

tAVAV

or E. A WRITE is terminated by the

from WRITE enable prior

WHAX

DVW H

prior to the

after W falls.

A0-A14

tAVEL

E

tAVWL

W

tWLQZ

DQ0-DQ7

VAL ID

tAVWH

tWLWH

tWHDX

DATA INPUT

tDVWH

Figure 7. Chip enable controlled, WRITE mode AC waveforms

tAVAV

A0-A14

tAVEL

VAL ID

tAVEH

tELEH

tWHAX

tWHQX

AI00926

tEHAX

E

tAVWL

W

DQ0-DQ7

10/29 Doc ID 6845 Rev 9

tDVEH

tEHDX

DATA INPUT

AI00927

M48T35AV Operation modes

Table 4. WRITE mode AC characteristics

Symbol Parameter

(1)

M48T35AV

Unit

Min Max

t

AVAV

t

AVW L

t

AVE L

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVW H

t

DVEH

t

WHDX

t

EHDX

(2)(3)

t

WLQZ

t

AVW H

t

AVEH

(2)(3)

t

WHQX

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).

2. CL = 5 pF.

goes low simultaneously with W going low, the outputs remain in the high impedance state.

3. If E

WRITE cycle time 100 ns

Address valid to WRITE enable low 0 ns

Address valid to chip enable low 0 ns

WRITE enable pulse width 80 ns

Chip enable low to chip enable high 80 ns

WRITE enable high to address transition 10 ns

Chip enable high to address transition 10 ns

Input valid to WRITE enable high 50 ns

Input valid to chip enable high 50 ns

WRITE enable high to input transition 5 ns

Chip enable high to input transition 5 ns

WRITE enable low to output Hi-Z 50 ns

Address valid to WRITE enable high 80 ns

Address valid to chip enable high 80 ns

WRITE enable high to output transition 10 ns

2.3 Data retention mode

With valid VCC applied, the M48T35AV operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V

Ta bl e 1 0 , and Table 11 on page 21). All outputs become high impedance, and all inputs are

treated as “don't care.”

Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t

. The M48T35AV may respond to transient noise spikes on VCC that reach

F

into the deselect window during the time the device is sampling V
of the power supply lines is recommended.

When V

drops below VSO, the control circuit switches power to the internal battery which

CC

preserves data and powers the clock. The internal button cell will maintain data in the
M48T35AV for an accumulated period of at least 7 years when V
system power returns and V
supply is switched to external V
plus t

(min). E should be kept high as VCC rises past V

rec

WRITE cycles prior to processor stabilization. Normal RAM operation can resume t
V

exceeds V

CC

PFD

CC

(max).

falls within the V

rises above VSO, the battery is disconnected and the power

CC

. Write protection continues until VCC reaches V

CC

PFD

(max), V

(min) window (see Figure 13,

PFD

(min), the

PFD

CC

. Therefore, decoupling

CC

is less than VSO. As

CC

(min) to prevent inadvertent

PFD

fall time

(min)

PFD

after

rec

Doc ID 6845 Rev 9 11/29

Operation modes M48T35AV

Also, as VCC rises, the battery voltage is checked. If the voltage is less than approximately

2.5 V, an internal battery not OK (BOK
power up. If the BOK

flag is set, the first WRITE attempted will be blocked. The flag is

) flag will be set. The BOK flag can be checked after

automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 8
illustrates how a BOK

check routine could be structured.

For more information on battery storage life refer to the application note AN1012.

Figure 8. Checking the BOK

COMPLEMENT BACK

TO SAME ADDRESS

(BATTERY OK)

flag status

POWER-UP

READ DATA

AT ANY ADDRESS

WRITE DATA

READ DATA

AT SAME

ADDRESS AGAIN

IS DATA

COMPLEMENT

OF FIRST

READ?

YES

WRITE ORIGINAL

DATA BACK TO

SAME ADDRESS

(BATTERY LOW)

NO

NOTIFY SYSTEM

OF LOW BATTERY

(DATA MAY BE

CORRUPTED)

CONTINUE

12/29 Doc ID 6845 Rev 9

AI00607

M48T35AV Clock operations

3 Clock operations

3.1 Reading the clock

Updates to the TIMEKEEPER® registers (see Ta ble 5 ) should be halted before clock data is
read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM
array are only data registers and not the actual clock counters, so updating the registers can
be halted without disturbing the clock itself.

Updating is halted when a '1' is written to the READ bit, D6 in the control register 7FF8h. As
long as a '1' remains in that position, updating is halted.

After a halt is issued, the registers reflect the count; that is, the day, date, and the time that
were current at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'

3.2 Setting the clock

Bit D7 of the control register 7FF8h is the WRITE bit. Setting the WRITE bit to a '1,' like the
READ bit, halts updates to the TIMEKEEPER
the correct day, date, and time data in 24-hour BCD format (seeTa bl e 5 ). Resetting the
WRITE bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits
marked as '0' in Ta bl e 5 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next clock update will occur within one second.

See the application note AN923, “TIMEKEEPER
information on century rollover.

®

registers. The user can then load them with

®

rolling into the 21st century” for

3.3 Stopping and starting the oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T35AV is shipped from STMicroelectronics with the STOP bit set to a '1.'
When reset to a '0,' the M48T35AV oscillator starts within 1 second.

Doc ID 6845 Rev 9 13/29

Clock operations M48T35AV

Table 5. Register map

Address

Data

D7 D6 D5 D4 D3 D2 D1 D0

7FFFh 10 years Year Year 00-99

7FFEh 0 0 0 10 M. Month Month 01-12

7FFDh 0 0 10 date Date Date 01-31

7FFCh 0 FT CEB CB 0 Day Century/day 00-01/01-07

7FFBh 0 0 10 hours Hours Hours 00-23

7FFAh 0 10 minutes Minutes Minutes 00-59

7FF9h ST 10 seconds Seconds Seconds 00-59

7FF8h W R S Calibration Control

Function/range

BCD format

Keys:

S = SIGN bit

FT = FREQUENCY TEST bit (must be set to '0' upon power for normal operation)

R = READ bit

W = WRITE bit

ST = STOP bit

0 = Must be set to '0'

CEB = CENTURY ENABLE bit

CB = CENTURY bit

Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century

(dependent upon the initial value set).

When CEB is set to '0,' CB will not toggle. The WRITE bit does not need to be set to write to
CEB.

3.4 Calibrating the clock

The M48T35AV is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T35AV improves to better than
+1/–2 ppm at 25°C.

The oscillation rate of any crystal changes with temperature (see Figure 9 on page 16).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T35AV design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 10 on page 16. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits (D4-D0) in the control register 7FF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the
SIGN bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration

14/29 Doc ID 6845 Rev 9

M48T35AV Clock operations

occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –

2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M48T35AV may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure.

The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the FREQUENCY TEST (FT) bit, the seventh-most
significant bit in the day register is set to a '1,' and D7 of the seconds register is a '0'
(oscillator running), DQ0 will toggle at 512 Hz during a READ of the seconds register. Any
deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the
test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte
for correction.

Note: Setting or changing the calibration byte does not affect the frequency test output frequency.

The FT bit MUST be reset to '0' for normal clock operations to resume. The FT bit is
automatically reset on power-down.

For more information on calibration, see application note AN934, “TIMEKEEPER
Calibration.”

®

3.5 Century bit

Bit D5 and D4 of clock register 7FFCh contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.

Note: The WRITE bit must be set in order to write to the CENTURY bit.

Doc ID 6845 Rev 9 15/29

Clock operations M48T35AV

Figure 9. Crystal accuracy across temperature

ppm

20

0

-20

-40

ΔF

= -0.038 (T - T

-60

-80

-100

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

F

Figure 10. Clock calibration

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

ppm

2

C

T0 = 25 °C

)2 ± 10%

0

°C

AI02124

AI00594B

16/29 Doc ID 6845 Rev 9

M48T35AV Clock operations

3.6 VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass capacitor value of 0.1 µF (as shown in

Figure 11) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from V

to VSS (cathode connected to VCC, anode to VSS). Schottky diode

CC

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.

Figure 11. Supply voltage protection

V

CC

bus. These transients can be reduced if

CC

that drive it to values below VSS by as much as

CC

V

bus. The energy stored in the

CC

CC

0.1µF DEVICE

V

SS

AI02169

Doc ID 6845 Rev 9 17/29

Maximum ratings M48T35AV

4 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 6. Absolute maximum ratings

Symbol Parameter Value Unit

T

A

T

STG

(1)(2)(3)

T

SLD

V

IO

V

CC

I

O

P

D

1. For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.

Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of
wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat
damage to the batteries.

2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid

damaging the crystal.

3. For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above

255 °C must not exceed 30 seconds).

Ambient operating temperature 0 to 70 °C

Storage temperature (VCC off, oscillator off) –40 to 85 °C

Lead solder temperature for 10 seconds 260 °C

Input or output voltages –0.3 to 4.6 V

Supply voltage –0.3 to 4.6 V

Output current 20 mA

Power dissipation 1 W

Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup

mode.

Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT

®

sockets.

18/29 Doc ID 6845 Rev 9

M48T35AV DC and AC parameters

5 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.

Table 7. Operating and AC measurement conditions

Parameter M48T35AV Unit

Supply voltage (VCC) 3.0 to 3.6 V

Ambient operating temperature (T

Load capacitance (CL)50pF

Input rise and fall times ≤ 5ns

Input pulse voltages 0 to 3 V

Input and output timing ref. voltages 1.5 V

Note: Output Hi-Z is defined as the point where data is no longer driven.

) 0 to 70 °C

A

Figure 12. AC measurement load circuit

DEVICE

UNDER

TEST

CL = 50pF
(or 5pF)

CL includes JIG capacitance

1.75V

Table 8. Capacitance

Symbol Parameter

C

IN

C

OUT

1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.

2. At 25 °C, f = 1 MHz.

3. Outputs deselected.

Input capacitance - 10 pF

(3)

Output capacitance - 10 pF

(1)(2)

Min Max Unit

AI02586

Doc ID 6845 Rev 9 19/29

DC and AC parameters M48T35AV

Table 9. DC characteristics

Symbol Parameter Test condition

(1)

M48T35AV

Unit

Min Max

I

LI

(2)

I

LO

I

CC

I

CC1

I

CC2

(3)

V

IL

V

IH

V

OL

V

OH

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).

2. Outputs deselected.

3. Negative spikes of –1 V allowed for up to 10 ns once per cycle.

Input leakage current 0 V ≤ VIN ≤ V

Output leakage current 0 V ≤ V

OUT

≤ V

CC

CC

Supply current Outputs open 30 mA

Supply current (standby) TTL E = V

IH

Supply current (standby) CMOS E = VCC – 0.2 V 2 mA

Input low voltage –0.3 0.8 V

Input high voltage 2.2 VCC + 0.3 V

Output low voltage IOL = 2.1 mA 0.4 V

Output high voltage IOH = –1 mA 2.4 V

Figure 13. Power down/up mode AC waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

tF

tPD

INPUTS

tFB

tDR

tRB

DON'T CARE

±1 µA

±1 µA

2mA

tR

trec

RECOGNIZEDRECOGNIZED

OUTPUTS

VAL ID VAL ID

(PER CONTROL INPUT)

HIGH-Z

20/29 Doc ID 6845 Rev 9

(PER CONTROL INPUT)

AI01168C

M48T35AV DC and AC parameters

Table 10. Power down/up AC characteristics

Symbol Parameter

(1)

Min Max Unit

t

PD

(2)

t

F

t

FB

t

R

t

RB

t

rec

1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).

2. V

PFD

V

CC

3. V

PFD

E or W at VIH before power down 0 µs

V

(max) to V

PFD

(3)

V

(min) to VSS VCC fall time

PFD

V

(min) to V

PFD

VSS to V

V

PFD

(max) to V

passes V

(min) to VSS fall time of less than tFB may cause corruption of RAM data.

PFD

PFD

(min) VCC rise time 1 µs

PFD

(max) to inputs recognized 40 200 ms

(min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after

(min).

(min) VCC fall time 300 µs

PFD

150 µs

(max) VCC rise time 10 µs

PFD

Table 11. Power down/up trip points DC characteristics

Symbol Parameter

V

PFD

V

SO

t

DR

1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).

2. All voltages referenced to V

3. At 25 °C, VCC = 0 V.

4. CAPHAT™ and M4T32-BR12SH1 SNAPHAT® only, M4T28-BR12SH1 SNAPHAT® top tDR = 7 years (typ).

Power-fail deselect voltage 2.7 2.9 3.0 V

Battery backup switchover voltage V

(3)

Expected data retention time 10

.

SS

(1)(2)

Min Typ Max Unit

–100mV V

(4)

PFD

Ye a r s

Doc ID 6845 Rev 9 21/29

Package mechanical data M48T35AV

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Figure 14. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline

B1 B

Note: Drawing is not to scale.

Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data

Symb

Typ Min Max Typ Min Max

A2

A1AL

e1

e3

D

N

E

1

mm inches

C

eA

PCDIP

A 8.89 9.65 0.350 0.380

A1 0.38 0.76 0.015 0.030

A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021

B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012

D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722

e1 2.29 2.79 0.090 0.110

e3 33.02 1.3

eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N28 28

22/29 Doc ID 6845 Rev 9

M48T35AV Package mechanical data

Figure 15. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®,

package outline

Be

N

1

Note: Drawing is not to scale.

Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, pack.

mech. data

Symb

Typ Min Max Typ Min Max

A3.050.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

A2

CP

D

E

H

A

C

eB

LA1 α

SOH-A

mm inches

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

a0°8°0°8°

N28 28

CP 0.10 0.004

Doc ID 6845 Rev 9 23/29

Package mechanical data M48T35AV

Figure 16. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, pack. outline

Note: Drawing is not to scale.

Table 14. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, pack. mech.

data

Symb

Typ Mi n M ax Typ Mi n Max

A9.780.385

A1

A

eA

D

E

B

eB

mm inches

A3

A2

L

SHTK-A

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

24/29 Doc ID 6845 Rev 9

M48T35AV Package mechanical data

Figure 17. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. outline

Note: Drawing is not to scale.

Table 15. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. mech.

data

Symb

Typ Mi n Max Typ M in Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A1

A

eA

D

E

B

eB

mm inches

A3

A2

L

SHTK-A

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Doc ID 6845 Rev 9 25/29

Part numbering M48T35AV

7 Part numbering

Table 16. Ordering information scheme

Example: M48T 35AV –10 MH 1 E

Device type

M48T

Supply voltage and write protect voltage

35AV = V

Speed

–10 = 100 ns (35AV)

Package

PC = PCDIP28

(1)

MH

= 3.0 to 3.6 V; V

CC

= SOH28

= 2.7 to 3.0 V

PFD

Temperature range

1 = 0 to 70°C

Shipping method

For SOH28:

E = Lead-free package (ECOPACK

F = Lead-free package (ECOPACK®), tape & reel

For PCDIP28:

blank = tubes

1. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under
the part number “M4TXX-BR12SHx” in plastic tubes (see Table 17).

Caution: Do not place the SNAPHAT

will drain the lithium button-cell battery.

For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.

Table 17. SNAPHAT

Part number Description Package

M4T28-BR12SH1 Lithium battery (48 mAh) SNAPHAT

M4T32-BR12SH1 Lithium battery (120 mAh) SNAPHAT

M4T32-BR12SH6 Lithium battery (120 mAh) SNAPHAT®, –40 to +85 °C crystal SH

®

battery table

®

), tubes

®

battery package “M4TXX-BR12SH” in conductive foam as it

®

®

SH

SH

26/29 Doc ID 6845 Rev 9

M48T35AV Environmental information

8 Environmental information

Figure 18. Recycling symbols

This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.

Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.

Doc ID 6845 Rev 9 27/29

Revision history M48T35AV

9 Revision history

Table 18. Document revision history

Date Revision Changes

Nov-1999 1 First issue

21-Apr-2000 2 From preliminary data to datasheet

29-May-2000 2.1 t

20-Jul-2001 3

20-May-2002 3.1 Modify reflow time and temperature footnotes (Ta b le 6 )

31-Mar-2003 4 v2.2 template applied; data retention condition updated (Ta b le 1 1)

01-Apr-2004 5 Reformatted; updated with lead-free package information (Ta b l e 6 , 16)

21-Nov-2007 6

23-Mar-2009 7

21-Oct-2010 8 Updated Section 4, Tabl e 1 2; reformatted document.

24-Jun-2011 9

change (Ta ble 1 0 )

FB

Reformatted; temp./voltage info. added to tables (Ta ble 8 , 9, 3, 4, 10,

11); add century bit text

Reformatted document; added lead-free second level interconnect
information to cover page and Section 6: Package mechanical data,
updated Ta b le 1 6 , 17; removed M48T35AY and all references.

Updated Ta b le 6 , Section 6: Package mechanical data; added

Section 8: Environmental information; minor formatting changes.

Updated footnote 1 of Table 6: Absolute maximum ratings; updated

Features and Section 8: Environmental information.

28/29 Doc ID 6845 Rev 9

M48T35AV

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Doc ID 6845 Rev 9 29/29