Datasheet M48T58, M48T58Y Datasheet (ST)

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查询M48T58Y-70MH1供应商

5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER®SRAM

FEATURES SUMMARY

■ INTEGRATED, ULTRA LOW POWER SRAM,

REAL TIMECLOCK, POWER-FAILCONTROL CIRCUIT and BATTERY

■ BYTEWIDE™ RAM-LIKE CLO CK A CCESS

■ BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES, and SE CONDS

■ FREQUENCY TEST OUTPUT FOR REAL

TIME CLOCK

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

= Power-fail Deselect V oltage):

PFD

– M48T58: V

4.5V ≤ V

– M48T58Y: V

4.2V ≤ V

■ SELF-CONTAINED BATTERY and CRYSTAL

IN THE CAPHAT™ DIP PACKAGE

■ PACKAGINGINCLUDESa28-LEADSOICand

SNAPHAT

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAPHAT HOUSING CONTAINING THE BATTERY and CRYSTAL

■ PIN and FUNCTION COMPATIBLE WITH

JEDEC STANDARD 8 Kb x 8 SRAMs

= 4.75 to 5.5V

≤ 4.75V

PFD

= 4.5 to 5.5V

≤ 4.5V

PFD

TOP (to be Ordered Separately)

M48T58

M48T58Y

Figure 1. 28-pin P CDI P, CAPHAT™ Package

PCDIP28 (PC) Battery/Crystal

CAPHAT

Figure 2. 28-pin SOIC Package

SNAPHAT (SH)

Battery/Crystal

SOH28 (MH)

1/27May 2002

Page 2

M48T58, M48T58Y

TABLE OF CONTENTS

SUMMARYDESCRIPTION...........................................................4

LogicDiagram(Figure3.).........................................................4

SignalNames(Table1.)..........................................................4

DIP Connect ions (Figure 4.) .......................................................5

SOIC Connections (Fig ure 5.)......................................................5

BlockDiagram(Figure6.).........................................................5

MAXIMUMRATING.................................................................6

AbsoluteMaximumRatings(Table2.) ...............................................6

DC AND AC PARAMETERS. . ........................................................7

Operating and AC Measurement Conditions (Tabl e 3.) ..................................7

ACMeasurementLoadCircuit(Figure7.).............................................7

Capacitance (Table 4. ) . . . ........................................................7

DCCharacteristics(Table5.) ......................................................8

OPERATIONMODES...............................................................9

Operating Modes (Table 6.)........................................................9

READMode...................................................................10

READModeACWaveforms(Figure8.).............................................10

READModeACCharacteristics(Table7.)...........................................11

WRITEMode..................................................................12

WRITE Enable Controlled, WRITE AC Waveform (Figure 9.).............................12

ChipEnableControlled,WRITEACWaveforms(Figure10.).............................13

WRITEModeACCharacteristics(Table8.)..........................................14

DataRetentionMode............................................................15

PowerDown/UpModeACWaveforms(Figure11.)....................................15

PowerDown/UpACCharacteristics(Table9.)........................................16

PowerDown/UpTripPointsDCCharacteristics(Table10.)..............................16

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M48T58, M 48T 58Y

CLOCKOPERATIONS.............................................................17

Reading the Clock. .............................................................17

RegisterMap(Table11.).........................................................17

SettingtheClock...............................................................17

Stopping and S tarting the Oscillator ................................................17

CalibratingtheClock............................................................18

BatteryLowFlag...............................................................19

CenturyBit....................................................................19

CrystalAccuracyAcrossTemperature(Figure12.) ....................................19

ClockCalibration(Figure13.).....................................................20

Noise And Negative Going Transients. ..........................................20

SupplyVoltageProtection(Figure14.)..............................................20

PARTNUMBERING ...............................................................21

SNAPHATBatteryTable(Table13.)................................................21

PACKAGE MECHANICAL INFORMATION . . . ..........................................22

REVISIONHISTORY...............................................................26

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M48T58, M48T58Y

SUMMARY DESCRIPTION

The M48T58/Y TIMEKEEPER non-volatile static RAM and real time clock . The monolithic chip is available in two special pack agesto providea highly integrated battery backed-up memory and real time clock solution.

The M48T58 /Y is a non-volatile pin and func tion equivalent toany JEDEC s tandard 8Kbx 8 SR AM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

The 28-pin, 600mil DIP CAPHAT™ houses the M48T58/Y silicon with a quartz crystal and a long life lithium button cell in a single package.

RAM is a 8Kb x 8

The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT taining the battery and crystal. The unique design allows the SNAPHAT battery pac k age to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surfacemounting. The S NAPHAT housing is keyed to prevent rev ers e insertion. The S OI C and battery/crystal packages are shipped separatelyin plastic antistatic tubes or in Tape & Reel form.

For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T 28BR12SH” (see Table 13, page 21).

Figure 3. Logic Diagram Table 1. Signal Names

A0-A12 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

Frequency Test Output (Open Drain)

A0-A12

DQ0-DQ7

housing con-

E1 FT

M48T58

M48T58Y

AI01374B

E1 E2 Chip Enable 2

Chip Enable 1

Output Enable WRITE Enable Supply Voltage Ground

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M48T58, M 48T 58Y

Figure 4. DIP Connections Figure 5. SOIC Connections

FT V

A12

5 6

A3 A2 A1 A0

DQ0

M48T58Y 9 10 11

M48T58

DQ2

13 14

Figure 6. Block Diagram

32,768 Hz CRYSTAL

27 26

A11

A10

DQ7

DQ6

DQ5DQ1 DQ4

DQ3V

AI01375B

OSCILLATOR AND

CLOCK CHAIN

FT V

A12

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

1 2 3 4 5 6 7 8 9 10 11

M48T58Y

DQ2

13 14

8 x 8 BiPORT

SRAM ARRAY

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI01376B

W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5DQ1 DQ4 DQ3V

A0-A12

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

POWER

PFD

8184 x 8

SRAM ARRAY

DQ0-DQ7

E1 E2 W G

AI01377C

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Page 6

M48T58, M48T58Y

MAXIMUM RATING

Stressingthedeviceabovetheratinglistedinthe “Absolute Maxim um Ratings” table may cause permanent damage to the dev ice. These are stress ratings only and operation of the device at these or any other conditions a bove those indicated in the Operating sections of this specification is

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

STG

(1,2)

SLD

Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer

than 30 seconds).

2. For SO package: Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOICto avoid damaging SNAPHAT sockets.

Ambient Operating Temperature 0 to 70 °C Storage Temperature (VCCOff, Oscillator Off)

Lead Solder Temperature for 10 seconds 260 °C Input or Output Voltages –0.3 to 7 V Supply Voltage –0.3 to 7 V

Output Current 20 mA Power Dissipation 1 W

not implied. Expos ure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

–40 to 85 °C

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Page 7

DC AND AC PARAMETERS

This s ec t ion summarizes the operating and measurement con ditions, as w ell as t he DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-

Table 3. Operating and AC Measurement Conditions

Parameter M48T58 M48T58Y Unit

M48T58, M 48T 58Y

ment Conditions listed in the relevant tables. Designers should check that the operating condit ions in their projects match the measurement conditions when using t he quoted parameters.

Supply Voltage (V Ambient Operating Temperature (T Load Capacitance (C

)

4.75 to 5.5 4.5 to 5.5 V 0 to 70 0 to 70 °C

100 100 pF Input Rise and Fall Times ≤ 5 ≤ 5ns Input Pulse Voltages 0 to 3 0 to 3 V Input and Output Timing Ref. Voltages 1.5 1.5 V

Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 7. AC Measurement Load Circuit

1.9kΩ

DEVICE UNDER

TEST

1kΩ

OUT

CL = 100pF or 5pF

CL includes JIG capacitance

AI01030

Table 4. Capacitance

Symbol

(3)

OUT

Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.

2. At 25°C, f = 1MHz.

3. Outputs deselected.

Input Capacitance 10 pF Output Capacitance 10 pF

Parameter

(1,2)

Min Max Unit

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M48T58, M48T58Y

Table 5. DC C haracteristics

Symbol Parameter

Test Condition

(1)

M48T58 M48T58Y

Min Max Min Max

Unit

Input Leakage Current

(2)

CC1

CC2

Output Leakage Current Supply Current Outputs open 50 50 mA

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

(3)

Input Low Voltage –0.3 0.8 –0.3 0.8 V

Input High Voltage 2.2

0V ≤ V

E1 E2=V

Output Low Voltage

Output Low Voltage (FT)

Note: 1. ValidforAmbientOperatingTemperature: TA=0to70°C;VCC= 4.75 to 5.5V or 4.5 to 5.5V (except where noted).

Output High Voltage

2. Outputs deselected.

3. Negativespikes of –1V allowed forup to 10ns onceper Cycle.

4. The FT pin is Open Drain.

(4)

≤ V

OUT

E2 = V

=VCC– 0.2V

+ 0.2V

= 2.1mA

IOL= 10mA

=–1mA

±1 ±1 µA ±1 ±1 µA

33mA

+ 0.3

2.2

VCC+0.3

0.4 0.4

0.4 0.4 V

2.4 2.4 V

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Page 9

OPERATION MODES

As Figure 6, page 5 shows, the static memory array and the quartz controlled clock oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to p rovide user acce ssible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BC D format (except for the c entury). Corrections for 28, 29 (leap year valid until 2100), 30, and 31 day m onths are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to th e clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; t hey are memory locations

Table 6. Operating Modes

Mode

Deselect Deselect X WRITE READ READ Deselect

Deselect

Note: X = VIHor VIL;VSO= Battery Back-up Switchover Voltage.

1. See Table 10, page 16 for details.

VSOto V

4.75 to 5.5V or

4.5 to 5.5V

(min)

PFD

(1)

≤ V

E1 E2 G W DQ0-DQ7 Power

(1)

X X X X High Z CMOS Standby X X X X High Z Battery Back-up Mode

X X X High Z Standby

M48T58, M 48T 58Y

consisting of BiPO RT™ READ/write memory cells. The M48T58/Y includes a clock control circuit which updates t he clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.

The M48T58/Y also has its own Power-fail Detect circuit. The control c ircuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When V protects the SRA M, providing a high degree of data security in the midst of unpredictable system operation brought on by low V low the Bat tery Back-up Switchover Voltage

), the control circuitry connects the battery

which maintains data and clock operation until valid power returns.

X X High Z Standby X

is out of tolerance, the circuit write

.AsVCCfalls be-

OUT

High Z Active

Active Active

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Page 10

M48T58, M48T58Y

READ Mode

The M48T58/Y is in the READ Mode whenev er W (WRITE E nable) is high,E1 (Chip Enable 1) islow, and E2 (Chip Enable 2) is high. The unique address specified by the 13 A ddres s Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at th e Data I/O pins within Address Access time (t last address input signal is stable, providing that the E1

, E2, and G access times are also satisfied.

If the E1

,E2andGaccess times arenot met,valid

data will be availableafter thelatter ofthe Chip En-

Figure 8. READ Mod e AC Waveforms

AVQV

)afterthe

able Access times (t Enable Access time (t

E1LQV

GLQV

or t

E2HQV

)orOutput

The state of the eight three-state Data I/O signals is controlled by E 1 tivated before t an indeterminate state until t Inputs are changed while E1

,E2andG. Ifthe outputsare ac-

,the data lineswill be driven to

AVQV

. If the Address

AVQV

, E2 and G remainactive, out put data will remai n valid for Outp ut Data Holdtime (t

)but willgo indeterminate until the

AXQX

next Address Acces s.

tAVAV

A0-A12

DQ0-DQ7

Note: WRITE Enable (W)=High.

VALID

tAVQV tAXQX

tE1LQV

tE1LQX

tE2HQV

tE2HQX

tGLQX

tGLQV

tGHQZ

VALID

tE1HQZ

tE2LQZ

AI00962

10/27

Page 11

Table 7. READ Mode AC Characteristics

Symbol

AVAV

Parameter

READ Cycle Time 70 ns

(1)

M48T58, M 48T 58Y

M48T58/Y

Unit

Min Max

AVQV

E1LQV

E2HQV

GLQV

E1LQX

E2HQX

GLQX

E1HQZ

E2LQZ

GHQZ

AXQX

Note: 1. ValidforAmbientOperatingTemperature: TA=0to70°C;VCC= 4.75 to 5.5V or 4.5 to 5.5V (except where noted).

2. C

Address Valid to Output Valid 70 ns Chip Enable 1 Low to Output Valid 70 ns

Chip Enable 2 High to Output Valid 70 ns Output Enable Low to Output Valid 35 ns

(2)

Chip Enable 1 Low to Output Transition 5 ns

(2)

Chip Enable 2 High to Output Transition 5 ns

(2)

Output Enable Low to Output Transition 5 ns

(2)

Chip Enable 1 High to Output Hi-Z 25 ns

(2)

Chip Enable 2 Low to Output Hi-Z 25 ns

(2)

Output Enable High to Output Hi-Z 25 ns Address Transition to Output Transition 10 ns

= 5pF.

11/27

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M48T58, M48T58Y

WRITE Mode

The M48T58/Y is in the WRITE Mode w henever W and E1 are low and E2 is high. The start of a WRITE is referenced from the latter occurring fallingedgeofW

or E1, or the rising edge of E2 . A

WRITE is terminated by the ea rlier rising edge of

or E1, or the falling edge of E2. T he addresses

W must be held valid throughout the cycle. E1 must return high orE2 lowfor a minimumof t or t

from Chip E nable or t

E2LAX

WHAX

from WRITE

or W

E1HAX

Figure 9. WRITE Enable Controlled, WRITE AC Waveform

Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t the end of WRITE and remain valid for t terward. G clesto avoid bus contention; although, if theoutput bus has been activated by a low on E1 ahighonE2,alowonW t

WLQZ

tAVAV

DVWH

should be kept high during WRITE cy-

will d isable the outputs

after W falls.

prior to

af-

WHDX

and G and

A0-A12

DQ0-DQ7

tAVE1L

tAVE2H

tAVWL

tWLQZ

VALID

tAVWH

tWLWH

tDVWH

tWHAX

tWHQX

tWHDX

DATA INPUT

AI00963

12/27

Page 13

Figure 10. Chip Enable Controlled, WRITE AC Waveforms

tAVAV

M48T58, M 48T 58Y

A0-A12

DQ0-DQ7

VALID

tAVE1H

tAVE1L

tAVE2H tE2HE2L

tAVWL

tE1LE1H

tAVE2L

tDVE1H tDVE2L

tE1HAX

tE2LAX

tE1HDX tE2LDX

DATA INPUT

AI00964B

13/27

Page 14

M48T58, M48T58Y

Table 8. WRITE Mod e AC Characteristics

Symbol

AVAV

AVWL

AVE1L

AVE2H

WLWH

E1LE1H

E2HE2L

WHAX

E1HAX

E2LAX

DVWH

DVE1H

DVE2L

WHDX

E1HDX

E2LDX

(2,3)

WLQZ

AVWH

AVE1H

AVE2L

(2,3)

WHQX

Note: 1. ValidforAmbientOperatingTemperature: TA=0to70°C;VCC= 4.75 to 5.5V or 4.5 to 5.5V (except where noted).

2. C

3. If E1

WRITE Cycle Time 70 ns Address Valid to WRITE Enable Low 0 ns Address Valid to Chip Enable 1 Low 0 ns Address Valid to Chip Enable 2 High 0 ns WRITE Enable Pulse Width 50 ns Chip Enable 1 Low to Chip Enable 1 High 55 ns Chip Enable 2 High to Chip Enable 2 Low 55 ns WRITE Enable High to Address Transition 0 ns Chip Enable 1 High to Address Transition 0 ns Chip Enable 2 Low to Address Transition 0 ns Input Valid to WRITE Enable High 30 ns Input Valid to Chip Enable 1 High 30 ns Input Valid to Chip Enable 2 Low 30 ns WRITE Enable High to Input Transition 5 ns Chip Enable 1 High to Input Transition 5 ns Chip Enable 2 Low to Input Transition 5 ns

Write Enable Low to Output Hi-Z 25 ns Address Valid to WRITE Enable High 60 ns Address Valid to Chip Enable 1 High 60 ns

Address Valid to Chip Enable 2 Low 60 ns WRITE Enable High to Output Transition 5 ns

= 5pF.

goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.

Parameter

(1)

M48T58/Y

Min Max

Unit

14/27

Page 15

Data Retention Mode

With valid V

applied, the M 48T58/Y operates as

a conventional BYTEWIDE™ static RAM. Should the supply volt age decay, the RAM will automatically power-fa il deselect, write protecting itself when V

falls within the V

PFD

(max), V

PFD

(min) window. All outputs become high imp edanc e, and all inputs are treated as “don't care.”

Note: A power failure during a WRITE c ycle may corrupt data at the currently addressed location, but does not jeopardize the r es t o f the RAM's content. At voltages belowV

(min),the usercan be

PFD

assured the memory will be in a write protected state, prov ided theV

fall time is not less than tF.

The M48T58/Y may respond to transient noise spikes on V during the timethe device is sampling V

that reach into the des elect window

. Therefore, decoupling of the p ower supply lines is recommended.

Figure 11. Power Down/Up Mode AC Waveforms

(max)

PFD

(min)

PFD

VSO

M48T58, M 48T 58Y

When V switches power to the internal battery which preserves data and powers the clock. The internal button cell will maint ain data in the M48T58/Y for an accum ulat ed period of at least 7 years when

is less than VSO. As system power returns

and V nected, and the power supply is switched to external V reaches V kept high or E2 low as V to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume t

For more information on Battery Storage Life refer to the Application Note AN1012.

drops below VSO, the control circuit

rises above VSO, the battery is discon-

. Write protection co ntinues until V

REC

(min) plus t

PFD

REC

after VCCexceeds V

(min). E1 should be

rises past V

PFD

(max).

(min)

INPUTS

OUTPUTS

tPD

VALID VALID

(PER CONTROL INPUT)

tFB

tDR

tRB

DON'T CARE

HIGH-Z

tREC

RECOGNIZEDRECOGNIZED

(PER CONTROL INPUT)

AI01168C

15/27

Page 16

M48T58, M48T58Y

Table 9. Power Down/Up AC Chara cteristics

Symbol

(2)

E1 or W at VIHor E2 at VILbefore Power Down V

(max) to V

PFD

(3)

(min) to VSSVCCFall Time

PFD

Parameter

(min) VCCFall Time

PFD

(1)

Min Max Unit

0µs

300 µs

M48T58 10 µs

M48T58Y 10 µs

REC

Note: 1. ValidforAmbientOperatingTemperature: TA=0to70°C;VCC= 4.75 to 5.5V or 4.5 to 5.5V (except where noted).

2. V

3. V

(min) to V

PFD

VSSto V V

(max) to V

PFD

es V

PFD

(min)to VSSfall time of less than tFBmay cause corruption of RAM data.

PFD

(max) to Inputs Recognized

PFD

(min) fall time of less than tFmayresultin deselection/write protectionnot occurring until200µs afterVCCpass-

PFD

(min).

(max) VCCRise Time

PFD

(min) VCCRise Time

10 µs

1µs

40 200 ms

Table 10. Power Down/Up Trip Points DC Characteris tics

Symbol

Note: 1. ValidforAmbientOperatingTemperature: TA=0to70°C;VCC= 4.75 to 5.5V or 4.5 to 5.5V (except where noted).

Power-fail Deselect Voltage

PFD

Battery Back-up Switchover Voltage 3.0 V

(3)

Expected Data Retention Time

2. All voltages referenced to V

3. At 25°C.

Parameter

(1,2)

M48T58 4.5 4.6 4.75 V

M48T58Y 4.2 4.35 4.5 V

Min Typ Max Unit

YEARS

16/27

Page 17

CLOCK OPERATIONS Reading the Clock

Updates to the TIMEKEEPER

registers (see Table 11) should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells inthe RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself.

Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 1FF8h. As long as a '1' remains in that position, updating is halted.

After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'

Setting the Clock

Bit D7 of the Control register (1FF8h) is the WRITEBit.SettingtheWRITEBittoa'1,'likethe READ Bit, halts updates to the TIMEKEEPER

registers. The user can then load them with the

M48T58, M 48T 58Y

correct day, date, and time data in 24 hour BCD format (see Table 11, page 17). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allowsnormal operation to resume. The bits marked as '0' in Table 11, page 17 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE Bit is reset, the next clock update will occur within one second.

See the Application Note AN923 “TIMEKEEPER Rolling Into the 21st Ce ntury” for information on Century Rollover.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the device is going to spend a s ignificant amount of time on the shelf, the oscillator c an be turned off to minimize current drain on t he battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T58/Y is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T58/Y oscillator starts within 1 second.

Table 11. Register Map

Address

D7 D6 D5 D4 D3 D2 D1 D0

1FFFh 10 Years Year Year 00-99 1FFEh 0 0 0 10 M Month Month 01-12 1FFDh BLE BL 10 Date Date Date 01-31 1FFCh 0 FT CEB CB 0 Day Century/Day 0-1/1-7 1FFBh 0 0 10 Hours Hours Hours 00-23 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W R S Calibration Control

Keys: S = SIGN Bit

FT = FREQUENCY TEST Bit R = READ Bit W=WRITEBit ST = STOP Bit

Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).

WhenCEBis set to '0,'CB willnot toggle. The WRITE Bitdoesnot need to be set to write toCEB.

Data

0=Mustbesetto'0' BLE = BatteryLowEnable Bit BL = Battery Low Bit (Read only) CEB = Century Enable Bit CB = Century Bit

Function/Range

BCD Format

17/27

Page 18

M48T58, M48T58Y

Calibrating the Clock

The M48T58/Y is driven by a quart z-controlle d oscillatorwith a nomi nal frequency of32,768 Hz. The devices are tested not to exceed 35ppm (partsper million) oscillator frequency er ror at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T58/Y improves to better than +1/–2 ppm at 25°C.

The oscillation rate of any crystal changes with temperature (see Figure 12, page 19). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” c apac itors. The M48T58/Y design, however, employs periodic counter correction. The cal ibration circuit adds orsubtract s counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 13, page 20. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon t he value loaded into the five calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts s lows the clock down.

The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register 1FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 m inut es in the cycle may, once per m inute, have one second either shorte ned by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 6 4 minute cycle will b e modified; if a binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibration step in the c alibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increment s in the Calibration Byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M48T58/Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate referenc e (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may requi re , even after the final product is p ackaged in a non-user serviceable enc losure. All thedesigner has to do is provide a simple utility that accesses the Calibration Byte.

The second approach is better suited to a m anufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit (D6 in the Day Register) is set to a '1,' and D7 of the Seconds Registeris a '0' (Oscillator Running), The Frequency Test (Pin 1) will toggle at 512Hz. An y deviation f rom 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of

512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiringa –10(WR001010)to be loaded into the Calibration Byte for correction.

The Frequency Test pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10kΩ resistor is recommended inorder to control the rise time.

For more information on calibration, see Application Note AN934, “TIMEK EEPER

Calibration.”

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Page 19

Battery Low Flag

The M48T5 8/Y automatically performs periodic battery voltage monitoring upon power-up and at factory-programmed time intervals of 24 hours (at day rollover) as l ong as the device is powered and the oscillator is running. The B attery Low flag (BL), Bit D6 of the flags Register 1FFDh, will be asserted high if the internal or SNAPHAT

battery is found to be less than approximately 2.5V and the Battery Low Enable (BLE) Bit has beenpreviously set to '1.' The BL flag will remain ac tive until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the nextscheduled 24-hour interval.

If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5V (approximately) , which may be insufficient to maintain data integrity. Data s hould be considered sus pec t and verifiedas c orrect.A fresh battery should be installed.

If a battery low indication is generat ed during the 24-hour interval check, this indicates that the battery is near end of li fe. However, datahas notbeen compromised due to the f ac t that a nominal V

supplied. I n order to insure data integrity during subsequent pe riods of battery back-up mode, it is

M48T58, M 48T 58Y

recommended that the battery be replaced. The SNAPHAT top may be replaced whil e V plied to the device.

Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected.

Note: Battery monitoring is a u se ful technique only when p erformed periodically. The M48T58/Y only monitors the battery when a nomin al V plied to the device. Thus applications which require extensive durations in t he battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.

Century Bit

Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURYBit(CB).SettingCEBtoa'1'willcauseCB to toggle, either from a '0' to '1' or from '1' t o '0' at the turn of the c entury (depending upon its initial state). If CEB is set to a '0,' CB wi ll not toggle.

Note: The WRITE Bit must be set in order to write to the CENTURY Bit.

is ap-

Figure 12. Crystal Accuracy Across Temperatur e

ppm

-20

-40

∆F

= -0.038 (T - T

-60

-80

-100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

ppm

T0 = 25 °C

)2 ± 10%

°C

AI02124

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M48T58, M48T58Y

Figure 1 3. Clock Calibration

NORMAL

POSITIVE CALIBRATION

NEGATIVE CALIBRATION

AI00594B

Noise And Negative Going Transients

transients, including those produced by output

switching, can produc e voltage fluctuations, resultinginspikesontheV

bus. These transients

can be reduced if capac itors are used to store energy which stabilizes the V

bus. The energy

stored in the by pas s capacitors will be released as low going spikes are generated or energy will be absorbed when ov ershoots occur. A bypass capacitor value of 0.1µF (as shown in Figure 14) is recommended in order to prov ide the needed filtering.

In addition to transients that are cause d by normal SRAM operation,power cycling c an generate negative voltage spikes on V below V

by as much as one volt. These negat ive

that drive it to values

spikes can cause data c orruption in the SRAM while in battery backup m ode. To protect from these voltage spikes, it is recommended to connect a schottky diode from V connected to V

, anode to VSS). Schottky diode

to VSS(cathode

1N5817 is recommended for through hole and MBRS120T3 is recom mended for surface mount.

Figure 14. Supply Voltage Protection

0.1µF DEVICE

AI02169

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M48T58, M 48T 58Y

PART NUMBERING

Table 12. Ordering Information Scheme

Example: M48T 58 –70 MH 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

(1)

=VCC= 4.75 to 5.5V; V

58 58Y = V

= 4.5 to 5.5V; V

Speed

–70 = 70ns

Package

PC = PCDIP28

(2)

= SOH28

= 4.5 to 4.75V

PFD

= 4.2 to 4.5V

PFD

Temperature Range

1 = 0 to 70°C

Shipping Method for SOIC

blank = Tubes TR = Tape & Reel

Note: 1. The M48T58 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.

2. The SOIC package (SOH28) requires the battery package (SNAPHAT “M4TXX-BR12SH ” in plastic tube or “M4TXX-BR12SHTR” in Ta pe & Reel form.

Caution: Do not place the SNAPHAT battery package “M4TXX-BR00SH” in conductive foam as it will drain the lithium button-cell

battery.

) which is ordered separately under the part number

For a list ofavailable options (e.g.,Speed, Package) or for furtherinformation on any aspect of thisdevice, please contact the ST Sales Office nearest to you.

Table 13. SNAPHAT Battery Table

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

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M48T58, M48T58Y

PACKAGE MECHANICAL INFORMATION

Figure 15. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline

A1AL

B1 B e1

Note: Drawing is not to scale.

PCDIP

Table 14. PCDIP28 – 28-pin Plastic DIP, battery C APHAT, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 8.89 9.65 0.350 0.380 A1 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021

mm inches

B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430

eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N28 28

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M48T58, M 48T 58Y

Figure 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Out line

LA1 α

SOH-A

Note: Drawing is not to scale.

Table 15. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

mm inches

A 3.05 0.120

A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 1.27 – – 0.050 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N28 28

CP 0.10 0.004

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M48T58, M48T58Y

Figure 17. SH – 4-pin SNAPHATHousing for 48mAh Battery & Crystal , Package Outline

SHTK-A

Note: Drawing is not to scale.

Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal,Package Mechanical Data

Symb

Typ Min Max Typ Min Max

mm inches

A 9.78 0.385

A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015

B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

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M48T58, M 48T 58Y

Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

SHTK-A

Note: Drawing is not to scale.

Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

mm inches

A 10.54 0.415

A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015

B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

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M48T58, M48T58Y

REVISION HISTORY

Table 18. Docum ent Revision History

Date Revision Details

July 1999 First Issue

07/27/00

06/04/01 Reformatted; temperature information added (Tables 5, 7, 8, 9, 10) 07/31/01 Formatting changes from recent document review findings 05/20/02 Modify reflow time and temperature footnotes (Table 2)

Century Bit and Battery Low Flag Paragraphs added Power Down/Up AC Characteristics Table and Waveforms changed (Table 9, Figure 11)

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M48T58, M 48T 58Y

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licenseis granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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