Features
VN5E010AH
10 mΩ high-side driver with analog current sense
for automotive applications
Max supply voltage V
Operating voltage range V
Typ. ON-state resistance R
Current limitation (typ) I
OFF-state supply current I
1. Typical value with all loads connected
■ General
– Inrush current active management by
power limitation
– Very low standby current
– 3 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
– Very low current sense leakage
■ Diagnostic functions
– Proportional load current sense
– High current sense precision for wide
current range
– Current sense disable
– OFF-state open-load detection
– Output short to V
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
■ Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Overtemperature shut down with
autorestart (thermal shutdown)
detection
CC
CC
CC
ON
LIMH
S
41 V
4.5 V to 28 V
10 mΩ
85 A
(1)
2 µA
– Reverse battery protection with self switch
on of the Power MOSFET
(see Figure 32)
– Electrostatic discharge protection
Applications
■ All types of resistive, inductive and capacitive
loads
■ Suitable as LED driver
Description
The VN5E010AH is a single-channel high-side
driver manufactured in the ST proprietary
VIPower M0-5 technology and housed in the tiny
HPAK package. The VN5E010AH is designed to
drive 12 V automotive grounded loads delivering
protection, diagnostics and easy 3 V and 5 V
CMOS compatible interface with any
microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with autorestart and overvoltage active clamp. A dedicated
analog current sense pin is associated with every
output channel in order to provide ehnanced
diagnostic functions including fast detection of
overload and short-circuit to ground through
power limitation indication, overtemperature
indication, short-circuit to Vcc diagnosis and
ON- and OFF-state open-load detection.
The current sensing and diagnostic feedback of
the whole device can be disabled by pulling the
CS_DIS pin high to allow sharing of the external
sense resistor with other similar devices
.
October 2009 Doc ID 15984 Rev 2 1/37
www.st.com
1
Contents VN5E010AH
Contents
1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 26
3.4 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 27
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 HPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 ECOPACK
5.2 HPAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 HPAK suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37 Doc ID 15984 Rev 2
VN5E010AH List of tables
List of tables
Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 13 V, Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Current sense (8 V < V
Table 10. Open load detection (8 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. HPAK mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
< 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Doc ID 15984 Rev 2 3/37
List of figures VN5E010AH
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) not in scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Open-load OFF-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. I
OUT/ISENSE
Figure 10. Maximum current sense ratio drift vs. load current
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. OFF-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Short to V
Figure 16. T
evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
J
Figure 17. OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. ON-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. ON-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. High-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. Low-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 34. Maximum turn-off current versus inductance
Figure 35. PC board
Figure 36. Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 28
Figure 37. HPAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 38. Thermal fitting model of a single-channel HSD in HPAK
Figure 39. HPAK package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 40. HPAK suggested pad layout
Figure 41. HPAK tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 42. HPAK tape and reel (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
vs. I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CC
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUT
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(1)
. . . . . . . . . . . . . . . . . . . . . . . . 29
4/37 Doc ID 15984 Rev 2
VN5E010AH Block diagram and pin configuration
1 Block diagram and pin configuration
Figure 1. Block diagram
V
CC
Signal Clamp
Control & Diagnostic
IN
CS_
DIS
CS
Undervoltage
LOGIC
Table 1. Pin functions
DRIVER
Over
temp.
V
SENSEH
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
Limitation
Current
Current
Sense
Power
Clamp
V
ON
Limitation
OFF State
Open load
Reverse
Battery
Protection
OUT
GND
Name Function
V
CC
OUT Power output
Battery connection
(1)
GND Ground connection
IN
CS
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
Analog CS pin, delivers a current proportional to the load current
CS_DIS Active high CMOS compatible pin, to disable the CS pin
1. Pins 1 and 7 must be externally tied together.
Doc ID 15984 Rev 2 5/37
Block diagram and pin configuration VN5E010AH
Figure 2. Configuration diagram (top view) not in scale
1234 567
IN
GND
OUT
Table 2. Suggested connections for unused and not connected pins
Vcc
CS CS_DIS
OUT
Connection / pin CS OUT IN CS_DIS
Floating Not allowed X X X
To ground
Through 1 kΩ
resistor
Through 22 kΩ
resistor
Through 10 kΩ
resistor
Through 10 kΩ
resistor
6/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
2 Electrical specifications
Figure 3. Current and voltage conventions
I
S
V
CC
I
I
SENSE
V
SENSE
OUT
V
OUT
I
CSD
V
CSD
I
IN
V
IN
CS_DIS
IN
GND
I
GND
OUT
CS
V
CC
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may
cause permanent damage to the device . These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
program and other relevant quality document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
-V
I
OUT
-I
I
CSD
V
CSENSE
E
DC supply voltage 41 V
CC
Reverse DC supply voltage 16 V
CC
DC output current Internally limited A
Reverse DC output current 20 A
OUT
I
DC input current -1 to 10 mA
IN
DC current sense disable input current -1 to 10 mA
Current sense maximum voltage (V
Maximum switching energy (single pulse)
MAX
(L = 2.2 mH; R
I
= I
OUT
limL
L
(Typ.))
= 0 Ω; V
= 13.5 V; T
BAT
CC
> 0)
jstart
= 150 °C;
V
- 41
CC
+V
CC
645 mJ
V
V
Doc ID 15984 Rev 2 7/37
Electrical specifications VN5E010AH
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Electrostatic discharge
(human body model: R = 1.5 kΩ; C = 100 pF)
4000
2000
4000
5000
5000
V
V
V
V
V
V
V
ESD
ESD
T
–IN
–CS
–CS_DIS
–OUT
–V
CC
Charge device model (CDM-AEC-Q100-011) 750 V
Junction operating temperature -40 to 150 °C
T
j
Storage temperature -55 to 150 °C
stg
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter Max. value Unit
R
thj-case
R
thj-amb
Thermal resistance junction-case 0.55 °C/W
Thermal resistance junction-ambient 67.7 °C/W
8/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
2.3 Electrical characteristics
Values specified in this section are for 8 V < V
< 28 V, -40 °C < Tj < 150 °C, unless
CC
otherwise specified.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
USDhyst
R
R
ON-Rev
V
clamp
I
L(off)
Operating supply voltage 4.5 13 28 V
CC
Undervoltage shutdown 3.5 4.5 V
USD
Undervoltage shutdown
hysteresis
ON-state resistance
ON
R
in reverse battery
DSON
condition
Clamp voltage I
I
Supply current
S
OFF-state output current
I
= 6 A; Tj = 25 °C 10
OUT
= 6 A; Tj = 150 °C 20
OUT
I
= 6 A; V
OUT
V
= -13 V; I
CC
= 25 °C
T
j
= 20 mA; I
CC
OFF-state: V
= V
V
IN
ON-state: V
= 0 A
I
OUT
V
= V
IN
= 25 °C
T
j
= V
V
IN
= 125 °C
T
j
OUT
OUT
OUT
= 5 V; Tj = 25 °C 13
CC
= -6 A;
OUT
= 0 A 41 46 52 V
OUT
= 13 V; Tj = 25 °C;
CC
= V
CC
= 0 V
SENSE
= 13 V; V
IN
= 5 V;
= 0 V; VCC = 13 V;
= 0 V; VCC = 13 V;
0.5 V
10 mΩ
2 5 µA
1.5 3 mA
00.01 3
05
mΩI
µA
Table 6. Switching (V
= 13 V, Tj = 25 °C)
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
R
= 2.2 Ω
Turn-on delay time
Turn-off delay time
Turn-on voltage
/dt)
on
slope
Turn-off voltage
/dt)
off
slope
(dV
(dV
t
d(on)
t
d(off)
OUT
OUT
Switching energy
W
ON
losses at turn-on
)
(t
won
Switching energy
W
OFF
losses at turn-off
)
(t
woff
L
(see Figure 6)
= 2.2 Ω
R
L
(see Figure 6)
R
= 2.2 Ω - (see Figure 26)- V/µs
L
= 2.2 Ω - (see Figure 28)- V/µs
R
L
= 2.2 Ω
R
L
(see Figure 6)
= 2.2 Ω
R
L
(see Figure 6)
-40 -µs
-28 -µs
-2 -mJ
-0.6 -mJ
Doc ID 15984 Rev 2 9/37
Electrical specifications VN5E010AH
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
I
V
I
IH
V
I(hyst)
V
ICL
V
CSDL
I
CSDL
V
CSDH
I
CSDH
V
CSD(hyst)
V
CSCL
Table 8. Protection and diagnostics
Low-level input voltage 0.9 V
IL
Low-level input current VIN = 0.9 V 1 µA
IL
High-level input voltage 2.1 V
IH
High-level input current V
= 2.1 V 10 µA
IN
Input hysteresis voltage 0.25 V
I
= 1 mA 5.5 7
Input clamp voltage
IN
= -1 mA -0.7
I
IN
Low-level CS_DIS voltage 0.9 V
Low-level CS_DIS current V
= 0.9 V 1 µA
CSD
High-level CS_DIS voltage 2.1 V
High-level CS_DIS current V
= 2.1 V 10 µA
CSD
CS_DIS hysteresis voltage 0.25 V
I
= 1 mA 5.5 7
CS_DIS clamp voltage
CSD
= -1 mA -0.7
I
CSD
(1)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
= 13 V 60 85 120
I
T
T
V
DEMAG
V
1. To ensure long term reliability under heavy overload or short-circuit conditions, protection and related
Short-circuit current
limH
Short-circuit current
I
limL
during thermal cycling
Shutdown temperature 150 175 200 °C
TSD
T
Reset temperature TRS + 1 TRS + 5 °C
R
Thermal reset of status 135 °C
T
RS
Thermal hysteresis
HYST
(T
TSD
- TR)
Turn-off output voltage
clamp
Output voltage drop
ON
limitation
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles
CC
5 V < V
V
TR < Tj < T
I
OUT
< 28 V 120
CC
=13 V;
CC
TSD
= 2 A; V
IN
L = 6 mH
= 0.5 A;
I
OUT
= -40 °C to 150 °C
T
j
= 0;
V
CC
- 41 V
A
21 A
7°C
CC
- 46 V
- 52 V
CC
25 mV
10/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
Table 9. Current sense (8 V < V
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
K
dK1/K
K
dK2/K
K
dK3/K
I
0
1
2
3
OUT/ISENSE
I
OUT/ISENSE
(1)
Current sense ratio drift
1
I
OUT/ISENSE
(1)
Current sense ratio drift
2
I
OUT/ISENSE
(1)
Current sense ratio drift
3
< 18 V)
CC
I
= 0.25 A; V
OUT
SENSE
Tj = -40 °C to 150 °C
= 25 °C to 150 °C
T
j
I
= 6 A; V
OUT
= -40 °C to 150 °C
T
j
= 25 °C to 150 °C
T
j
I
= 6 A; V
OUT
=0V;
V
CSD
SENSE
SENSE
Tj = -40 °C to 150 °C
I
= 10 A; V
OUT
SENSE
Tj = -40 °C to 150 °C
= 25 °C to 150 °C
T
j
I
= 10 A; V
OUT
V
= 0 V;
CSD
= -40 °C to 150 °C
T
j
I
= 25 A; V
OUT
= -40 °C to 150 °C
T
j
= 25 °C to 150 °C
T
j
I
= 25 A; V
OUT
= 0 V;
V
CSD
SENSE
SENSE
SENSE
Tj = -40 °C to 150 °C
= 0.5 V
= 0.5 V
= 0.5 V;
= 4 V
= 4 V;
= 4 V
= 4 V;
3000
7410
12000
3000
7410
11600
5350
5510
6740
6740
8500
7745
-15 15 %
5850
5800
6570
6570
7690
7195
-11 11 %
5915
5850
6420
6420
7000
6755
-8 8 %
I
SENSE0
Analog sense leakage
current
= 0 A; V
I
OUT
V
= 5 V; V
CSD
= -40 °C to 150 °C
T
j
I
= 0 A; V
OUT
= 0 V; V
V
CSD
= -40 °C to 150 °C
T
j
I
= 2 A; V
OUT
= 5 V; VIN = 5 V;
V
CSD
SENSE
=0 V;
IN
SENSE
= 5 V;
IN
SENSE
= 0 V;
= 0 V;
= 0 V;
01
02
µA
1
Tj = -40 °C to 150 °C
Open load ON-state
I
OL
current detection
threshold
V
SENSE
V
SENSEH
I
SENSEH
Max analog sense
output voltage
Analog sense output
(2)
voltage in fault condition
Analog sense output
(2)
current in fault condition
VIN = 5 V, 8 V < V
= 5 µA
I
SENSE
I
= 18 A; R
OUT
V
V
CC
CC
= 13 V; R
= 13 V; V
SENSE
SENSE
SENSE
< 18 V
CC
580mA
= 3.9 kΩ 5V
= 3.9 kΩ 8V
= 5 V 9 mA
Doc ID 15984 Rev 2 11/37
Electrical specifications VN5E010AH
Table 9. Current sense (8 V < V
< 18 V) (continued)
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
DSENSE1H
t
DSENSE1L
t
DSENSE2H
Δ
t
DSENSE2H
t
DSENSE2L
Delay response time
from falling edge of
CS_DIS pin
Delay response time
from rising edge of
CS_DIS pin
Delay response time
from rising edge of
IN pin
Delay response time
between rising edge of
output current and rising
edge of current sense
Delay response time
from falling edge of
IN pin
V
1.5 A < I
I
(see Figure 4)
V
1.5 A < I
I
(see Figure 4)
V
1.5 A < I
I
(see Figure 4)
V
I
I
I
V
1.5 A < I
I
(see Figure 4)
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
= 90% of I
OUT
OUTMAX
SENSE
SENSE
< 4 V,
< 25 A
OUT
= 90% of I
SENSE max
< 4 V,
< 25 A
OUT
=10% of I
SENSE max
< 4 V,
< 25 A
OUT
=90% of I
SENSE max
<4V,
= 90% of I
SENSEMAX,
OUTMAX
= 3A (see Figure 7)
< 4 V,
< 25 A
OUT
=10% of I
SENSE max
50 100 µs
520µs
270 600 µs
310 µs
100 250 µs
1. Parameter guaranteed by design, it is not tested.
2. Fault condition includes: power limitation, over-temperature and open load OFF-state detection.
Table 10. Open load detection (8 V < V
CC
< 18 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Open-load OFF-state
V
voltage detection
OL
= 0 V 2
V
IN
threshold
See
Figure 5
4V
Output short-circuit to
detection delay at
t
DSTKON
V
CC
See Figure 5 180 1200 µs
turn-off
I
L(off2)r
I
L(off2)f
OFF-state output
current at V
OUT
OFF-state output
current at V
OUT
= 4 V
= 2 V
= 0 V; V
V
IN
V
rising from 0 V to 4 V
OUT
= 0 V; V
V
IN
V
falling from VCC to 2 V
OUT
SENSE
SENSE
= 0 V
= V
SENSEH
-120 90 µA
;
-50 90 µA
Delay response from
= 4 V; V
t
d_vol
output rising edge to
V
SENSE
rising edge in
open-load
V
OUT
V
SENSE
= 90% of V
IN
= 0 V
SENSEH
20 µs
12/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
Figure 4. Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
CURRENT SENSE
t
DSENSE2H
t
DSENSE1L
t
DSENSE1H
t
DSENSE2L
Figure 5. Open-load OFF-state delay timing
OUTPUT STUCK TO V
V
IN
V
CS
Figure 6. Switching characteristics
V
OUT
dV
OUT
/dt
(on)
t
Won
80%
t
r
10%
CC
V
t
DSTKON
t
Woff
90%
t
f
OUT
V
SENSEH
> V
dV
OL
OUT
/dt
(off)
t
INPUT
t
d(on)
t
d(off)
t
Doc ID 15984 Rev 2 13/37
Electrical specifications VN5E010AH
Figure 7. Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
V
IN
Δ
t
DSENSE2H
t
I
OUT
I
SENSE
90% I
OUTMAX
I
OUTMAX
I
SENSEMAX
t
90% I
SENSEMAX
t
Figure 8. Output voltage drop limitation
V
cc-Vout
T
=150oC
j
V
on
V
on/Ron(T)
T
=25oC
j
T
=-40oC
j
I
out
14/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
Figure 9. I
I
OUT/ISENSE
12800
11600
10400
9200
8000
6800
5600
4400
3200
2000
OUT/ISENSE
vs. I
OUT
A
B
C
D
E
-2 1 4 7 10131619222528
I
(A)
OUT
A: Max, Tj = -40 °C to 150 °C
B: Max, T
C: Typical, T
= 25 °C to 150 °C
j
= -40 °C to 150 °C
j
D: Min, T
E: Min, Tj = -40 °C to 150 °C
= 25 °C to 150 °C
j
Figure 10. Maximum current sense ratio drift vs. load current
(1)
dK/K (%)
20
15
A
10
5
0
-5
-10
B
-15
-20
4 7 10 13 16 19 22 25 28
I
OUT
(A)
A: Max, Tj = -40 °C to 150 °C B: Min, Tj = -40 °C to 150 °C
1. Parameter guaranteed by design; it is not tested.
Doc ID 15984 Rev 2 15/37
Electrical specifications VN5E010AH
Table 11. Truth table
Conditions Input Output SENSE (V
Normal operation
CSD
L
H
L
H
0
Nominal
= 0 V)
(1)
Overtemperature
Undervoltage
Overload
Short-circuit to GND
(power limitation)
Open load OFF-state
(with external pull-up)
Short-circuit to V
CC
(external pull-up
disconnected)
Negative output voltage
clamp
1. If the V
and external circuit.
is high, the SENSE output is at a high-impedance, its potential depends on leakage currents
CSD
L
H
L
H
H
L
L
L
L
X
0
V
SENSEH
0
0
Nominal
(no power limitation)
H
Cycling
V
SENSEH
(power limitation)
L
H
LHV
L
H
L
L
H
H
0
V
SENSEH
SENSEH
V
SENSEH
< Nominal
LL 0
16/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
Table 12. Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test pul s e
Test levels
(1)
Number of
pulses or
III IV Min. Max.
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
1 -75 V -100 V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37 V +50 V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω
3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 -6 V -7 V 1 pulse 100 ms, 0.01 Ω
(2)
5b
1. The above test levels must be considered referred to VCC= 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40 V maximum referred to ground.
Table 13. Electrical transient requirements (part 2)
ISO 7637-2:
+65 V +87 V 1 pulse 400 ms, 2 Ω
Test level results
2004(E)
Test pul s e
III IV
1C C
2a C C
3a C C
3b C C
4C C
(1)
5b
CC
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 14. Electrical transient requirements (part 3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 15984 Rev 2 17/37
Electrical specifications VN5E010AH
2.4 Waveforms
Figure 11. Normal operation
INPUT
INPUT
Nominal load Nominal load
Nominal load Nominal load
I
I
OUT
OUT
V
V
SENSE
SENSE
V
V
CS_DIS
CS_DIS
Figure 12. Overload or short to GND
INPUT
INPUT
I
>
I
>
LimH
LimH
I
I
OUT
OUT
V
V
SENSE
SENSE
V
V
CS_DIS
CS_DIS
Power Limitation
Power Limitation
I
I
LimL
LimL
Thermal cycling
Thermal cycling
>
>
18/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
Figure 13. Intermittent overload
INPUT
INPUT
I
I
OUT
OUT
V
V
SENSE
SENSE
V
V
CS_DIS
CS_DIS
I
I
LimH
LimH
V
V
SENSEH
SENSEH
>
>
>
>
Overload
Overload
I
I
LimL
LimL
Nominal load
>
>
Nominal load
Figure 14. OFF-state open-load with external circuitry
INPUT
INPUT
V
> V
V
> V
OUT
OL
OUT
OL
V
V
OL
OL
t
t
DSTK(on)
DSTK(on)
V
V
SENSEH
SENSEH
>
>
V
V
SENSE
SENSE
V
V
OUT
OUT
I
I
OUT
OUT
V
V
CS_DIS
CS_DIS
Doc ID 15984 Rev 2 19/37
Electrical specifications VN5E010AH
Figure 15. Short to V
V
V
OUT
OUT
I
I
OUT
OUT
V
V
CS_DIS
CS_DIS
CC
Resistive
Resistive
Short to V
Short to V
V
V
OL
OL
t
t
DSTK(on)
DSTK(on)
CC
CC
Hard
Hard
Short to V
Short to V
V
> V
V
> V
OUT
OUT
t
t
DSTK(on)
DSTK(on)
OL
OL
CC
CC
Figure 16. TJ evolution in overload or short to GND
INPUT
INPUT
Self-limitation of fast thermal transients
Self-limitation of fast thermal transients
T
T
J_START
J_START
T
T
J
J
I
>
I
>
LimH
LimH
I
I
OUT
OUT
Power Limitation
Power Limitation
T
T
TSD
TSD
T
T
R
R
< I
< I
T
T
HYST
HYST
LimL
LimL
20/37 Doc ID 15984 Rev 2
VN5E010AH Electrical specifications
2.5 Electrical characteristics curves
Figure 17. OFF-state output current Figure 18. High-level input current
Iloff [ nA]
6000
5000
4000
3000
2000
1000
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Iih [uA]
5
4.5
4
Vin= 2.1V
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Figure 19. Input clamp voltage Figure 20. Low-level input voltage
Vicl [V]
7
6.8
6.6
Iin= 1mA
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Vil [V ]
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Figure 21. High-level input voltage Figure 22. Input hysteresis voltage
Vih [V]
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Vihyst [V]
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Doc ID 15984 Rev 2 21/37
Electrical specifications VN5E010AH
V
Figure 23. ON-state resistance vs. T
Ron [m Ohm ]
80
70
case
Figure 24. ON-state resistance vs. V
Ron [m Ohm ]
30
25
60
50
40
Iout= 6A
Vcc= 13V
30
20
15
10
20
10
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
5
0
0 5 10 15 20 25 30 35 40
Vcc [V]
Figure 25. Undervoltage shutdown Figure 26. Turn-on voltage slope
Vusd [V]
16
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
(dV out /dt)On [V/m s]
1000
900
800
700
Vcc= 13V
Rl= 13 Ω
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
CC
Tc= 150°C
Tc= 125°C
Tc= 25°C
Tc= -40°C
Figure 27. I
LIMH
Vs. T
case
Ilim h [A]
100
90
cc= 13V
80
70
60
50
40
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
22/37 Doc ID 15984 Rev 2
Figure 28. Turn-off voltage slope
(dVout/dt)Off [V/ms]
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Vcc= 13V
Rl= 13 Ω
Tc [°C]
VN5E010AH Electrical specifications
Figure 29. High-level CS_DIS voltage Figure 30. CS_DIS clamp voltage
Vcsdh [V]
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Vcsdcl [V]
10
9
8
Iin= 1mA
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Figure 31. Low-level CS_DIS voltage
Vcsdl [V]
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc [°C]
Doc ID 15984 Rev 2 23/37
Application information VN5E010AH
3 Application information
Figure 32. Application schematic
+5V
MCU
R
prot
R
prot
R
prot
R
SENSE
C
ext
CS_DIS
IN
CS
45V
3.1 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
max DC rating. The same applies if the device is subject to transients on the VCC line
CC
that are greater than the ones shown in the ISO 7637-2 2004 (E) table.
GND
V
20V
CC
OUT
D
ld
3.2 MCU I/Os protection
When negative transients are present on the VCC line, the control pins is pulled negative to
approximatly -1.5 V. ST suggests to insert a resistor (R
microcontroller I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
-V
CCpeak
Calculation example:
For V
CCpeak
75 Ω ≤ R
= - 1.5 V; I
≤ 240 kΩ.
prot
latchup
Recommended values: R
24/37 Doc ID 15984 Rev 2
≥ 20 mA; V
=10 kΩ, C
prot
/ I
latchup
≤ R
OHμC
EXT
≤ (V
prot
≥ 4.5 V
=10 nF.
) in line to prevent the
prot
- VIH ) / I
OHμC
IHmax
VN5E010AH Application information
3.3 Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
● Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a know ratio K
The current I
external resistor R
minimum (see parameter V
can be easily converted to a voltage V
SENSE
. Linearity between I
SENSE
SENSE
in Table 9: Current sense (8 V < V
OUT
and V
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8 V < V
● Diagnostic flag in fault conditions, delivering a fixed voltage V
maximum current I
SENSEH
in case of the following fault conditions (refer to
< 18 V)).
CC
Table 11: Truth table):
– Power limitation activation
–Overtemperature
–Short to V
in OFF-state
CC
– Open load in OFF-state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high-impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
.
X
SENSE
by means of an
SENSE
is ensured up to 5 V
CC
SENSEH
< 18 V)). The
up to a
Figure 33. Current sense and diagnostic
V
PU_CMD
R
I
Loff2r
I
Loff2f
R
PU
PU
Load
PD
V
BAT
V
CC
INPUTn
Main MOSn
+
-
V
GND
OL
OUTn
41V
I
OUT/KX
I
SENSEH
V
V
SENSE
CS_DIS
CURRENT
SENSEn
R
PROT
To uC ADC
R
SENSE
Overtemperature
OL OFF
Pwr_Lim
SENSEH
Doc ID 15984 Rev 2 25/37
Application information VN5E010AH
(
)
3.3.1 Short to VCC and OFF-state open-load detection
Short to V
A short-circuit between V
V
SENSEH
during the ON-state depending on the nature of the short-circuit.
OFF-state open-load with external circuitry
CC
and output is indicated by the relevant current sense pin set to
CC
during the device OFF-state. Small or no current is delivered by the current sense
Detection of an open load in off mode requires an external pull-up resistor R
the output to a positive supply voltage V
It is preferable V
to be switched off during the module standby mode in order to avoid the
PU
PU
.
connecting
PU
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull-down resistor R
connected between output and GND is mandatory to
PD
avoid misdetection in case of floating outputs in OFF-state (see Figure 33: Current sense
and diagnostic).
R
must be selected in order to ensure V
PD
OUT < VOLmin
unless pulled-up by the external
circuitry:
Equation 2
minOLf)off(LPD
R
≤ 22 kΩ is recommended.
PD
OUT
OFF_upPull
−
VVIRV
22=<⋅=
For proper open load detection in OFF-state, the external pull-up resistor must be selected
according to the following formula:
Equation 3
()
V
OUT
−
For the values of V
OLmin ,VOLmax, IL(off2)r
< VCC < 18 V)).
26/37 Doc ID 15984 Rev 2
=
ON_upPull
IRRVR
⋅⋅−⋅
r)off(LPDPUPUPD
()
and I
RR
+
PDPU
(see Table 10: Open load detection (8 V
L(off2)f
maxOL
VV
42=>
VN5E010AH Application information
3.4 Maximum demagnetization energy (V
Figure 34. Maximum turn-off current versus inductance
100
A
B
C
10
I (A)
1
0, 1 1 10 100L (mH)
=13.5 V)
CC
(1)
A
B
C
VIN, I
: T
: T
: T
= 150 °C (single pulse)
jstart
= 100 °C (repetitive pulse)
jstart
= 125 °C (repetitive pulse)
jstart
L
Demagnetization Demagnetization Demagnetization
t
1. Values are generated with R
In case of repetitive pulses, T
the temperature specified above for curves A and B.
=0 Ω.
L
(at beginning of each demagnetization) of every pulse must not exceed
jstart
Doc ID 15984 Rev 2 27/37
Package and PC board thermal data VN5E010AH
4 Package and PC board thermal data
4.1 HPAK thermal data
Figure 35. PC board
1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm,
PCB thickness =1.8 mm, Cu thickness = 70 µm, Copper areas: from minimum pad lay-out to 8 cm
Figure 36. R
thj-amb
(1)
vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
70
65
2
).
60
55
50
45
40
35
30
0246810
PCB Cu heatsink area (cm^2)
28/37 Doc ID 15984 Rev 2
VN5E010AH Package and PC board thermal data
Figure 37. HPAK thermal impedance junction ambient single pulse
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=foot print
10
1
0.1
0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 38. Thermal fitting model of a single-channel HSD in HPAK
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
(1)
Doc ID 15984 Rev 2 29/37
Package and PC board thermal data VN5E010AH
Equation 4: pulse calculation formula
where δ = tP/T
Table 15. Thermal parameter
Area/island (cm2)Footprint48
R1 (°C/W) 0.01
R2 (°C/W) 0.15
R3 (°C/W) 0.5
R4 (°C/W) 8
R5 (°C/W) 28 22 12
R6 (°C/W) 31 25 16
C1 (W.s/°C) 0.005
C2 (W.s/°C) 0.05
C3 (W.s/°C) 0.1
C4 (W.s/°C) 0.4
Z
THδ
RTHδ Z
THtp
1 δ–()+⋅=
C5 (W.s/°C) 0.8 1.4 3
C6 (W.s/°C) 3 6 9
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VN5E010AH Package and packing information
5 Package and packing information
5.1 ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
5.2 HPAK mechanical data
Figure 39. HPAK package dimension
.
Doc ID 15984 Rev 2 31/37
Package and packing information VN5E010AH
Table 16. HPAK mechanical data
Data book mm
Ref. dim
Nom. Min. Max.
A 2.20 2.40
A1 0.90 1.10
A2 0.03 0.23
b 0.40 0.55
b4 5.20 5.40
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
D1 5.10
E 6.40 6.60
E1 5.20
e0.85
e1 1.60 1.80
e2 3.30 3.50
e3 5.00 5.20
H 9.35 10.10
L1
(L1) 2.80
L2 0.80
L4 0.60 1.00
R0.20
V2 0° 8°
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VN5E010AH Package and packing information
5.3 HPAK suggested land pattern
Figure 40. HPAK suggested pad layout
(1)
All dimensions are in mm.
1. The land pattern proposed is not intended to overrule User's PCB design, manufacturing and soldering
process rules
Doc ID 15984 Rev 2 33/37
Package and packing information VN5E010AH
5.4 Packing information
The devices can be packed in tube or tape and reel shipments (see Table 17: Device
summary).
Figure 41.
HPAK tube shipment (no suffix)
A
Base q.ty 75
C
Bulk q.ty 3000
Tube length (± 0.5) 532
A 6
B 21.3
C (± 0.1) 0.6
B
All dimensions are in mm.
Figure 42. HPAK tape and reel (suffix “TR”)
REEL DIMENSIONS
All dimensions are in mm.
Base q.ty 2500
Bulk q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 16
Tape hole spacing P0 (± 0.1) 4
Component spacing P 8
Hole diameter D (± 0.1/-0) 1.5
Hole diameter D1 (min) 1.5
Hole position F (± 0.05) 7.5
Compartment depth K (max) 2.75
Hole spacing P1 (± 0.1) 2
All dimensions are in mm.
34/37 Doc ID 15984 Rev 2
Top
cover
tape
End
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Start
No componentsNo components Components
500mm min
VN5E010AH Order codes
6 Order codes
Table 17. Device summary
Order codes
Package
Tube Tape and reel
6 pins HPAK VN5E010AH-E VN5E010AHTR-E
Doc ID 15984 Rev 2 35/37
Revision history VN5E010AH
7 Revision history
Table 18. Document revision history
Date Revision Changes
2-Jul-2009 1 Initial release.
02-Oct-2009 2 Updated Table 10: Open load detection (8 V < VCC < 18 V).
36/37 Doc ID 15984 Rev 2
VN5E010AH
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