Memory module temperature sensor
Features
■ Temperature sensor compliant with JEDEC
JC42.4
Temperature sensor
■ Temperature sensor resolution:
0.25°C (typ)/LSB
■ Temperature sensor accuracy:
– ± 1°C from +75°C to +95°C
– ± 2°C from +40°C to +125°C
– ± 3°C from –40°C to +125°C
■ ADC conversion time: 125 ms (max)
■ Supply voltage: 2.7 V to 3.6 V
■ Maximum operating supply current: 200 µA
■ Hysteresis selectable set points from: 0, 1.5, 3,
6.0°C
■ Ambient temperature sensing range: –40°C to
125°C
■ Supports bus timeout
STTS424
TDFN8 (DN)
2 mm x 3 mm (max height 0.80 mm)
Two-wire bus
■ 2-wire SMBus/I
■ Supports up to 400 kHz transfer rate
■ Does not initiate clock stretching
2
C - compatible serial interface
Packages
■ 2 mm x 3 mm TDFN8, height: 0.80 mm (max)
RoHS compliant, halogen-free
■
a. Compliant to JEDEC MO-229, WCED-3
April 2009 Rev 6 1/36
(a)
www.st.com
1
Contents STTS424
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Device type identifier (DTI) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1 A0, A1, A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 V
2.2.3 SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.4 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.5 EVENT
2.2.6 V
(ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
(open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DD
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 SMBus/I2C communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 SMBus/I
3.3 SMBus/I
2
C slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
C AC timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 SMBus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1 Alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.2 Critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.2 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.3 Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.4 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.5 Event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.1 Temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Temperature trip point registers (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 Manufacturer ID register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 Device ID and device revision ID register (read-only) . . . . . . . . . . . . . . . 25
2/36
STTS424 Contents
5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3/36
List of tables STTS424
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. AC SMBus and I
Table 3. Temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Legend for Figure 9: Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. Manufacturer ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. Device ID and device revision ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 20. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 22. DC and AC characteristics - temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 23. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN) . . . . . . . . . . 30
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25. Parameters for landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
C compatibility timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4/36
STTS424 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. TDFN8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. SMBus/I
Figure 5. SMBus/I
Figure 6. SMBus/I
Figure 7. SMBus/I
Figure 8. Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN) . . . . . . . . . . 30
Figure 11. Device topside marking information (TDFN-8L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
C write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
C write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 11
2
C write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 12
2
C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5/36
Description STTS424
1 Description
The STTS424 is targeted for DIMM modules in mobile personal computing platforms
(laptops), server memory modules, and other industrial applications. The thermal sensor
(TS) in the STTS424 is fully compliant with the JEDEC specification which defines memory
module thermal sensors requirements for mobile platforms.
The TS provides space as well as cost savings for mobile and server platform dual inline
memory modules (DIMM) manufacturers as it is packaged in the compact 2 mm x 3 mm
(height 0.80 mm) 8-lead TDFN package which is compliant to JEDEC MO-229, variation
WCED-3.
The temperature sensor includes a band gap-based temperature sensor and 10-bit analogto-digital converter (ADC) which monitor and digitize the temperature to a resolution of up to
0.25°C. The typical accuracies over these temperature ranges are:
● ±3°C (max) over the full temperature measurement range of –40°C to 125°C
● ±2°C in the +40°C to +125°C temperature range and
● ±1°C in the +75°C to +95°C temperature range
The temperature sensor in the STTS424 is specified for operating at supply voltages from
2.7 V to 3.6 V. Operating at 3.3 V, the supply current is 100 µA (typ).
The on-board sigma delta ADC converts the measured temperature to a digital value that is
calibrated in °C. For Fahrenheit applications, a lookup table or conversion routine is
required. The STTS424 is factory-calibrated and requires no external components to
measure temperature.
The digital temperature sensor component has user-programmable registers that provide
the capabilities for DIMM temperature-sensing applications. The open drain event output pin
is active when the monitoring temperature exceeds a programmable limit, or it falls above or
below an alarm window. The user has the option to set the event output as a critical
temperature output. This pin can be configured to operate in either a comparator mode for
thermostat operation or in interrupt mode.
6/36
STTS424 Serial communications
2 Serial communications
The STTS424 has a simple 2-wire SMBus/I2C-compatible digital serial interface which
allows the user to access the data in the temperature register at any time. It communicates
via the serial interface with a master controller which operates at speeds of up to 400 kHz. It
also gives the user easy access to all of the STTS424 registers in order to customize device
operation.
2.1 Device type identifier (DTI) code
The JC42.4 temperature sensor has its own unique I2C address, which ensures that there
are no compatibility or data translation issues. The DTI code is the unique 4-bit address,
'0011'.
The full I
and A2 pins. This allows up to 8 unique addresses, hence 8 STTS424 devices may be
connected on the same bus.
Figure 1. Logic diagram
2
C address consists of the unique DTI code and 3 bits determined by the A0, A1,
V
DD
SDA
(1)
EVENT
(1)
SCL
STTS424
V
SS
AI12947
1. SDA and EVENT are open drain.
Table 1. Signal names
A
2
A
1
A
0
Pin Symbol Description Direction
1 A0 Serial bus address selection pin. Can be tied to V
2 A1 Serial bus address selection pin. Can be tied to V
3 A2 Serial bus address selection pin. Can be tied to V
4V
SS
5SDA
Supply ground
(1)
Serial data Input/output
or VDD. Input
SS
or VDD. Input
SS
or VDD. Input
SS
6 SCL Serial clock Input
(1)
7 EVENT
Event output pin. Open drain and active-low. Output
8V
1. SDA and EVENT are open drain.
DD
Supply power (2.7 V to 3.6 V)
See Section 2.2: Pin descriptions on page 9 for details.
7/36
Serial communications STTS424
Figure 2. TDFN8 connections (top view)
1. SDA and EVENT are open drain.
Figure 3. Block diagram
Temperature
Sensor
A0
A1
A2
GND
ADC
Capability
Register
Configuration
Register
Temperature
Register
V
1
2
3
4
8
7
6
5
8
V
DD
DD
EVENT
SCL
(1)
SDA
AI12262
Logic Control
Comparator
Timing
Upper
Register
Lower
Register
Critical
Register
(1)
EVENT
7
Address Pointer
Register
A0
1
A1
2
A2
3
8/36
SMBus/I2C
Interface
V
SS
4
Manufacturer
ID
Device ID/
Revision
SCL
SDA
6
5
AI12948
STTS424 Serial communications
2.2 Pin descriptions
2.2.1 A0, A1, A2
A2, A1, and A0 are selectable address pins for the 3 LSBs of the I2C interface address.
They can be set to V
2.2.2 VSS (ground)
This is the reference for the power supply. It must be connected to system ground.
2.2.3 SDA (open drain)
This is the serial data input/output pin.
2.2.4 SCL
This is the serial clock input pin.
2.2.5 EVENT (open drain)
This output pin is open drain and active-low and functions as an alert interrupt.
or GND to provide 8 unique address selections.
DD
2.2.6 VDD (power)
This is the supply voltage pin, and ranges from +2.7 V to +3.6 V.
9/36
Operation STTS424
3 Operation
The STTS424 TS continuously monitors the ambient temperature and updates the
temperature data registers at least eight times per second. Temperature data is latched
internally by the device and may be read by software from the bus host at any time.
The SMBus/I
same bus. This means that up to 8 memory modules can be supported, given that each
module has one such slave device address slot.
After initial power-on, the configuration registers are set to the default values. The software
can write to the configuration register to set bits per the bit definitions in Section 3.1:
SMBus/I
3.1 SMBus/I2C communications
The registers in this device are selected by the pointer register. At power-up, the pointer
register is set to “00”, which is the capability register location. The pointer register latches
the last location it was set to. Each data register falls into one of three types of user
accessibility:
1. Read-only
2. Write-only and
3. WRITE/READ same address.
2
C slave address selection pins allow up to 8 such devices to co-exist on the
2
C communications.
A WRITE to this device will always include the address byte and the pointer byte. A WRITE
to any register other than the pointer register, requires two data bytes.
Reading this device is achieved in one of two ways:
● If the location latched in the pointer register is correct (most of the time it is expected
that the pointer register will point to one of the read temperature registers because that
will be the data most frequently read), then the READ can simply consist of an address
byte, followed by retrieval of the two data bytes.
● If the pointer register needs to be set, then an address byte, pointer byte, repeat start,
and another address byte will accomplish a READ.
The data byte transfers the MSB first. At the end of a READ, this device can accept either an
acknowledge (ACK) or no acknowledge (No ACK) status from the master. The No ACK
status is typically used as a signal for the slave that the master has read its last byte. This
device subsequently takes up to 125 ms to measure the temperature.
Note: STTS424 does not initiate clock stretching which is an optional I
2
C bus feature.
10/36
STTS424 Operation
Figure 4. SMBus/I2C write to pointer register
SCL
SDA
Figure 5. SMBus/I
SCL
SDA
Master
SCL
(continued)
19
1199
0 1 1 A2 A1 A0 R/W 0 0 0 0 0 D2 D1 D0
0
Start
by
Master
Address Byte
ACK
by
STTS424
2
C write to pointer register, followed by a read data word
1199
0 1 1 A2 A1 A0 R/W 0 0 0 0 0 D2 D1 D0
0
Start
by
Address Byte
ACK
by
STTS424
1919
Pointer Byte
Pointer Byte
ACK
by
STTS424
AI12264
ACK
by
STTS424
SDA
(continued)
Repeat
Start
by
Master
0 0 1 1 A2 A1 A0
Address Byte
R/W
ACK
by
STTS424
D14D15
D13
D12
D9D10D11
D7 D6 D5 D4 D3 D2 D1 D0
D8
MSB Data Byte LSB Data Byte
ACK
by
Master
No ACK
by
Master
Stop
Cond.
by
Master
AI12265
11/36
Operation STTS424
Figure 6. SMBus/I2C write to pointer register, followed by a write data word
SCL
SDA
SCL
(continued)
SDA
(continued)
1199
0
0 1 1 A2 A1 A0 R/W 0 0 0 0 0 D2 D1 D0
Start
by
Master
Address Byte
1919
D12
D14D15
D13
MSB Data Byte LSB Data Byte
STTS424
D9D10D11
ACK
by
D8
ACK
by
STTS424
Pointer Byte
D7 D6 D5 D4 D3 D2 D1 D0
3.2 SMBus/I2C slave sub-address decoding
ACK
by
STTS424
No ACK
by
STTS424
Stop
Cond.
by
Master
AI14012
The physical address for the TS is binary 0011A2A1A0RW, whereas A2, A1, and A0
are the three slave sub-address pins, and the LSB “RW” is the READ/WRITE flag.
3.3 SMBus/I2C AC timing consideration
In order for this device to be both SMBus- and I2C-compatible, it complies to a subset of
each specification. These interoperability requirements which will enable this device to coexist with devices on either an SMBus or an I
● The SMBus minimum clock frequency is required.
● The 300 ns SMBus data hold time (THD:DAT) is required (see Figure 7 and Ta bl e 2 o n
page 13).
● The SMBus time-out is maximum 50 ms.
Note: Since the voltage levels are specified only within 3.3 V ±10%, there are no compatibility
concerns with the SMBus/I
2
C DC specifications.
2
C bus:
12/36
STTS424 Operation
Figure 7. SMBus/I2C timing diagram
tR
tF
tHIGH
tSU:DAT
C compatibility timings
S
tSU:STA
tSU:STO
P
A12266
V
IH
SCL
V
IL
tBUF
V
IH
SDA
V
IL
SP
Table 2. AC SMBus and I
tLOW
tHD:STA
tHD:DAT
2
Symbol Parameter Min Max Units
t
BUF
t
HD:STA
t
SU:STA
t
HIGH
t
LOW
t
F
t
R
t
SU:DAT
t
HD:DAT
t
SU:STO
f
SCL
t
timeout
1. For a restart condition, or following a WRITE cycle
Bus free time between stop (P) and start (S) conditions 1.3 – µs
Hold time after (repeated) start condition. After this period,
the first clock cycle is generated.
(1)
Repeated start condition setup time 1.3 – µs
0.6 – µs
Clock high period 0.6 – µs
Clock low period 1.3 – µs
Clock/data fall time – 300 ns
Clock/data rise time – 300 ns
Data setup time 100 – ns
Data hold time 300 – ns
Stop condition setup time 0.6 – µs
SMBUS/I2C clock frequency 10 400 kHz
Bus timeout 25 50 ms
3.4 SMBus timeout
The STTS424 supports the SMBus timeout feature. If the host holds SCL low for more than
25 ms, the STTS424 resets and releases the bus. This feature is turned on by default.
13/36
Temperature sensor registers STTS424
4 Temperature sensor registers
The temperature sensor component is comprised of various user-programmable registers.
These registers are required to write their corresponding addresses to the Pointer register.
They can be accessed by writing to their respective addresses (see Ta bl e 3 ). Pointer
register Bits 7-3 must always be written to '0' (see Ta bl e 4 ). This must be maintained, as not
setting these bits to '0' may keep the device from performing to specifications.
The main registers include:
● Capability register (read-only)
● Configuration register (read/write)
● Temperature register (read-only)
● Temperature trip point registers (r/w), including
– Alarm temperature upper boundary,
– Alarm temperature lower boundary, and
– Critical temperature.
● Manufacturer ID register format
● Device ID and device revision ID register format
Note: See Table 5 on page 15 for pointer register selection bit details.
Table 3. Temperature sensor registers summary
Address (Hex) Register name Power-on default
Not applicable Address pointer Undefined
Table 4. Pointer register format
MSB LSB
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00000P2P1P0
00 Capability B-grade only 0x002F
01 Configuration 0x0000
02 Alarm temperature upper boundary trip 0x0000
03 Alarm temperature lower boundary trip 0x0000
04 Critical temperature trip 0x0000
05 Temperature Undefined
06 Manufacturer’s ID 0x104A
07 Device ID/revision 0x0101
Pointer/register select bits
14/36
STTS424 Temperature sensor registers
Table 5. Pointer register select bits (type, width, and default values)
P2 P1 P0 Name Register description
0 0 0 CAPA Thermal sensor capabilities B-grade only 16 R 00 2F
0 0 1 CONF Configuration 16 R/W 00 00
0 1 0 UPPER Alarm temperature upper boundary 16 R/W 00 00
0 1 1 LOWER Alarm temperature lower boundary 16 R/W 00 00
1 0 0 CRITICAL Critical temperature 16 R/W 00 00
1 0 1 TEMP Temperature 16 R 00 00
1 1 0 MANU Manufacturer ID 16 R 104A
1 1 1 ID Device ID/revision 16 R 01 01
Width
(bits)
Type
(R/W)
Default
4.1 Capability register (read-only)
This 16-bit register is read-only, and provides the TS capabilities which comply with the
minimum JEDEC 424.4 specifications (see Ta bl e 6 and Table 7 on page 16). The STTS424
provides temperatures at 0.25 resolution (10-bit).
state
(POR)
4.1.1 Alarm window trip
The device provides a comparison window with an upper temperature trip point in the alarm
upper boundary register, and a lower trip point in the alarm lower boundary register. When
enabled, the event output will be triggered whenever entering or exiting (crossing above or
below) the alarm window.
4.1.2 Critical trip
The device can be programmed in such a way that the event output is only triggered when
the temperature exceeds the critical trip point. The critical temperature setting is
programmed in the critical temperature register. When the temperature sensor reaches the
critical temperature value in this register, the device is automatically placed in comparator
mode, which means that the critical event output cannot be cleared by using software to set
the clear event bit.
15/36
Temperature sensor registers STTS424
Table 6. Capability register format
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
RFU RFU RFU RFU RFU RFU RFU RFU
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RFU RFU V
C
Table 7. Capability register bit definitions
HV
TRES1 TRES0
Wider
range
Higher
precision
Bit Definition
Basic capability
0
– 0 = Alarm and critical trips turned OFF.
– 1 = Alarm and critical trips turned ON.
Accuracy
– 0 = Accuracy ±2°C over the active range and ±3°C over the monitoring range
1
(C - Grade).
– 1 = High accuracy ±1°C over the active range and ±2°C over the monitoring range
(B - Grade).
Range width
2
– 0 = Values lower than 0°C will be clamped and represented as binary value '0'.
– 1 = Temperatures below 0°C can be read and the Sign bit will be set accordingly.
Temperature resolution
4:3
– 01 = This 10-bit value is fixed for STTS424, providing temperatures at 0.25°C resolution
(LSB).
) High voltage support for A0 (pin 1)
(V
HV
5
– 1 = STTS424 supports a voltage up to 10 volts on the A0 pin (default).
Reserved
15:6
These values must be set to '0'.
Alarm and
critical trips
16/36
STTS424 Temperature sensor registers
4.2 Configuration register (read/write)
The 16 bit Configuration register stores various configuration modes that are used to set up
the sensor registers and configure according to application and JEDEC 42.4 requirements
(see Table 8 on page 17 and Table 9 on page 18).
4.2.1 Event thresholds
All event thresholds use hysteresis as programmed in register address 0x01 (bits 10 through
9) to be set when they de-assert.
4.2.2 Interrupt mode
The interrupt mode allows an event to occur where software may write a '1' to the clear
event bit (bit 5) to de-assert the event Interrupt output until the next trigger condition occurs.
4.2.3 Comparator mode
Comparator mode enables the device to be used as a thermostat. READs and WRITEs on
the device registers will not affect the event output in comparator mode. The event signal will
remain asserted until temperature drops outside the range or is re-programmed to make the
current temperature “out of range”.
4.2.4 Shutdown mode
The STTS424 features a shutdown mode which disables all power-consuming activities
(e.g. temperature sampling operations), and leaves the serial interface active. This is
selected by setting shutdown bit (bit 8) to '1'. In this mode, the devices consume the
minimum current (I
Note: Bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'.
The device may be enabled for continuous operation by clearing bit 8 to '0'. In shutdown
mode, all registers may be read or written to. Power recycling will also clear this bit and
return the device to continuous mode as well.
Table 8. Configuration register format
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
RFU RFU RFU RFU RFU Hysteresis Hysteresis
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Critical
lock bit
Alarm
lock bit
), as shown in Table 22 on page 28.
SHDN
Clear
event
Event output
status
Event output
control
Critical
event only
Event
polarity
Shutdown
mode
Event
mode
17/36
Temperature sensor registers STTS424
Table 9. Configuration register bit definitions
Bit Definition
Event mode
0
– 0 = Comparator output mode (this is the default)
– 1 = Interrupt mode; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Event polarity
1
– 0 = Active-low (this is the default).
– 1 = Active-high; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Critical event only
– 0 = Event output on alarm or critical temperature event (this is the default).
2
– 1 = Event only if the temperature is above the value in the critical temperature register; when the alarm
window lock bit is set, this bit cannot be altered until it is unlocked.
Event output control
3
– 0 = Event output disabled (this is the default).
– 1 = Event output enabled; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Event status (read-only)
– 0 = Event output condition is not being asserted by this device.
4
(1)
– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.
Clear event (write-only)
5
–0 = No effect
(2)
– 1 = Clears the active Event in Interrupt mode.
Alarm window lock bit
– 0 = Alarm trips are not locked and can be altered (this is the default).
6
– 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with a
single WRITE, and do not require double WRITEs.
Critical trip lock bit
– 0 = Critical trip is not locked and can be altered (this is the default).
7
– 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with a
single WRITE, and do not require double WRITEs.
Shutdown mode
– 0 = TS is enabled (this is the default).
8
– 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No
event conditions will be asserted; when either of the lock bits is set, this bit cannot be altered until it is
unlocked. However, it can be cleared at any time.
(3)
Hysteresis enable
(see Figure 8 and Ta b le 1 0 )
– 00 = Hysteresis is disabled.
10:9
– 01 = Hysteresis is enabled at 1.5°C.
– 10 = Hysteresis is enabled at 3°C.
– 11 = Hysteresis is enabled at 6°C.
1. The actual incident causing the event can be determined from the read temperature register. Interrupt events can be
cleared by writing to the clear event bit (writing to this bit will have no effect on overall device functioning.
2. Writing to this register has no effect on overall device functioning in comparator mode. When read, this bit will always return
a logic '0' result.
3. Hysteresis is also applied to the EVENT
pin functionality. When either of the lock bits is set, these bits cannot be altered.
18/36
STTS424 Temperature sensor registers
Figure 8. Hysteresis
T
H
T
L
Below Window bit
Above Window bit
1. TU = Value stored in the alarm temperature upper boundary trip register.
= Value stored in the alarm temperature lower boundary trip register.
2. T
L
3. Hys = Absolute value of selected hysteresis.
Table 10. Hysteresis as applied to temperature movement
TH - HYS
TL - HYS
AI12270
Below alarm window bit Above alarm window bit
Temperature
slope
Sets Falling T
Temperature
threshold
- HYS Rising T
L
Clears Rising T
Temperature
slope
L
Falling TH - HYS
Temperature
threshold
H
19/36
Temperature sensor registers STTS424
4.2.5 Event output pin functionality
The EVENT pin is an open drain output and requires a pull-up resistor to VDD on the system
motherboard or incorporated into the master controller.
Figure 9 shows the defined outputs of the EVENT
change.
The event outputs can be programmed to be configured as either a comparator output or as
an interrupt. This is done by enabling the output control bit (bit 3) and setting the event mode
bit (bit 0). The output pin polarity can also be specified as active-high or active-low by setting
the event polarity bit (bit 1).
When the hysteresis bit (bits 10 and 9) is enabled, hysteresis may be used to sense
temperature movement around trigger points. For example, when using the “above alarm
window” bit (temperature register bit 14, see Table 12 on page 22) and hysteresis is set to
3°C, as the temperature rises, bit 14 is set (bit 14 = 1). The temperature is above the alarm
window and the temperature register contains a value that is greater than the value set in
the alarm temperature upper boundary register (see Table 15 on page 23).
If the temperature decreases, bit 14 will remain set until the measured temperature is less
than or equal to the value in the alarm temperature upper boundary register minus 3°C (see
Figure 8 on page 19 and Table 10 on page 19 for details.
Similarly, when using the “below alarm window” bit (temperature register bit 13, see Table 12
on page 22) will be set to '0'. The temperature is equal to or greater than the value set in the
alarm temperature lower boundary register (see Table 16 on page 24). As the temperature
decreases, bit 13 will be set to '1' when the value in the temperature register is less than the
value in the alarm temperature lower boundary register minus 3°C (see Figure 8 on page 19
and Table 10 on page 19 for details).
The device will retain the previous state when entering the shutdown mode. If the device
enters the shutdown mode while the EVENT
due to the additional event output pull-down current.
correspondent to the temperature
pin is low, the shutdown current will increase
If in interrupt mode and the temperature reaches the critical temperature, the EVENT
remains asserted until the temperature drops below the critical limit minus hysteresis.
Note: Hysteresis is also applied to the EVENT
or 7) is set, these bits cannot be altered.
20/36
pin
pin functionality. When either of the lock bits (bits 6
STTS424 Temperature sensor registers
Figure 9. Event output boundary timings
T
- T
CRIT
T
UPPER
HYS
- T
T
LOWER
HYS
- T
HYS
T
T
UPPER
T
LOWER
Comparator
Interrupt
S/W Int. Clear
Event Output (active-low)
CRIT
Critical
T
T
A
T
LOWER
- T
HYS
UPPER
- T
HYS
12133574642
Table 11. Legend for Figure 9: Event output boundary timings
Event output T
bits
A
AI12271
Note Event output boundary conditions
Comparator Interrupt Critical 15 14 13
1T
2T
3T
4T
5T
6T
When T
7
of the configuration register (interrupt mode) is ignored.
A
A
A
≥ T
≥ T
≥ T
< T
A
CRIT
≥ T
A
LOWER
LOWER - THYS
> T
A
UPPER
UPPER - THYS
≥ T
A
CRIT
CRIT - THYS
and TA < T
CRIT - THYS
HLH000
LLH001
LLH010
HLH000
LLL110
LHH010
, the event output is in comparator mode and bit 0
Note: Systems that use the active high mode for event output must be wired pont-to-point between
the STTS424 and the sensing controller. Wire-OR configurations should not be used with
active high EVENT since any device pulling the event output signal low will mask the other
devices on the bus. Also note that the normal state of EVENT
in active high mode is a ‘0’
which will constantly draw power through the pull-up resistor.
21/36
Temperature sensor registers STTS424
4.3 Temperature register (read-only)
This 16-bit, read-only register stores the temperature measured by the internal band gap TS
as shown inTa bl e 1 2. The STTS424 meets the JEDEC JC42.4 mandatory 0.25°C resolution
requirement. When reading this register, the MSBs (bit 15 to bit 8) are read first, and then
the LSBs (bit 7 to bit 0) are read. The result is the current-sensed temperature. The data
format is 2s complement with one LSB = 0.25°C. The MSB has a 128°C resolution.
The trip status bits represent the internal temperature trip detection, and are not affected by
the status of the event or configuration bits (e.g. event output control or clear event). If
neither of the above or below values are set (i.e. both are 0), then the temperature is exactly
within the user-defined alarm window boundaries.
4.3.1 Temperature format
The 16-bit value used in the trip point set and temperature read-back registers is 2s
complement, with the LSB equal to 0.0625°C (see Tab le 1 3 ). For example:
1. a value of 019Ch will represent 25.75°C,
2. a value of 07C0h will represent 124°C, and
3. a value of 1E74h will represent –24.75°C
The 0.0625°C resolution is optional. Supporting a resolution of at least 0.25°C is mandatory.
All unused resolution bits will be set to zero. The MSB will have a resolution of 128°C. The
STTS424 supports the 0.25°C/LSB only.
The upper 3 bits indicate trip status based on the current temperature, and are not affected
by the event output status.
Table 12. Temperature register format
Bit
15
Above
critical
input
0 0 0 0 011111000 0 0 0 07C0 h
0 0 0 1 110110000 0 0 0 1C00 h
1. See Table 13 for explanation.
Sign
MSB
Bit
14
Above
(1)
alarm
(1)
window
Flag bits Example hex value of 07C0 corresponds to 124°C (10-bit)
Flag bits Example hex value of 1C00 corresponds to –40°C (10-bit)
Bit
13
Below
alarm
window
Bit12Bit11Bit10Bit9Bit8Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit
(1)
Temperature 0 0
LSB
0
22/36
STTS424 Temperature sensor registers
Table 13. Temperature register bit definitions
Bit Definition with hysteresis = 0
Below (temperature) alarm window
13
– 0 = Temperature is equal to or above the alarm window lower boundary temperature.
– 1 = Temperature is below the alarm window.
Above (temperature) alarm window
14
– 0 = Temperature is equal to or below the alarm window upper boundary temperature.
– 1 = Temperature is below the alarm window.
Above critical trip
15
– 0 = Temperature is below the critical temperature setting.
– 1 = Temperature is equal to or above the critical temperature setting.
4.4 Temperature trip point registers (r/w)
The STTS424 alarm mode registers provide for 11-bit data in 2s compliment format. The
data provides for one LSB = 0.25°C. All unused bits in these registers are read as '0'.
The STTS424 has three temperature trip point registers (see Tab l e 1 4):
● Alarm temperature upper boundary threshold (Tab l e 1 5),
● Alarm temperature lower boundary threshold (Ta bl e 1 6), and
● Critical temperature trip point value (Ta bl e 1 7 ).
Note: If the upper or lower boundary threshold values are being altered in-system, all interrupts
should be turned off until a known state can be obtained to avoid superfluous interrupt
activity.
Table 14. Temperature trip point register format
Default
state
(POR)
P2 P1 P0 Name Register description
Width
(bits)
Type
(R/W)
0 1 0 UPPER Alarm temperature upper boundary 16 R/W 00 00
0 1 1 LOWER Alarm temperature lower boundary 16 R/W 00 00
1 0 0 CRITICAL Critical temperature 16 R/W 00 00
Table 15. Alarm temperature upper boundary register format
Sign
MSB
LSB
Bit15Bit14Bit13Bit12Bit11Bit10Bit9Bit8Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit
0 0 0 Alarm window upper boundary temperature 0 0
0
23/36
Temperature sensor registers STTS424
Table 16. Alarm temperature lower boundary register format
Sign
MSB
Bit15Bit14Bit13Bit12Bit11Bit10Bit9Bit8Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit
0 0 0 Alarm window lower boundary temperature 0 0
Table 17. Critical temperature register format
Sign
MSB
Bit15Bit14Bit13Bit12Bit11Bit10Bit9Bit8Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit
0 0 0 Critical temperature trip point 0 0
4.5 Manufacturer ID register (read-only)
The manufacturer’s ID (programmed value 104Ah) in this register is the STMicroelectronics
identification provided by the Peripheral Component Interconnect Special Interest Group
(PCiSIG).
LSB
0
LSB
0
Table 18. Manufacturer ID register format
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
00010000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
01001010
24/36
STTS424 Temperature sensor registers
4.6 Device ID and device revision ID register (read-only)
The device IDs and device revision IDs are maintained in this register. The register format is
shown in Ta bl e 1 9 . The device IDs and device revision IDs are currently '0' and will be
incremented whenever an update of the device is made.
Table 19. Device ID and device revision ID register format
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
0000000 1
Device ID
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00000001
Device revision ID
25/36
Maximum ratings STTS424
5 Maximum ratings
Stressing the device above the ratings listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 20. Absolute maximum ratings
Symbol Parameter Value Unit
T
STG
T
SLD
V
IO
V
DD
V
OUT
I
O
P
D
θ
JA
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
Storage temperature –60 to 150 °C
(1)
Lead solder temperature for 10 seconds 260 °C
Input or output voltage - all pins VSS – 0.3 to VDD + 0.5 V
Supply voltage VSS – 0.3 to 6.5 V
Output voltage VDD + 0.5 V
Output current 10 mA
Power dissipation 320 mW
Thermal resistance 130 °C/W
26/36
STTS424 DC and AC parameters
6 DC and AC parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 21: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 21. Operating and AC measurement conditions
Parameter Conditions Unit
V
supply voltage - temperature sensor 2.7 to 3.6 V
DD
Operating temperature –40 to 125 °C
Input rise and fall times ≤ 5ns
Input pulse voltages 0.2 to 0.8V
Input and output timing reference voltages 0.3 to 0.7V
DD
DD
V
V
27/36
DC and AC parameters STTS424
Table 22. DC and AC characteristics - temperature sensor
Sym Description Test condition
V
DD
(1)
Supply voltage 2.7 3.3 3.6 V
VDD supply current, active
temperature conversions
I
VDD supply current,
DD
SCL/SDA = V
100 kHz 40 µA
DD
communication only
400 kHz 100 µA
(3)
at 125°C 1.0 3.0 µA
I
I
SINK
I
IH
V
DD1
, I
POR
(no conversions)
Shutdown mode supply current,
serial port inactive
DN package
SMBUS output low sink current SDA forced to 0.6 V 6 mA
Input/output leakage current ±2 µA
IL
Power on reset (POR) threshold VDD falling edge: 2.0 V
+75°C < TA < +95°C ±0.5 ±1.0 °C
B-grade
Accuracy for corresponding
range 2.7V ≤ V
DD
≤ 3.6V
+40°C < T
–40°C < T
< +125°C ±1.0 ±2.0 °C
A
< +125°C ±2.0 ±3.0 °C
A
Resolution 10-bit temperature data
t
CONV
T
HYS
Conversion time 10-bit 125 ms
Hysteresis Default value 500 mV
3.0 V ≤ VDD ≤ 3.6 V;
V
SMBus/I
Low level voltage EVENT
OL1
2
C interface
EVENT;
= 2.1 mA
I
OL
Min Typ
100 200 µA
(2)
Max Unit
0.25
°C/L
SB
10 bits
0.4 V
V
V
C
f
SCL
t
TIMEOUT
V
L
V
1. Guaranteed operating temperature for DN package: TA = –40°C to 125°C; VDD = 2.7 V to 3.6 V (except where noted).
2. Typical numbers taken at V
3. TDFN package max 0.80 mm height.
Input logic high
IH
Input logic low
IL
SMBus/I2C Input capacitance 5 pF
IN
SMBus/I2C clock frequency 10 400 kHz
SMBus timeout 25 50 ms
Allowable voltage on pin A0 10 V
HV
Leakage on pin A0 in
AO
overvoltage state
Low level voltage SDA IOL = 6 mA 0.6 V
OL2
= 3.3 V, TA = 25°C.
DD
3.0 V ≤ V
3.0 V ≤ V
≤ 3.6 V;
DD
SCL, SDA
≤ 3.6 V;
DD
SCL, SDA
2.1 V
0.8 V
500 µA
28/36
STTS424 Package mechanical data
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
29/36
Package mechanical data STTS424
Figure 10. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN)
DA_ME
(a)
Table 23. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN)
mm inches
Sym
Min Typ Max Min Typ Max
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.00 0.05 0.000 0.000 0.002
A3 0.20 0.005
b 0.20 0.25 0.30 0.008 0.010 0.012
D 1.95 2.00 2.05 0.075 0.078 0.079
D2 1.35 1.40 1.45 0.053 0.055 0.057
E 2.95 3.00 3.05 0.116 0.118 0.120
E2 1.25 1.30 1.35 0.049 0.051 0.053
e 0.50 0.020
L 0.30 0.35 0.40 0.012 0.014 0.016
ddd 0.08 0.003
1. JEDEC MO-229, variation WCED-3 proposal
(1)
a. JEDEC MO-229, variation WCED-3 proposal
30/36
STTS424 Part numbering
8 Part numbering
Table 24. Ordering information scheme
Example: STTS424 B DN 3 F
Device type
STTS424
Grade
B: Maximum accuracy 75°C to 95°C = ± 1°C
Package
DN = TDFN8 (2 mm x 3 mm) (0.80 mm max height)
Temperature range
3 = –40°C to 125°C
Shipping method
®
F = ECOPACK
E = ECOPACK
package, tape & reel packing
®
package, tube packing
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
31/36
Package marking information STTS424
9 Package marking information
Figure 11. Device topside marking information (TDFN-8L)
424B
(1)
1. TDFN package identifier
DN = 0.80 mm (package height)
2. Traceability codes
P = Plant code
Y = Year
WW = Work Week
DN
PYWW
(2)
ai13910b
32/36
STTS424 Landing pattern
10 Landing pattern
The landing pattern recommendations for the TDFN package (DN) are shown in Figure 12.
The preferred implementation with wide corner pads enhances device centering during
assembly, but a narrower option is defined for modules with tight routing requirements.
Figure 12. Landing pattern - TDFN package (DN)
e4
e2
e/2
e
L
K
e/2
E3
E3
D2
D2/2
K
L
b2
b4
K2
b
K2
D2/2
b
K2
E2/2
E2
E2/2
ai14000
33/36
Landing pattern STTS424
Ta bl e 2 5 lists variations of landing pattern implementations, ranked as “preferred”, and
minimum acceptable” based on the JEDEC proposal.
Table 25. Parameters for landing pattern - TDFN package (DN)
Dimension
Parameter Description
Min Nom Max
D2 Heat paddle width 1.40 - 1.60
E2 Heat paddle height 1.40 - 1.60
E3 Heat paddle centerline to contact inner locus 1.00 - -
L Contact length 0.70 - 0.80
K Heat paddle to contact keepout 0.20 - -
K2 Contact to contact keepout 0.20 - -
e Contact centerline to contact centerline pitch for inner contacts - 0.50 -
b Contact width for inner contacts 0.25 - 0.30
e2
b2 Corner contact width, “minimum acceptable option”
e4 Landing pattern centerline to outer contact centerline, “preferred” option
b4 Corner contact width, “preferred” option
1. Minimum acceptable option to be used when routing prevents preferred width contact.
2. Preferred option to be used when possible.
Landing pattern centerline to outer contact centerline, “minimum
acceptable” option
(1)
(1)
(2)
-0.50-
0.25 - 0.30
(2)
-0.60-
0.45 - 0.50
34/36
STTS424 Revision history
11 Revision history
Table 26. Document revision history
Date Revision Changes
17-Apr-2007 1 Initial release.
09-May-2007 2 Updated Ta b le 3 , 5, 6, 7, 22, 23, and 24.
04-June-2007 3 Updated Ta bl e 2 2 .
02-Jul-2007 4 Added POR threshold values to Ta bl e 2 2.
Added TDFN package (cover page, Figure 10, Tab l e 2 3 ) and landing
pattern recommendations (Figure 12, Ta b l e 2 5 ); updated Section 1,
22-Oct-2008 5
01-Apr-2009 6
Section 4.3.1; Ta b le 2 , 3, 5, 7, 11, 19, 20, 22, 25, and Figure 2, 4, 5,
11; added Figure 6; removed all TSSOP8 and DFN8 package
references throughout datasheet.
Updated Features on cover page, Section 3.1, Section 3.3,
Section 4.2.5, Section 6, Ta b le 3 , 5, 9, 12, 22.
35/36
STTS424
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