ST7232AK1-Auto ST7232AK2-Auto
Obsolete Product(s) - Obsolete Product(s)
ST7232AJ1-Auto ST7232AJ2-Auto
8-bit MCU for automotive, 16 Kbyte Flash/ROM,
Features
■ Memories
– 8K dual voltage high density Flash
(HDFlash) or ROM with read-out protection
capability. In-application programming and
in-circuit programming for HDFlash devices
– 384 bytes RAM
– HDFlash endurance: 100 cycles, data
retention: 20 years at 55°C
■ Clock, reset and supply management
– Clock sources: crystal/ceramic resonator
oscillators and bypass for external clock
– PLL for 2x frequency multiplication
– Four power saving modes: halt, active halt,
wait and slow
■ Interrupt management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and reset
– 6 external interrupt lines (on 4 vectors)
■ Up to 32 I/O ports
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
■ 4 timers
Table 1. Device summary
10-bit ADC, 4 timers, SPI, SCI
LQFP32 7 x 7
– Main clock controller with: real time base,
beep and clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2
output compares, PWM and pulse
generator modes
■ 2 communications interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
■ 1 analog peripheral (low current coupling)
– 10-bit ADC with up to 12 robust input ports
■ Instruction set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development tools
– Full hardware/software development
package
– In-circuit testing capability
LQFP44 10 x 10
Program memory - bytes RAM (stack) - bytes Operating volt. Temp. range Package
ST72F32AK1-Auto Flash 4K
ST72F32AK2-Auto Flash 8K
ST72F32AJ1-Auto Flash 4K
ST72F32AJ2-Auto Flash 8K
ST7232AK1-Auto ROM 4K
ST7232AK2-Auto ROM 8K
ST7232AJ1-Auto ROM 4K
ST7232AJ2-Auto ROM 8K
January 2008 Rev 1 1/201
384 (256) 3.8V to 5.5V
-40°C to
+125°C
LQFP32
LQFP44
LQFP32
LQFP44
www.st.com
1
Obsolete Product(s) - Obsolete Product(s)
Contents ST7232Axx-Auto
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 Differences between ST7232A-Auto and ST7232A datasheets . . . . . . . . 15
1.2.1 Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.2 Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.3 Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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6.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Contents
6.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.2 Asynchronous external RESET
6.5.3 External power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5.4 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.6 System integrity management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.2 Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.3 Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.4 Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.6 Interrupt related instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.7 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.7.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.8 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.9 Nested interrupts register map and reset value . . . . . . . . . . . . . . . . . . . . 53
7.10 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.4 Active halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.4.1 Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Contents ST7232Axx-Auto
9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.1.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.6 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.7 Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 72
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.9 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.1.10 Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . 73
10.2 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 73
10.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.3 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.7 MCC/RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.2.8 MCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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10.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.4.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.4.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.5 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.6 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.6 10-bit ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.1.1 Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.2 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.3 Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.4 Indexed instructions (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . 147
11.1.5 Indirect instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.6 Indirect indexed instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . 148
11.1.7 Relative mode instructions (direct, indirect) . . . . . . . . . . . . . . . . . . . . . 149
11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.3 Using a pre-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.2 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.5.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 162
12.5.4 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.7 Electromagnetic compatability (EMC) characteristics . . . . . . . . . . . . . . 165
12.7.1 Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 165
12.7.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 167
12.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.2 ICCSEL/V
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
12.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.10.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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12.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 175
12.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 179
12.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.3 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 185
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3 ROM device ordering information and transfer of customer code . . . . . 188
14.4 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 193
14.5 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.1 Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.3 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.1.4 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 196
15.1.5 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 197
15.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
15.1.8 39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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15.2 ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.1 I/O port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
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ST7232Axx-Auto List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4. Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. CC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. ST7 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8. SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 10. CPU CC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 11. ISPRx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 12. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 13. EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 14. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 15. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16. Active halt and halt power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 18. I/O Port Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 19. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 20. Port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 21. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 22. I/O interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 23. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 24. Effect of low power modes on watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 25. WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 26. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 27. Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 28. MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 29. MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 30. MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 31. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 32. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 33. 16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 34. Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 35. CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 36. CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 37. CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 38. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 39. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 40. SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 41. SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 42. SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 43. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 44. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 45. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 46. SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 47. SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 48. SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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Table 49. SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 50. SCIBRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 51. SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 52. SCIETPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 53. Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 54. SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 55. Effect of low power modes on 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 56. ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 57. ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 58. ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 59. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 60. CPU addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 61. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 62. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 63. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 64. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 148
Table 65. Short instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 66. Relative mode instructions (direct and indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 67. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 68. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 69. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 70. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 71. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 72. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 73. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 74. Supply current of clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 75. On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 76. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 77. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 78. Oscillator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 79. Examples of typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 81. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 82. Characteristics of dual VOLTAGE HDFlash MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 83. Electromagnetic test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 85. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 86. Latch up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 87. I/O general port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 88. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 89. Asynchronous RESET
Table 90. ICCSEL/V
Table 91. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 92. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 93. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 94. ADC accuracy with V
Table 95. 32-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 96. 44-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 97. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 98. Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 184
Table 99. Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. Option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
= 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DD
10/201
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ST7232Axx-Auto List of tables
Table 101. Option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 103. Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 104. FASTROM factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 105. ROM factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 106. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 107. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 108. Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 109. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
11/201
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List of figures ST7232Axx-Auto
List of figures
Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. 32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. 44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. Memory map and sector addresses of the ST7232X family . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 19. Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 20. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. Wait mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. Active halt Mode Flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25. Halt mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 26. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 28. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 29. Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 30. Exact timeout duration (t
Figure 31. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 32. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 33. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 34. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 35. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 36. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 37. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 38. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 39. Output compare block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 40. Output compare timing diagram, f
Figure 41. Output compare timing diagram, f
Figure 42. One pulse mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 43. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 44. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . . 91
Figure 45. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 46. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 47. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 48. Generic SS
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
min
and t
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
max
TIMER=fCPU
TIMER=fCPU
/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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ST7232Axx-Auto List of figures
Figure 49. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 50. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 51. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 111
Figure 52. Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 53. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 54. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 55. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 56. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 57. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 58. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 59. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 60. f
Figure 61. Typical I
Figure 62. Typical I
Figure 63. Typical I
Figure 64. Typ. I
max versus V
CPU
DD
DD
DD
in slow wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DD
in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 65. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 66. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 67. Integrated PLL jitter vs signal frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 68. Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 69. Typical I
Figure 70. Typical V
Figure 71. Typ. V
Figure 72. Typical V
Figure 73. Typical V
Figure 74. Typical V
Figure 75. Typical V
Figure 76. RESET
Figure 77. Two typical applications with ICCSEL/V
vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
PU
at VDD= 5V (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
OL
at VDD= 5V (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OL
at VDD= 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OH
vs. VDD (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OL
vs. VDD (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
OL
vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
OH
pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
Figure 78. SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 79. SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 80. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 81. R
Figure 82. Recommended C
max. vs f
AIN
ADC
with C
and R
AIN
= 0pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
AIN
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
AIN
Figure 83. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 84. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 85. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 86. 32-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 87. 44-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 88. Flash commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 89. FASTROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 90. ROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Introduction ST7232Axx-Auto
1 Introduction
1.1 Description
The ST7232AK1-Auto, ST7232AK2-Auto, ST7232AJ1-Auto, and ST7232AJ2-Auto devices
are members of the ST7 microcontroller family designed for the 5V operating range.
The 32 and 44-pin devices are designed for mid-range applications
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory.
Under software control, all devices can be placed in wait, slow, active halt or halt mode,
reducing power consumption when the application is in idle or stand-by state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8 x 8 unsigned multiplication and indirect addressing modes.
Figure 1. Device block diagram
8-bit core
ALU
RESET
V
PP
V
SS
V
DD
OSC1
OSC2
V
V
AREF
SSA
Control
OSC
ADDRESS AND DATA BUS
MCC/RTC/beep
PORT F
Timer A
Beep
Por t E
SCI
Por t D
10-bit ADC
Program
memory
(8K bytes)
RAM
(384 bytes)
Watchdog
Por t A
Por t B
Por t C
Timer B
SPI
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Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Introduction
1.2 Differences between ST7232A-Auto and ST7232A datasheets
The differences between the ST7232A-Auto datasheet, version 1, released in January 2008
and the ST7232A datasheet, version 2, released in December 2005 are listed below.
Differences are categorised as follows:
● Principal differences
● Minor content differences
● Editing and formatting differences
1.2.1 Principal differences
1. Changed root part number from ST7232A to ST7232AK1-Auto, ST7232AK2-Auto,
ST7232AJ1-Auto, and ST7232AJ2-Auto throughout document
2. Changed document title on page 1
3. Removed 1 and 5 suffix version temperatures ranges throughout the document
4. Features on page 1: Changed minimum value of data retention time (t
and changed the condition to T
5. Table 2: Device pin description on page 21: Added footnote
= 55°C
A
(5)
6. Section 6.3: Phase locked loop (PLL) on page 36: Added caution regarding use of PLL
with an external clock
7. Reset vector fetch on page 38: Added a ‘caution’ about the reset vector when it is not
programmed
8. Section 9.2.1: Input modes on page 62: Amended note3 of this section
9. Section 9.3: I/O port implementation on page 66: Deleted I/O port implementation
tables
10. Output compare on page 85: Amended text in note 3
11. Figure 41: Output compare timing diagram, fTIMER = fCPU/4 on page 88: Removed
compare register i Latch from diagram
12. Section 10.6: 10-bit A/D converter (ADC) on page 139: Amended text concerning the
EOC bit in Starting the conversion
13. Table 70: Current characteristics on page 155:
– Added data for the LQFP44 package to I
– Updated max I
values for standard I/O and high sink I/O
IO
VDD
and I
VSS
14. Table 72: General operating conditions on page 156: Updated temperature ranges in
the ‘conditions’ column
15. Table 82: Characteristics of dual VOLTAGE HDFlash MEMORY on page 164:
– Changed typical value of supply current (I
– Changed minimum value of data retention time (t
condition to T
= 55°C
A
– Changed the condition of write erase cycle (N
) to < 10µA
DD
RET
RW
) to 20 years and changed the
) to TA = 85°C
16. Section 12.7.3: Absolute maximum ratings (electrical sensitivity) on page 167:
Removed text concerning dynamic latch-up
17. Electro-static discharge (ESD) on page 167: Replaced JESD22-A114A/A115A
standard with AEC-Q100-002/003/011 standard
) to 20 years
RET
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Obsolete Product(s) - Obsolete Product(s)
Introduction ST7232Axx-Auto
18. Table 85: ESD absolute maximum ratings on page 167:
– Added test standards to conditions column
– Changed max value of CDM from 250 V to: > 500 V to ≤ 750 V with corner pins >
750 V
– Added ‘class’ information
19. Static latch-up on page 167: Added ‘AEC-Q100/004’ standard
20. Table 86: Latch up results on page 167:
– Removed T
= +25°C, +85°C and +105°C from latch-up conditions
A
– Added AEC-Q100/004 test standard
– Removed dynamic latch-up results
– Changed ‘class’ information
– Removed footnote 1 pertaining to class descriptions and JEDEC standards
21. Table 87: I/O general port pin characteristics on page 168:
– Added footnote
(3)
– Amended footnote
and
(4)
(5)
22. Figure 76: RESET pin protection on page 173: Removed EMC protective circuitry
(device works correctly without these components)
23. Table 92: SPI characteristics on page 175:
– Added footnote
(1)
and
(2)
– Updated max and unit information of tv(MO)
– Updated min values of t
(MO)
h
– Updated min and max values for ‘data output valid’ and ‘data output hold’ times
24. Figure 80: SPI master timing diagram on page 177: Modified figure to reflect changes
made in Table 92: SPI characteristics concerning t
(MO) and th(MO)
v
25. Table 93: 10-bit ADC characteristics on page 178:
– Removed word ‘positive’ from explanation of I
– Updated footnote
(2)
26. Figure 83: Typical A/D converter application on page 179: Changed IL ± 1µA to I
parameter
lkg
lkg
27. Table 94: ADC accuracy with VDD = 5.0V on page 181:
– Made the ‘conditions’ applicable for all parameters
– Updated footnote
(2)
28. Table 97: Thermal characteristics on page 184:
– Amended footnotes
(1)
and
(2)
– Added a value for LQFP44
29. Table 99: Flash option bytes on page 185:
– Changed bits 4 and 3 of option byte 0 to a default value of ‘1’
– Changed the OSCRANGE bits [2:0] of option byte 1 from 111 to 011
– Added footnote 1 concerning package selection
30. Updated Table 100: Option byte 0 description on page 186
31. Updated Table 101: Option byte 1 description on page 186
32. Added Table 102: Package selection (OPT7) on page 187
33. Section 15.1.2: External interrupt missed on page 194: Added section on ‘external
interrupt missed’ bug
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ST7232Axx-Auto Introduction
34. Section 15.1.6: TIMD set simultaneously with OC interrupt on page 197:
– Added section concerning limitation of the 16-bit timer
– Added ‘TBCR1’, ‘TBCSR I’ and ‘TBCSR &’ to the workaround subsection
1.2.2 Minor content differences
1. Removed all references to the SDIP32 and SDIP42 packages (which are unavailable in
automotive) thoughout document
2. Replaced TQFP by LQFP throughout document
3. Table 3: Hardware register map on page 25: Replaced ‘h’ with ‘b’ in the reset status
column for the SCICR1 register
4. System integrity control/status register (SICSR) on page 41: Replaced ‘h’ with ‘b’ in the
reset value cell of the SICSR register
5. Table 43: SPI register map and reset values on page 117: Changed the name of bit 5 in
the SPICSR register from OR to OVR
6. Break character on page 123: SPI replaced by SCI
7. Control register 1 (SCICR1) on page 133: Replaced ‘h’ with ‘b’ in the reset value cell of
the SCICR1 register
8. Changed I
application with an external clock source on page 161 and Table 90: ICCSEL/VPP pin
characteristics on page 174
9. Table 95: 32-pin LQFP mechanical data on page 182 and Table 96: 44-pin LQFP
mechanical data on page 183: Altered ‘inches’ data to four decimal places
10. Section 13.3: Soldering information on page 184:
– Updated environmental information regarding ‘ECOPACK®’ packages
– Replaced ECOPACK
– Updated section on ECOPACK® soldering compatability
11. Table 98: Soldering compatibility (wave and reflow soldering process) on page 184:
Removed footnote on Pb package maximum temperature
12. Updated Table 103: Flash user programmable device types on page 187
13. Added Figure 88: Flash commercial product code structure on page 188
14. Updated Section 14.3: ROM device ordering information and transfer of customer code
on page 188
15. Added Table 104: FASTROM factory coded device types on page 189
16. Added Figure 89: FASTROM commercial product code structure on page 189
17. Added Table 105: ROM factory coded device types on page 190
18. Updated Figure 90: ROM commercial product code structure on page 190
19. Updated ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list on page 191
20. Updated Table 106: STMicroelectronics development tools on page 193
21. Section 14.4: Development tools on page 192:
– Updated Introduction and Programming tools
– Deleted Emulators and In-circuit debugging kit
– Added Evaluation tools and starter kits and Development and debugging tools
22. Section 14.5: ST7 application notes on page 193: Removed list of ST7 application
notes
L
to I
in Table 77: External clock source on page 161, Figure 65: Typical
lkg
TM
with ECOPACK® throughout the document
17/201
Obsolete Product(s) - Obsolete Product(s)
Introduction ST7232Axx-Auto
1.2.3 Editing and formatting differences
1. Reformatted document
2. Converted register and bit decriptions to table format
3. Edited English throughout document
4. Correctly aligned footnotes of tables throughout document
18/201
Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Pin description
2 Pin description
Figure 2. 32-pin LQFP 7x7 package pinout
_2
PE1/RDI
ICCCLK/SCK/PC6
PE0/TDO
ei0
/PC7
AIN15/SS
V
24
23
22
21
20
19
18
17
(HS) PA3
DD
OSC1
OSC2
V
_2
SS
RESET
V
/ICCSEL
PP
PA7 ( H S)
PA6 ( H S)
PA4 ( H S)
V
AREF
V
MCO/AIN8/PF0
Beep/(HS) PF1
OCMP1_A/AIN10/PF4
ICAP1_A/(HS) PF6
EXTCLK_A/(HS) PF7
AIN12/OCMP2_B/PC0
SSA
PD0/AIN0
ei3
PB4 (HS)
PB3
ei2
PB0
PD1/AIN1
32 31 30 29 2827 2625
1
2
3
ei1
4
5
6
7
8
9 10111213141516
AIN14/MOSI/PC5
ICAP2_B/(HS) PC2
ICAP1_B/(HS) PC3
ICCDATA/MISO/PC4
AIN13/OCMP1_B/PC1
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
19/201
Obsolete Product(s) - Obsolete Product(s)
Pin description ST7232Axx-Auto
Figure 3. 44-pin LQFP package pinout
_2
_2
/ICCSEL
SS
RDI/PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
DD
PE0/TDO
V
OSC1
OSC2
44 43 42 41 40 39 38 37 36 35 34
1
2
3
ei2
4
5
ei3
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
ei1
PP
V
PA 6 ( HS )
PA 5 ( HS )
ei0
PA 4 ( HS )
V
33
SS_1
V
32
DD_1
PA3 ( H S )
31
PC7/SS
30
PC6/SCK/ICCCLK
29
PC5/MOSI/AIN14
28
PC4/MISO/ICCDATA
27
PC3 (HS)/ICAP1_B
26
PC2 (HS)/ICAP2_B
25
PC1/OCMP1_B/AIN13
24
PC0/OCMP2_B/AIN12
23
/AIN15
PA 7 ( HS )
V
RESET
SSA
AREF
V
V
AIN5/PD5
MCO/AIN8/PF0
(HS) PF2
Beep/(HS) PF1
ICAP1_A/(HS) PF6
OCMP1_A/AIN10/PF4
DD_0
V
EXTCLK_A/(HS) PF7
SS_0
V
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
For external pin connection guidelines, refer to Section 12: Electrical characteristics on
page 153.
In Table 2: Device pin description below, refer to Section 9: I/O ports on page 62 for more
details on the software configuration of the I/O ports. The RESET
configuration of each pin
is shown in bold. This configuration is valid as long as the device is in reset state. For
external pin connection guidelines refer to Section 12: Electrical characteristics on
page 153.
20/201
Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Pin description
Table 2. Device pin description
Pin
no.
LQFP44
Pin name
LQFP32
Typ e
(1)
Level Port
Input Output
Input
Output
float
(2)
wpu
int
ana
(3)
OD
Main
function
(after
reset)
PP
630PB4 (HS) I/OCTHS X ei3 X X Port B4
7 31 PD0/AIN0 I/O C
8 32 PD1/AIN1 I/O C
(4)
9 -
10 -
11 -
12 -
13 1 V
14 2 V
PD2/AIN2 I/O C
(4)
PD3/AIN3 I/O C
(4)
PD4/AIN4 I/O C
(4)
PD5/AIN5 I/O C
(5)
AREF
(5)
SSA
S Analog reference voltage for ADC
S Analog ground voltage
15 3 PF0/MCO/AIN8 I/O C
16 4 PF1 (HS)/Beep I/O C
(4)
17 -
18 5
PF2 (HS) I/O CTHS X ei1 X X Port F2
PF4/OCMP1_A/
AIN10
I/O C
T
T
T
T
T
T
T
T
T
X X X X X Port D0 ADC analog input 0
X X X X X Port D1 ADC analog input 1
X X X X X Port D2 ADC analog Input 2
X X X X X Port D3 ADC analog Input 3
X X X X X Port D4 ADC analog Input 4
X X X X X Port D5 ADC analog Input 5
Xei1XXXPort F0
HS X ei1 X X Port F1 Beep signal output
XX XX XPort F4
Alternate function
Main clock
out (f
CPU
)
Timer A output
compare 1
ADC analog
input 8
ADC analog
input 10
19 6 PF6 (HS)/ICAP1_A I/O CTHS X X X X Port F6 Timer A input capture 1
20 7
21 - V
22 - V
23 8
24 9
25 10
26 11
27 12
28 13 PC5/MOSI/AIN14 I/O C
29 14 PC6/SCK/ICCCLK I/O C
PF7
(HS)/EXTCLK_A
(5)
DD_0
(5)
SS_0
PC0/OCMP2_B/
AIN12
PC1/OCMP1_B/
AIN13
PC2
(HS)/ICAP2_B
PC3
(HS)/ICAP1_B
PC4/MISO/
ICCDATA
I/O CTHS X X X X Port F7 Timer A external clock source
S Digital main supply voltage
S Digital ground voltage
I/O C
I/O C
I/O C
I/O C
I/O C
T
T
T
T
T
T
T
XX XX XPort C0
XX XX XPort C1
HS X X X X Port C2 Timer B input capture 2
HS X X X X Port C3 Timer B input capture 1
XX XXPort C4
XX XX XPort C5
XX XXPort C6
Timer B output
compare 2
Timer B output
compare 1
SPI master in/
slave out data
SPI master out
/slave in data
SPI serial
clock
ADC analog
input 12
ADC analog
input 13
ICC data
input
ADC analog
input 14
ICC clock
output
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Obsolete Product(s) - Obsolete Product(s)
Pin description ST7232Axx-Auto
Table 2. Device pin description
Pin
no.
Pin name
LQFP44
LQFP32
30 15 PC7/SS/AIN15 I/O C
31 16 PA3 (HS) I/O C
32 - V
33 - V
DD_1
SS_1
(5)
(5)
34 17 PA4 (HS) I/O C
(4)
35 -
PA5 ( H S ) I/ O CTHS X X X X Port A5
36 18 PA6 (HS) I/O C
37 19 PA7 (HS) I/O C
38 20 V
/ICCSEL I
PP
Level Port
Type
Input
T
T
S Digital main supply voltage
S Digital ground voltage
T
T
T
(1)
(continued)
Main
Input Output
ana
(3)
OD
Output
float
(2)
wpu
int
function
(after
reset)
PP
XX XX XPort C7
HS X ei0 X X Port A3
HS X X X X Port A4
HS X T Port A6
HS X T Port A7
Must be tied low. In the Flash
programming mode, this pin acts as the
programming voltage input V
Section 12.9.2 for more details. High
voltage must not be applied to ROM
devices.
Alternate function
SPI slave
select (active
low)
ADC analog
input 15
. See
PP
39 21 RESET I/O C
40 22 V
SS_2
41 23 OSC2
42 24 OSC1
43 25 V
DD_2
(5)
(6)
(6)
(5)
S Digital ground voltage
O Resonator oscillator inverter output
I
S Digital main supply voltage
44 26 PE0/TDO I/O C
127PE1/RDI I/OC
T
T
T
X X X X Port E0 SCI transmit data out
X X X X Port E1 SCI receive data in
Top priority non maskable interrupt.
External clock input or resonator
oscillator inverter input
Caution: Negative current
228PB0 I/OC
(4)
3-
4-
PB1 I/O C
(4)
PB2 I/O C
529PB3 I/OC
1. Legend/abbreviations for Table 2:
Type: I = input, O = output, S = supply
Input level: C
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration inputs: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ports
Port and control configuration outputs: OD = open drain, PP = push-pull
2. ‘eiX’ defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column
(int), then the I/O configuration is pull-up interrupt input; otherwise the configuration is floating interrupt input
= CMOS 0.3VDD/0.7VDD with input trigger
T
T
T
T
T
Xei2 XXPort B0
injection not allowed on this
pin
Xei2 XXPort B1
Xei2 XXPort B2
Xei2XXPort B3
(7)
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ST7232Axx-Auto Pin description
3. ‘T’ defines a true open drain I/O (P-buffer and protection diode to VDD are not implemented). See Section 9: I/O ports on
page 62 and Section 12.8: I/O port pin characteristics for more details
4. Each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The
configuration of these pads must be kept at reset state to avoid added current consumption.
5. It is mandatory to connect all available V
6. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1:
Introduction and Section 12.5: Clock and timing characteristics for more details
7. For details refer to Section 12.8.1: General characteristics on page 168
DD
and V
pins to the supply voltage and all VSS and V
AREF
pins to ground
SSA
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Obsolete Product(s) - Obsolete Product(s)
Register and memory map ST7232Axx-Auto
3 Register and memory map
As shown in <Blue HT>Figure 4, the MCU is capable of addressing 64K bytes of memories
and I/O registers.
The available memory locations consist of 128 bytes of register locations, up to 384 bytes of
RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 256 bytes
for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Caution: Memory locations marked as ‘reserved’ must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 4. Memory map
0000h
007Fh
0080h
047Fh
0480h
E000h
FFDFh
FFE0h
FFFFh
HW registers
Program memory
Interrupt and reset vectors
(see Ta bl e 3)
RAM
(384 bytes)
Reserved
(4K or 8K)
(see Ta bl e 15 )
0080h
00FFh
0100h
01FFh
0200h
027Fh
or 047Fh
Short addressing
RAM (zero page)
256 bytes stack
Reserved
E000h
8 Kbytes
F000h
4 Kbytes
FFFFh
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Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Register and memory map
Table 3. Hardware register map
Address Block Register label Register name Reset status
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h to
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
Por t A
Por t B
Por t C
Por t D
Por t E
Por t F
SPI
ITC
(3)
(3)
(3)
(3)
(3)
PA DR
PADDR
PA OR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDADR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
Port A data register
Port A data direction register
Port A option register
Port B data register
Port B data direction register
Port B option register
Port C data register
Port C data direction register
Port C option register
Port D data register
Port D data direction register
Port D option register
Port E data register
Port E data direction register
Port E option register
Port F data register
Port F data direction register
Port F option register
Reserved area (15 bytes)
SPI data I/O register
SPI control register
SPI control/status register
Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xxh
0xh
00h
FFh
FFh
FFh
FFh
(1)
(4)
(4)
(4)
(4)
(4)
(4)
0028h EICR External interrupt control register 00h R/W
0029h Flash FCSR Flash control/status register 00h R/W
002Ah Watchdog WDGCR Watchdog control register 7Fh R/W
002Bh Reserved area (1 byte)
002Ch
002Dh
002Eh to
0030h
MCC
MCCSR
MCCBCR
Main clock control/status register
Main clock controller: beep control register
Reserved area (3 bytes)
00h
00h
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(3)
R/W
(3)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(2)
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Obsolete Product(s) - Obsolete Product(s)
Register and memory map ST7232Axx-Auto
Table 3. Hardware register map (continued)
00h
00h
xxh
xxh
80h
00h
FFh
xxh
xxh
80h
00h
00h
00h
xxh
xxh
80h
00h
xxh
xxh
80h
00h
xxh
00h
00h
00h
00h
00h
00h
00h
(1)
Remarks
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
Address Block Register label Register name Reset status
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h Reserved area (1 byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h to
006Fh
0070h
0071h
0072h
0073h
007Fh
1. x = undefined
2. R/W = read/write
3. The bits associated with unavailable pins must always keep their reset value
4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents
Timer A
Timer B
SCI
ADC
TAC R2
TAC R1
TAC SR
TA IC 1 H R
TAIC1LR
TAO C1 HR
TAO C1 LR
TAC HR
TAC LR
TAACHR
TA AC L R
TA IC 2 H R
TAIC2LR
TAO C2 HR
TAO C2 LR
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
ADCCSR
ADCDRH
ADCDRL
Timer A control register 2
Timer A control register 1
Timer A control/status register
Timer A input capture 1 high register
Timer A input capture 1 low register
Timer A output compare 1 high register
Timer A output compare 1 low register
Timer A counter high register
Timer A counter low register
Timer A alternate counter high register
Timer A alternate counter low register
Timer A input capture 2 high register
Timer A input capture 2 low register
Timer A output compare 2 high register
Timer A output compare 2 low register
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register
Reserved area (24 bytes)
Control/status register
Data high register
Data low register
Reserved area (13 bytes)
xxxx x0xxb
FCh
FFh
FCh
xxxx x0xxb
FFh
FCh
FFh
FCh
C0h
x000 0000b
(2)
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Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Flash program memory
4 Flash program memory
4.1 Introduction
The ST7 dual voltage high density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external V
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organisation allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2 Main features
● Three Flash programming modes:
– Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased
– ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board
– IAP (in-application programming) In this mode, all sectors except sector 0, can be
programmed or erased without removing the device from the application board
and while the application is running
● ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
● Read-out protection
● Register access security system (RASS) to prevent accidental programming or erasing
supply.
PP
4.3 Structure
The Flash memory is organised in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Ta b l e 4 ). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
sector 0 (F000h-FFFFh).
Table 4. Sectors available in Flash devices
Flash size (bytes) Available sectors
4K Sector 0
8K Sectors 0,1
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Obsolete Product(s) - Obsolete Product(s)
Flash program memory ST7232Axx-Auto
4.3.1 Read-out protection
Read-out protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Read-out protection selection depends on the device type:
● In Flash devices it is enabled and removed through the FMP_R bit in the option byte
● In ROM devices it is enabled by mask option specified in the option list
Figure 5. Memory map and sector addresses of the ST7232X family
4K 10K 24K 48K
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
8K 16K 32K 60K
2Kbytes
4.4 ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
● RESET: device reset
● V
● ICCCLK: ICC output serial clock pin
● ICCDATA: ICC input/output serial data pin
● ICCSEL/V
● OSC1(or OSCIN): main clock input for external source (optional)
● V
: device power supply ground
SS
: programming voltage
PP
: application board power supply (optional, see Figure 6, footnote 3)
DD
8Kbytes 40 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
24 Kbytes
Flash memory size
Sector 2
52 Kbytes
Sector 1
Sector 0
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Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Flash program memory
Figure 6. Typical ICC interface
Programming tool
ICC connector
ICC cable
(3)
Application
power supply
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to implemented in case another device forces the
signal. Refer to the programming tool documentation for recommended resistor values.
2. During the ICC session, the programming tool must control the RESET
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(push pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application reset
circuit in this case. When using a classical RC network with R > 1K or a reset management IC with open
drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.
C
L2
DD
V
OSC2
(See ‘caution’)
C
L1
OSC1
ST7
975 3
10kΩ
SS
V
ICC connector
1
HE10 connector type
246810
Application reset source
RESET
ICCCLK
ICCSEL/VPP
ICCDATA
pin. This can lead to conflicts
Application board
Application I/O
(2)
(1)
Caution: External clock ICC entry mode is mandatory. Pin 9 must be connected to the OSC1 or
OSCIN pin of the ST7 and OSC2 must be grounded.
4.5 In-circuit programming (ICP)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.
29/201
Obsolete Product(s) - Obsolete Product(s)
Flash program memory ST7232Axx-Auto
4.6 In-application programming (IAP)
This mode uses a Bootloader program previously stored in sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored, ...). For example, it is possible
to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash sectors except sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.7 Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash programming
reference manual and to the ST7 ICC protocol reference manual
Flash control/status register (FCSR)
FCSR Reset value: 0000 0000 (00h)
76543210
.
0
R/W
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Table 5. Flash control/status register address and reset value
Address (Hex.)Register label76543210
0029h
FCSR
Reset value00000000
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5 Central processing unit
5.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient
8-bit data manipulation.
5.2 Main features
● Enable executing 63 basic instructions
● Fast 8-bit by 8-bit multiply
● 17 main addressing modes (with indirect addressing mode)
● Two 8-bit index registers
● 16-bit stack pointer
● Low power halt and wait modes
● Priority maskable hardware interrupts
● Non-maskable software/hardware interrupts
5.3 CPU registers
The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
Figure 7. CPU registers
15
Reset value = reset vector @ FFFEh-FFFFh
15 8 70
Reset value = stack higher address
8PCH PCL
Reset value =
70
Accumulator
Reset value = XXh
70
X index register
Reset value = XXh
70
Y index register
Reset value = XXh
07
70
1C1I1HI0NZ
1X11X1XX
Program counter
Condition code register
Stack pointer
1. X = undefined value
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Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The cross-assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
Condition code register (CC)
CC Reset value: 111x 1xxx
76543210
1I1HI0NZC
R/W R/W R/W R/W R/W R/W R/W
The 8-bit condition code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
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Table 6. CC register description
Bit Bit name Function
Interrupt management bits - interrupt
The combination of the I1 and I0 bits gives the current interrupt
software priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
5,3
4H
2N
1Z
I1, I0
00: Interrupt software priority = level 2
11: Interrupt software priority = level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in
interrupt. The loaded value is given by the corresponding bits in the
interrupt software priority registers (IxSPR). They can be also
set/cleared by software with the RIM, SIM, IRET, HALT, WFI and
PUSH/POP instructions. See Section 7: Interrupts for more details.
Arithmetic management bit -
This bit is set by hardware when a carry occurs between bits 3 and 4
of the ALU during an ADD or ADC instructions. It is reset by
hardware during the same instructions.
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is
useful in BCD arithmetic subroutines.
Arithmetic management bit - Negative
This bit is set and cleared by hardware. It is representative of the
result sign of the last arithmetic, logical or data manipulation. It’s a
copy of the result 7
0: The result of the last operation is positive or null
1: The result of the last operation is negative (i.e. the most significant
bit is a logic 1)
This bit is accessed by the JRMI and JRPL instructions.
Arithmetic management bit - Zero
This bit is set and cleared by hardware. This bit indicates that the
result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero
1: The result of the last operation is zero
This bit is accessed by the JREQ and JRNE test instructions.
th
Half carry
bit.
Arithmetic management bit -
This bit is set and cleared by hardware and software. It indicates an
overflow or an underflow has occurred during the last arithmetic
operation.
0C
0: No overflow or underflow has occurred
1: An overflow or underflow has occurred
This bit is driven by the SCF and RCF instructions and tested by the
JRC and JRNC instructions. It is also affected by the ‘bit test and
branch’, shift and rotate instructions.
Carry/borrow
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Central processing unit ST7232Axx-Auto
Stack pointer register (SP)
SP Reset value: 01 FFh
15 14 13 12 11 10 9 8
01
R/W R/W
76543210
SP[7:0]
R/W
The stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU reset, or after a reset stack pointer instruction (RSP), the stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the stack pointer (called S) can be directly accessed by a LD
instruction.
Note: When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 8.
● When an interrupt is received, the SP is decremented and the context is pushed on the
stack
● On return from interrupt, the SP is incremented and the context is popped from the
stack
A subroutine call occupies two locations and an interrupt five locations in the stack area.
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Figure 8. Stack manipulation example
@ 0100h
SP
@ 01FFh
Call
subroutine
PCH
PCL
Interrupt
event
SP
CC
A
X
PCH
PCL
PCH
PCL
PUSH Y POP Y IRET RET or RSP
SP
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
1. Legend: stack higher addres = 01FFh; stack lower address = 0100h
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
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6 Supply, reset and clock management
6.1 Introduction
The device includes a range of utility features for securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An overview is
shown in Figure 10.
6.2 Main features
● Optional PLL for multiplying the frequency by 2
● Reset sequence manager (RSM)
● Multi-oscillator clock management (MO)
– 5 crystal/ceramic resonator oscillators
6.3 Phase locked loop (PLL)
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the
frequency by two to obtain an f
disabled, then f
OSC2 =fOSC
/2.
Caution: The PLL is not recommended for applications where timing accuracy is required.
of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is
OSC2
Caution: When the PLL is used with an external clock signal, the clock signal must be available on
the OSCIN pin before the reset signal is released.
Figure 9. PLL block diagram
f
OSC
PLL x 2
/2
0
1
PLL option bit
f
OSC2
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Figure 10. Clock, reset and supply block diagram
OSC2
OSC1
RESET
V
V
DD
Multi-oscillator
(MO)
Reset sequence manager
(RSM)
SS
f
OSC
PLL
(option)
6.4 Multi-oscillator (MO)
The main clock of the ST7 can be generated by two different source types coming from the
multi-oscillator block:
● An external source
● 4 crystal or ceramic resonator oscillators
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Ta bl e 7 . Refer to Section 12: Electrical characteristics for more details.
System integrity management
SICSR
0
f
OSC2
Main clock controller
with real-time clock
(MCC/RTC)
Watchdog timer
(WDG)
f
0
WDG
00
RF
CPU
Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of failure
mode and effect analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
f
clock frequency in excess of the allowed maximum (> 16MHz), putting the ST7 in an
OSC
unsafe/undefined state. The product behaviour must therefore be considered undefined
when the OSC pins are left unconnected.
6.4.1 External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
6.4.2 Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 14.2: Flash
devices on page 185 for more details on the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
start-up phase.
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Table 7. ST7 clock source
Hardware configuration
ST7
OSC1 OSC2
External clockCrystal/ceramic resonators
External source
OSC1 OSC2
C
L1
capacitors
6.5 Reset sequence manager (RSM)
6.5.1 Introduction
The reset sequence manager includes two reset sources as shown in Figure 12:
● External RESET source pulse
● Internal watchdog reset
These sources act on the RESET
pin and it is always kept low during the delay phase.
ST7
Load
C
L2
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in Figure 11:
● Active phase depending on the reset source
● 256 or 4096 CPU clock cycle delay (selected by option byte)
● Reset vector fetch
Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET
pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
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The reset vector fetch phase duration is 2 clock cycles.
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ST7232Axx-Auto Supply, reset and clock management
Figure 11. Reset sequence phases
Reset
Active phase
256 or 4096 CLOCK CYCLES
6.5.2 Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 12: Electrical
characteristics for more details.
A reset signal originating from an external source must have a duration of at least t
in order to be recognized (see Figure 13). This detection is asynchronous and therefore the
MCU can enter reset state even in halt mode.
Figure 12. Reset block diagram
V
DD
R
ON
RESET
Filter
Internal reset
Fetch vector
h(RSTL)in
Internal reset
The RESET
Pulse
generator
pin is an asynchronous signal which plays a major role in EMS performance. In
Watchdog reset
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
6.5.3 External power on reset
To start up the microcontroller correctly, the user must ensure by means of an external reset
circuit that the reset signal is held low until V
selected f
A proper reset signal for a slow rising V
RC network connected to the RESET
frequency.
OSC
DD
pin.
is over the minimum level specified for the
DD
supply can generally be provided by an external
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6.5.4 Internal watchdog reset
The reset sequence generated by a internal watchdog counter overflow is shown in
Figure 13.
Starting from the watchdog counter underflow, the device RESET
is pulled low during at least t
w(RSTL)out
.
Figure 13. Reset sequences
Watchdog
Active
phase
External
RESET
source
RESET pin
Watchdog
reset
Run
t
h(RSTL)in
External reset
Active
phase
Watchdog underflow
Run Run
pin acts as an output that
reset
t
w(RSTL)out
Internal reset (256 or 4096 T
Vector fetch
CPU
)
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6.6 System integrity management
System integrity control/status register (SICSR)
SICSR Reset value: 0000 000x (00b)
76543210
Reserved WDGRF
-R/W
Table 8. SICSR register description
Bit Bit name Function
7:1
0 WDGRF
-
Reserved, must be kept cleared
Watchdog reset flag
This bit indicates that the last reset was generated by the watchdog
peripheral. It is set by hardware (watchdog reset) and cleared by
software (writing zero).
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Interrupts ST7232Axx-Auto
7 Interrupts
7.1 Introduction
The ST7 enhanced interrupt management provides the following features:
● Hardware interrupts
● Software interrupt (TRAP)
● Nested or concurrent interrupt management with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: reset, TRAP
This interrupt management is based on:
● Bit 5 and bit 3 of the CPU CC register (I1:0)
● Interrupt software priority registers (ISPRx)
● Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2 Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
Ta bl e 9 ). The processing flow is shown in Figure 14.
When an interrupt request has to be serviced:
● Normal processing is suspended at the end of the current instruction execution
● The PC, X, A and CC registers are saved onto the stack
● I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector
● The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 15: Interrupt
mapping for vector addresses)
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction, the I1 and I0 bits are restored from the stack and
the program in the previous level is resumed.
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Table 9. Interrupt software priority levels
Interrupt software priority Level I1 I0
Level 0 (main)
Level 1 0 1
Level 2 0 0
Low
High
10
Level 3 (= interrupt disable) 1 1
Figure 14. Interrupt processing flowchart
Reset
Restore PC, X, A, CC
from stack
Pending
interrupt
Fetch next
instruction
Y
Execute
instruction
N
‘IRET’
N
Y
Interrupt has the same or a
lower software priority
than current one
The interrupt
stays pending
Interrupt has a higher
software priority
than current one
Stack PC, X, A, CC
Load I1:0 from interrupt SW register
Load PC from interrupt vector
TRAP
N
I1:0
Y
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Interrupts ST7232Axx-Auto
7.2.1 Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
● the highest software priority interrupt is serviced
● if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first
Figure 15 describes this decision process.
Figure 15. Priority decision process
Pending
interrupts
Same
Highest hardware
priority serviced
Software
priority
priority serviced
Different
Highest software
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
2 Reset and TRAP can be considered as having the highest software priority in the decision
process.
7.2.2 Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).
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7.2.3 Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 14). After stacking the PC, X, A and CC registers (except for reset), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit halt mode.
● TRAP (non maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It is serviced
according to the flowchart in Figure 14.
● Reset
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority. See Section 6.5:
Reset sequence manager (RSM).
7.2.4 Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
● External interrupts
External interrupts allow the processor to exit from halt low power mode. External
interrupt sensitivity is software selectable through the external interrupt control register
(EICR).
External interrupt triggered on edge is latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these are logically ORed.
● Peripheral interrupts
Usually the peripheral interrupts cause the MCU to exit from halt mode except those
mentioned in Table 15: Interrupt mapping . A peripheral interrupt occurs when a
specific flag is set in the peripheral status registers and if the corresponding enable bit
is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status register
followed by a read or write to an associated register.
Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be
serviced) is therefore lost if the clear sequence is executed.
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7.3 Interrupts and low power modes
All interrupts allow the processor to exit the wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the halt modes (see
column ‘exit from halt’ in Table 15: Interrupt mapping). When several pending interrupts are
present while exiting halt mode, the first one serviced can only be an interrupt with exit from
halt mode capability and it is selected through the same decision process shown in
Figure 15.
Note: If an interrupt, that is not able to exit from halt mode, is pending with the highest priority
when exiting halt mode, this interrupt is serviced after the first one serviced.
7.4 Concurrent and nested management
Figure 16 and Figure 17 show two different interrupt management modes. The first is called
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in Figure 17. The interrupt hardware priority is given in this order from the lowest to the
highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.
Warning: A stack overflow may occur without notifying the software of
the failure.
Figure 16. Concurrent interrupt management
3
3
3
3
3
3
3/0
I1
11
11
11
11
11
11
I0
Used stack = 10 bytes
TRAP
IT2
IT1
IT4
IT3
IT1
IT2
Hardware priority
RIM
MAIN
11/10
IT0
TRAP
IT0
IT1
IT3
Software priority level
IT4
MAIN
10
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Figure 17. Nested interrupt management
IT2
IT1
IT1
IT2
Hardware priority
RIM
MAIN
11/10
7.5 Interrupt registers
CPU CC register interrupt bits
CPU CC Reset value: 111x 1010 (xAh)
76543210
1I1HI0NZC
Software priority level
IT1
IT2
MAIN
10
IT4
TRAP
IT3
IT0
TRAP
IT0
IT3
IT4
IT4
I1
3
3
2
1
3
3
3/0
11
11
00
01
11
11
I0
Used stack = 20 bytes
R/W R/W R/W R/W R/W R/W R/W
Table 10. CPU CC register description
Bit Bit name Function
Software interrupt priority
These two bits indicate the current interrupt software priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
5, 3 I1, I0
00: Interrupt software priority = level 2
11: Interrupt software priority = level 3 (= interrupt disable
These two bits are set/cleared by hardware when entering in
(1)
)
interrupt. The loaded value is given by the corresponding bits in the
interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT,
WFI, IRET and PUSH/POP instructions (see Table 12: Dedicated
interrupt instruction set).
1. TRAP and reset events can interrupt a level 3 program.
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Interrupt software priority registers (ISPRX)
ISPR0 Reset value: 1111 1111 (FFh)
76543210
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
R/W R/W R/W R/W R/W R/W R/W R/W
ISPR1 Reset value: 1111 1111 (FFh)
76543210
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
R/W R/W R/W R/W R/W R/W R/W R/W
ISPR2 Reset value: 1111 1111 (FFh)
76543210
I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
R/W R/W R/W R/W R/W R/W R/W R/W
ISPR3 Reset value: 1111 1111 (FFh)
76543210
1 1 1 1 I1_13 I0_13 I1_12 I0_12
R R R R R/W R/W R/W R/W
These four registers contain the interrupt software priority of each interrupt vector.
● Each interrupt vector (except reset and TRAP) has corresponding bits in the ISPRx
registers where its own software priority is stored. This correspondance is shown in
Ta bl e 1 1 .
● Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
● Level 0 can not be written (I1_x = 1, I0_x = 0). In this case, the previously stored value
is kept (example, previous = CFh, write = 64h, result = 44h).
Table 11. ISPRx interrupt vector correspondence
Vector address ISPRx bits
FFFBh-FFFAh I1_0 and I0_0 bits*
FFF9h-FFF8h I1_1 and I0_1 bits
--
FFE1h-FFE0h I1_13 and I0_13 bits
The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
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7.6 Interrupt related instructions
Table 12. Dedicated interrupt instruction set
Instruction New description Function/example I1 H I0 N Z C
HALT Entering halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0 = 11 (level 3) I1:0 = 11 ?
JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?
POP CC Pop CC from the stack Mem =>
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software TRAP Software NMI 1 1
WFI Wait for interrupt 1 0
1. During the execution of an interrupt routine, the HALT, POP CC, RIM, SIM and WFI instructions change
the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
7.7 External interrupts
7.7.1 I/O port interrupt sensitivity
(1)
CC I1 H I0 N Z C
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 18). This control allows up to 4 fully independent external interrupt source
sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
● Falling edge
● Rising edge
● Falling and rising edge
● Falling edge and low level
● Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
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Figure 18. External interrupt control bits
Port A3 interrupt
PAOR.3
PADDR.3
PA 3
IPA bit
Port F [2:0] interrupts
PFOR.2
PFDDR.2
PF2
Port B [3:0] interrupts
PBOR.3
PBDDR.3
PB3
IPB bit
EICR
IS20 IS21
Sensitivity
control
EICR
IS21
IS20
Sensitivity
control
EICR
IS10 IS11
Sensitivity
control
PF2
PF1
PF0
PB3
PB2
PB1
PB0
ei0 interrupt source
ei1 interrupt source
ei2 interrupt source
Port B [7:4] interrupts
PBOR.7
PBDDR.7
PB7
EICR
IS10
Sensitivity
control
IS11
PB7
PB6
PB5
PB4
ei3 interrupt source
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7.8 External interrupt control register (EICR)
EICR Reset value: 0000 0000 (00h)
76543210
IS1[1:0] IPB IS2[1:0] IPA Reserved
R/W R/W R/W R/W -
Table 13. EICR register description
Bit Bit name Function
Interrupt sensitivity (ei2 and ei3)
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to
the following external interrupts:
External interrupt ei2 (port B[3:0]):
00: External interrupt sensitivity = falling edge and low level
(IPB bit = 0) and rising edge and high level (IPB bit = 1)
01: External interrupt sensitivity = rising edge only (IPB bit = 0) and
falling edge only (IPB bit = 1)
10: External interrupt sensitivity = falling edge only (IPB bit = 0) and
7:6 IS1[1:0]
5IPB
rising edge only (IPB bit = 1)
11: External interrupt sensitivity = rising and falling edge
(IPB bit = 0 and 1)
External interrupt ei3 (port B[4]):
00: external interrupt sensitivity = falling edge and low level
01: external interrupt sensitivity = rising edge only
10: external interrupt sensitivity = falling edge only
11: external interrupt sensitivity = rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register
are both set to 1 (level 3).
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B [3:0] external
interrupts. It can be set and cleared by software only when I1 and I0
of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
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Table 13. EICR register description (continued)
Bit Bit name Function
Interrupt sensitivity (ei0 and ei1)
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to
the following external interrupts:
External interrupt ei0 (port A[3:0]):
00: External interrupt sensitivity = falling edge and low level
(IPA bit = 0) and rising edge and high level (IPA bit = 1)
01: External interrupt sensitivity = rising edge only (IPA bit = 0) and
falling edge only (IPA bit = 1)
10: External interrupt sensitivity = falling edge only (IPA bit = 0) and
4:3 IS2[1:0]
rising edge only (IPA bit = 1)
11: External interrupt sensitivity = rising and falling edge
(IPA bit = 0 and 1)
External interrupt ei1 port ([F2:0]):
00: External interrupt sensitivity = falling edge and low level
01: External interrupt sensitivity = rising edge only
10: External interrupt sensitivity = falling edge only
11: External interrupt sensitivity = rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register
are both set to 1 (level 3).
Interrupt polarity for port A
2IPA
1:0 -
Reserved, must always be kept cleared
This bit is used to invert the sensitivity of the port A [3:0] external
interrupts. It can be set and cleared by software only when I1 and I0
of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
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7.9 Nested interrupts register map and reset value
0024h
0025h
0026h
0027h
0028h
ISPR0
Reset value
ISPR1
Reset value
ISPR2
Reset value
ISPR3
Reset value 1 1 1 1
EICR
Reset value
ei1 ei0 MCC + SI
I1_31I0_3
1
SPI ei3 ei2
I1_71I0_7
1
AVD SCI Timer B Timer A
I1_111I0_111I1_101I0_101I1_91I0_91I1_8
IS110IS10
0
I1_21I0_21I1_11I0_1
11 1
I1_61I0_61I1_51I0_51I1_4
1
1
I1_131I0_131I1_121I0_12
IPB
0
IS210IS20
0
IPA
00 0
Table 14. Nested interrupts register map and reset values
Address (Hex.) Register label 7 6 5 4 3 2 1 0
7.10 Interrupt mapping
Table 15. Interrupt mapping
I0_4
1
I0_8
1
1
Source
No.
1. Unexpected exit from halt may occur when SPI is in slave mode.
block
Reset Reset
TRAP Software interrupt No No FFFCh-FFFDh
0 Not used FFFAh-FFFBh
1 MCC/RTC
2 ei0 External interrupt port A[3:0]
3 ei1 External interrupt port F[2:0] Yes No FFF4h-FFF5h
4 ei2 External interrupt port B[3:0] Yes No FFF2h-FFF3h
5 ei3 External interrupt port B[7:4] Yes No FFF0h-FFF1h
6 Not used Not used FFEEh-FFEFh
7 SPI SPI peripheral interrupts SPICSR Yes
8 Timer A Timer A peripheral interrupts TASR No No FFEAh-FFEBh
9 Timer B Timer B peripheral interrupts TBSR No No FFE8h-FFE9h
10 SCI SCI peripheral interrupts SCISR No No FFE6h-FFE7h
11 Not used FFE4h-FFE5h
Main clock controller time
base interrupt
Description
Register
label
N/A
MCCSR
N/A
Priority
order
Higher
priority
Lower
priority
Exit from
halt
Yes Yes FFFEh-FFFFh
Yes Yes FFF8h-FFF9h
Yes No FFF6h-FFF7h
(1)
Exit from
active halt
No FFECh-FFEDh
Address vector
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8 Power saving modes
8.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 19): slow, wait (slow
wait), active halt and halt.
After a reset the normal operating mode is selected by default (RUN mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f
From RUN mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 19. Power saving mode transitions
High
Run
OSC2
).
Slow
Wait
Slow wait
Active halt
Halt
Low
Powe r consu mpti on
8.2 Slow mode
This mode has two targets:
● To reduce power consumption by decreasing the internal clock in the device
● To adapt the internal clock frequency (f
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables slow mode and two CPx bits which select the internal slow frequency (f
In this mode, the master clock frequency (f
and peripherals are clocked at this lower frequency (f
Note: Slow wait mode is activated when entering the wait mode while the device is already in slow
mode.
) to the available supply voltage
CPU
) can be divided by 2, 4, 8 or 16. The CPU
OSC2
CPU
).
CPU
).
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Figure 20. Slow mode clock transitions
f
f
CPU
f
OSC2
/2 f
OSC2
OSC2
/4 f
OSC2
8.3 Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in wait mode until an interrupt or reset occurs, whereupon the program counter
branches to the starting address of the interrupt or reset service routine. The MCU remains
in wait mode until a reset or an interrupt occurs, causes it to wake up.
Refer to Figure 21.
CP1:0
SMS
MCCSR
00 01
New slow
frequency request
Normal run mode request
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Figure 21. Wait mode flow-chart
WFI instruction
N
Interrupt
Y
Oscillator
Peripherals
CPU
I[1:0] bits
N
Oscillator
Peripherals
CPU
I[1:0] bits
256 OR 4096 CPU clock
Oscillator
Peripherals
CPU
I[1:0] bits
Reset
Y
cycle delay
ON
ON
OFF
10
ON
OFF
ON
10
ON
ON
ON
XX
(1)
Fetch reset vector or
service interrupt
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
8.4 Active halt and halt modes
Active halt and halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in active
halt or halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register).
Table 16. Active halt and halt power saving modes
MCCSR
OIE bit
0 Halt mode
1 Active halt mode
Power saving mode entered when HALT instruction is executed
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8.4.1 Active halt mode
Active halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the main clock
controller status register (MCCSR) is set (see Section 10.2: Main clock controller with real-
time clock and beeper (MCC/RTC) on page 73 for more details on the MCCSR register).
The MCU can exit active halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see Table 15: Interrupt mapping on page 53) or a reset. When exiting active halt
mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure 23).
When entering active halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In active halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in active halt mode is provided by the oscillator
interrupt.
Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering active halt mode while the watchdog is active does not generate a reset. This
means that the device cannot spend more than a defined delay in this power saving mode.
Caution: When exiting active halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before t
on option byte). Otherwise, the ST7 enters halt mode for the remaining t
after the interrupt occurs (t
DELAY
= 256 or 4096 t
DELAY
delay depending
CPU
DELAY
period.
Figure 22. Active halt timing overview
Active
haltRun Run
HALT
instruction
[MCCSR.OIE = 1]
1. This delay occurs only if the MCU exits active halt mode by means of a reset
256 OR 4096 CPU
cycle delay
Reset or interrupt
(1)
Fetch
vector
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Figure 23. Active halt mode flow-chart
Oscillator
HALT instruction
(MCCSR.OIE = 1)
N
1. Peripheral clocked with an external clock source can still be active
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from active halt mode (such as
external interrupt). Refer to Table 15: Interrupt mapping on page 53 for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
Interrupt
Y
(2)
Peripherals
CPU
I[1:0] bits
N
Oscillator
Peripherals
CPU
I[1:0] bits
256 OR 4096 CPU clock
Oscillator
Peripherals
CPU
I[1:0] bits
(1)
Reset
Y
cycle delay
Fetch reset vector or
service interrupt
ON
OFF
OFF
ON
OFF
ON
XX
ON
ON
ON
XX
10
(3)
(3)
8.4.2 Halt mode
The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the ‘HALT’ instruction when the OIE bit of the main clock controller status register (MCCSR)
is cleared (see Section 10.2: Main clock controller with real-time clock and beeper
(MCC/RTC) on page 73 for more details on the MCCSR register).
The MCU can exit halt mode on reception of either a specific interrupt (see Table 15:
Interrupt mapping on page 53) or a reset. When exiting halt mode by means of a reset or an
interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is
used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25).
When entering halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
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The compatibility of watchdog operation with halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction when executed while the watchdog
system is enabled, can generate a watchdog reset (see Section 14.2 on page 185) for more
details.
Figure 24. Halt timing overview
HaltRun Run
HALT
instruction
[MCCSR.OIE = 1]
256 OR 4096 CPU
cycle delay
Reset or interrupt
Fetch
vector
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Figure 25. Halt mode flow-chart
HALT instruction
(MCCSR.OIE = 0)
WDGHALT
1
Watchdog reset
N
Interrupt
Enable
0
(1)
Oscillator
Peripherals
CPU
I[1:0] bits
N
(3)
Y
Oscillator
Peripherals
CPU
I[1:0] bits
256 or 4096 CPU clock
Watchdog
(2)
Reset
Y
cycle delay
Disable
OFF
OFF
OFF
ON
OFF
ON
XX
10
(4)
Oscillator
Peripherals
CPU
I[1:0] bits
Fetch reset vector or
service interrupt
XX
ON
ON
ON
(4)
1. WDGHALT is an option bit. See Section 14.2: Flash devices for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from halt mode (such as external interrupt). Refer to
Table 15: Interrupt mapping on page 53 for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
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Halt mode recommendations
● Make sure that an external event is available to wake up the microcontroller from halt
mode
● When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as ‘input pull-up with interrupt’ before executing the HALT instruction.
The main reason for this is that the I/O may be wrongly configured due to external
interference or by an unforeseen logical condition.
● For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
● The opcode for the HALT instruction is 0 x 8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
● As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake up event (reset or external
interrupt).
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9 I/O ports
9.1 Introduction
The I/O ports offer different functional modes:
● Transfer of data through digital inputs and outputs
For specific pins they offer different functional modes:
● External interrupt generation
● Alternate signal input/output for the on-chip peripherals
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
9.2 Functional description
Each port has 2 main registers:
● Data register (DR)
● Data direction register (DDR)
Each port also has one optional register:
● Option register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to Section 9.3: I/O port implementation on page 66). The generic
I/O block diagram is shown in Figure 26.
9.2.1 Input modes
The input configuration is selected by clearing the corresponding DDR register bit. In this
case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.
2 When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
3 Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input."
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External interrupt function
When an I/O is configured as input with interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Section 2:
Pin description and Section 7: Interrupts). If several input pins are selected simultaneously
as interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.
9.2.2 Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain.
See Ta bl e 1 7 for the DR register value and output pin status.
Table 17. DR register value and output pin status
DR Push-pull Open-drain
0V
1V
SS
DD
Vss
Floating
9.2.3 Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.
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Figure 26. I/O port general block diagram
Register
access
Data bus
DR
DDR
OR
OR SEL
DDR SEL
DR SEL
Alternate
output
Alternate
enable
If implemented
1
1
0
Pull-up
condition
N-buffer
V
DD
CMOS
Schmitt trigger
P-buffer (see Table below)
Pull-up (see Table below)
V
DD
Pad
Diodes
(see Table below)
Analog input
0
External interrupt
source (eix)
Table 18. I/O port mode options
Alternate input
Diodes
Configuration mode Pull-up P-buffer
to V
DD
Off
(1)
(2)
(1)
(3)
Off
On
NI
(3)
(1)
(2)
(1)
On
NI
(2)
(4)
Input
Output
Floating with/without interrupt Off
Pull-up with/without interrupt On
Push-pull
Open drain (logic level) Off
True open drain NI
1. Implemented not activated
2. Implemented and activated
3. Not implemented
4. The diode to V
implemented to protect the device against positive stress.
is not implemented in the true open drain pads. A local protection between the pad and VSS is
DD
to V
On
SS
(2)
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Table 19. I/O port configurations
(1)
Not implemented in
true open drain
I/O ports
Pad
Input
Not implemented in
(2)
true open drain
I/O ports
Pad
V
DD
R
PU
Hardware configuration
V
DD
R
PU
Pull-up condition
Interrupt condition
DR register access
DR
register
W
R
External interrupt source (eix)
DR register access
DR
register
R/W
Data bus
Alternate input
Analog input
Data bus
Open-drain output
(2)
Push-pull output
Not implemented in
true open drain
I/O ports
Pad
Alternate
enable
V
DD
R
PU
Alternate
enable
DR
register
Alternate
output
DR register access
R/W
Alternate
output
Data bus
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR
register reads the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate
function reads the pin status given by the DR register content.
Caution: The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
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Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
9.3 I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation. The I/O port register
configurations are summarized in Tab l e 2 0 below.
Figure 27. Interrupt I/O port state transitions
01
Input
floating/pull-up
interrupt
00
Input
floating
(reset state)
XX
10
Output
open-drain
=DDR, OR
11
Output
push-pull
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Table 20. Port register configurations
Input (DDR = 0) Output (DDR = 1)
Port Pin name
OR=0 OR=1 OR=0 OR=1
PA[7:6] Floating True open-drain
Por t A
Por t B
PA[5:4]
PA [3 ]
PB[3]
PB[4]
PB[2:0]
Pull-up
Floating interrupt
Pull-up interrupt
Port C PC[7:0]
Port D PD[5:0]
Port E PE[1:0]
PF[7:6]
PF[4]
Por t F
PF[2] Floating interrupt
PF[1:0] Pull-up interrupt
9.4 Low power modes
Table 21. Effect of low power modes on I/O ports
Mode Description
Wait No effect on I/O ports. External interrupts cause the device to exit from wait mode.
Halt No effect on I/O ports. External interrupts cause the device to exit from halt mode.
9.5 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Table 22. I/O interrupt control/wake-up capability
Floating
Open drain Push-pull
Pull-up
Interrupt event Event flag Enable control bit Exit from wait Exit from halt
External interrupt on selected
external event
-
DDRx
ORx
Ye s
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Table 23. I/O port register map and reset values
Address (Hex.) Register label 7 6 5 4 3 2 1 0
Reset value of all I/O port registers 0 0 0 0 0 0 0 0
0000h PADR
MSB LSB0001h PADDR
0002h PAOR
0003h PBDR
MSB LSB0004h PBDDR
0005h PBOR
0006h PCDR
MSB LSB0007h PCDDR
0008h PCOR
0009h PDDR
MSB LSB000Ah PDDDR
000Bh PDOR
000Ch PEDR
000Eh PEOR
000Fh PFDR
0011h PFOR
MSB LSB000Dh PEDDR
MSB LSB0010h PFDDR
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10 On-chip peripherals
10.1 Watchdog timer (WDG)
10.1.1 Introduction
The watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
10.1.2 Main features
● Programmable free-running downcounter
● Programmable reset
● Reset (if watchdog activated) when the T6 bit reaches zero
● Optional reset on HALT instruction (configurable by option byte)
● Hardware watchdog selectable by option byte
10.1.3 Functional description
The counter value stored in the watchdog control register (WDGCR bits T[6:0]), is
decremented every 16384 f
be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the reset pin low
for typically 30µs.
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: it counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:
● The WDGA bit is set (watchdog enabled)
● The T6 bit is set to prevent generating an immediate reset
● The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see Figure 29: Approximate timeout duration).
The timing varies between a minimum and a maximum value due to the unknown
status of the prescaler when writing to the WDGCR register (see Figure 30).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
cycles (approx.), and the length of the timeout period can
OSC2
If the watchdog is activated, the HALT instruction generates a reset.
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Figure 28. Watchdog block diagram
WDGA
Reset
Watchdog control register (WDGCR)
T6 T0
6-bit downcounter (CNT)
WDG prescaler DIV 4
T1T2T3T4T5
MCC/RTC
11
f
OSC2
DIV 64
12-bit MCC
RTC counter
MSB LSB
6
5
0
TB[1:0] bits (MCCSR register)
10.1.4 How to program the watchdog timeout
Figure 29 shows the linear relationship between the 6-bit value to be loaded in the watchdog
counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a
quick calculation without taking the timing variations into account. If more precision is
needed, use the formulae in Figure 30.
Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 29. Approximate timeout duration
3F
38
30
28
20
CNT value (hex.)
18
10
08
00
1.5 65
Watchdog timeout (ms) @ 8 MHz. f
503418 82 98 114
OSC2
128
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Figure 30. Exact timeout duration (t
Where:
t
= (LSB + 128) x 64 x t
min0
t
= 16384 x t
max0
t
= 125ns if f
OSC2
CNT = value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register.
OSC2
OSC2
OSC2
=8 MHz
min
and t
max
)
TB1 bit (MCCSR reg.) TB0 bit (MCCSR reg.) Selected MCCSR timebase MSB LSB
0 0 2ms 4 59
0 1 4ms 8 53
1 0 10ms 20 35
1 1 25ms 49 54
To calculate the minimum watchdog timeout (t
If Then
To calculate the maximum watchdog timeout (t
If Then
MSB
-------------
<
CNT
MSB
-------------
CNT
≤ t
t
Else
Else
t
mintmin0
mintmin0
maxtmax0
t
maxtmax0
16384 CNT
4
4
):
min
16384 CN T t
16384 CN T t
16384 CNT
××+=
osc2
4CNT
⎛⎞
× 192 L S B+()64
max
-----------------
–
⎝⎠
):
××+=
⎛⎞
× 192 L S B+()64
–
⎝⎠
+ t
MSB
osc2
4CNT
-----------------
+ t
MSB
××
4CNT
----------------MSB
4CNT
-----------------
××
MSB
×+=
osc2
×+=
osc2
Note: In the above formulae, division results must be rounded down to the next integer value.
Example: With 2ms timeout selected in MCCSR register
Value of T[5:0] bits in WDGCR register
(Hex.)
Min. watchdog timeout (ms)
t
min
Max. watchdog timeout (ms)
t
max
00 1.496 2.048
3F 128 128.552
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10.1.5 Low power modes
Table 24. Effect of low power modes on watchdog timer
Mode Description
Slow No effect on watchdog.
Wait No effect on watchdog.
OIE bit in
MCCSR
register
00
Halt
0 1 A reset is generated
1x
WDGHALT
bit in option
byte
10.1.6 Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to Section 14.2: Flash devices.
No watchdog reset is generated. The MCU enters halt mode.
The watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
until the MCU receives an external interrupt or a reset.
If an external interrupt is received, the watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the watchdog is disabled (reset state) unless hardware
watchdog is selected by option byte. For application
recommendations see Section 10.1.7 below.
No reset is generated. The MCU enters active halt mode. The
watchdog counter is not decremented. It stops counting. When
the MCU receives an oscillator interrupt or external interrupt,
the watchdog restarts counting immediately. When the MCU
receives a reset the watchdog restarts counting after 256 or
4096 CPU clocks.
10.1.7 Using halt mode with the WDG (WDGHALT option)
The following recommendation applies if halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
10.1.8 Interrupts
None
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10.1.9 Control register (WDGCR)
WDGCR Reset value: 0111 1111 (7Fh)
76543210
WDGA T[6:0]
R/W R/W
Table 25. WDGCR register description
Bit Bit name Function
Activation bit
This bit is set by software and only cleared by hardware after a reset.
7WDGA
6:0 T[6:0]
1. The WDGA bit is not used if the hardware watchdog option is enabled by option byte.
When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. They are
decremented every 16384 f
produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
(1)
cycles (approx.). A reset is
OSC2
10.1.10 Watchdog timer register map and reset values
Table 26. Watchdog timer register map and reset values
Address(Hex.)Register label7 6543210
10.2
002Ah
WDGCR
Reset value
Main clock controller with real-time clock and beeper
WDGA0T6
T5
1
1
T4
1
T3
T2
1
T1
1
T0
1
1
(MCC/RTC)
The main clock controller consists of three different functions:
●
A programmable CPU clock prescaler
●
A clock-out signal to supply external devices
●
A real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
10.2.1
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages slow power saving mode (see Section 8.2: Slow mode for more
details).
The prescaler selects the f
MCCSR register: CP[1:0] and SMS.
main clock frequency and is controlled by three bits in the
CPU
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10.2.2
Caution:
10.2.3
10.2.4
Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a f
to drive external devices. It is controlled by the MCO bit in the MCCSR register.
When selected, the clock out pin suspends the clock during active halt mode.
OSC2
clock
Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on f
are available.
OSC2
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters active halt mode when the
HALT instruction is executed. See Section 8.4: Active halt and halt modes for more details.
Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).
Figure 31.
Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
f
OSC2
DIV 64
MCO
MCCSR
DIV 2, 4, 8, 16
Beep signal
selection
12-bit MCC RTC
counter
SMSCP1 CP0 TB1 TB0 OIE OIF
1
0
To watchdog timer
MCC/RTC interrupt
f
CPU
Beep
MCO
CPU clock
to CPU and
peripherals
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10.2.5
10.2.6
Low power modes
Table 27. Effect of low power modes on MCC/RTC
Mode Description
Wait
Active halt
Halt
No effect on MCC/RTC peripheral
MCC/RTC interrupt causes the device to exit from wait mode
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen
MCC/RTC interrupt causes the device to exit from active halt mode
MCC/RTC counter and registers are frozen
MCC/RTC operation resumes when the MCU is woken up by an interrupt with
‘exit from halt’ capability
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
Table 28. MCC/RTC interrupt control/wake-up capability
Interrupt event Event flag Enable control bit Exit from wait Exit from halt
Time base overflow event OIF OIE Yes No
1. The MCC/RTC interrupt wakes up the MCU from active halt mode, not from halt mode.
(1)
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10.2.7
MCC/RTC registers
MCC control/status register (MCCSR)
MCCSR Reset value: 0000 0000 (00h)
76543210
MCO CP[1:0] SMS
TB[1:0]
R/W R/W R/W R/W R/W R/W
Table 29. MCCSR register description
Bit Bit name Function
Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is
set and cleared by software.
7MCO
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
CPU
Note: To reduce power consumption, the MCO function is not active
in active halt mode.
CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the
different slow modes. Their action is conditioned by the setting of the
6:5 CP[1:0]
SMS bit. These two bits are set and cleared by software.
00: f
01: f
10: f
11: f
in slow mode = f
CPU
in slow mode = f
CPU
in slow mode = f
CPU
in slow mode = f
CPU
OSC2
OSC2
OSC2
OSC2
/2
/4
/8
/16
Slow mode select
This bit is set and cleared by software.
4SMS
0: Normal mode, f
1: Slow mode, f
CPU=fOSC2
is given by CP1, CP0; see Section 8.2: Slow
CPU
mode and Section 10.2: Main clock controller with real-time clock
and beeper (MCC/RTC) for more details.
OIE OIF
on I/O port)
Time base control
These bits select the programmable divider time base. They are set
and cleared by software:
OSC2
OSC2
OSC2
=4MHz)
=4MHz)
=4MHz)
3:2
TB[1:0]
00: Time base (for counter prescaler 16000) = 4ms (f
and 2ms (f
OSC2
=8MHz)
01: Time base (for counter prescaler 32000) = 8ms (f
and 4ms (f
OSC2
=8MHz)
10: Time base (for counter prescaler 80000) = 20ms (f
and 10ms (f
OSC2
=8MHz)
11: Time base (for counter prescaler 200000) = 50ms
(f
= 4MHz) and 25ms (f
OSC2
A modification of the time base is taken into account at the end of the
current period (previously set) to avoid an unwanted time shift. This
OSC2
=8MHz)
allows use of this time base as a real-time clock.
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Table 29. MCCSR register description (continued)
Bit Bit name Function
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1OIE
1: Oscillator interrupt enabled
This interrupt can be used to exit from active halt mode. When this
bit is set, calling the ST7 software HALT instruction enters the active
halt power saving mode
.
Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the
MCCSR register. It indicates when set that the main oscillator has
0OIF
reached the selected elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the
MCCSR register to avoid unintentionally clearing the OIF bit.
MCC beep control register (MCCBCR)
MCCBCR Reset value: 0000 0000 (00h)
76543210
Reserved BC[1:0]
-R/W
Table 30. MCCBCR register description
Bit Bit name Function
7:2 - Reserved, must be kept cleared
Beep control
These 2 bits select the PF1 pin beep capability:
00: Beep mode (with f
01: Beep mode (with f
=8MHz)=off
OSC2
= 8MHz) = ~2-KHz (output beep
OSC2
signal ~ 50% duty cycle)
1:0 BC[1:0]
10: Beep mode (with f
= 8MHz) = ~1-KHz (output beep
OSC2
signal ~ 50% duty cycle)
11: beep mode (with f
= 8MHz) = ~500-Hz (output beep
OSC2
signal ~ 50% duty cycle)
The beep output signal is available in active halt mode but has to be
disabled to reduce the consumption.
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10.2.8 MCC register map and reset values
Table 31. Main clock controller register map and reset values
Address(Hex.) Register label 7 6 5 4 3 2 1 0
002Ch
002Dh
10.3 16-bit timer
10.3.1 Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
MCCSR
Reset value
MCCBCR
Reset value 0 0 0 0 0 0
MCO0CP10CP00SMS0TB10TB00OIE0OIF
0
BC10BC0
0
10.3.2 Main features
● Programmable prescaler: f
● Overflow status flag and maskable interrupt
● External clock input (must be at least 4 times slower than the CPU clock speed) with
the choice of active edge
● 1 or 2 output compare functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
● 1 or 2 input capture functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
● Pulse width modulation mode (PWM
● One pulse mode
divided by 2, 4 or 8
CPU
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● Reduced power mode
● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)
(a)
The block diagram is shown in Figure 32.
10.3.3 Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter register (CR)
● Counter high register (CHR) is the most significant byte (MS byte)
● Counter low register (CLR) is the least significant byte (LS byte)
Alternate counter register (ACR)
● Alternate counter high register (ACHR) is the most significant byte (MS byte)
● Alternate counter low register (ACLR) is the least significant byte (LS byte)
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR), (see 16-bit read sequence (from either the counter register or alternate
counter register) on page 81).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM
mode.
The timer clock depends on the clock control bits (bits 3 and 2) of the CR2 register, as
illustrated in Table 36: CR2 register description. The value in the counter register repeats
every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The
timer frequency can be f
CPU
/2, f
CPU
/4, f
/8 or an external frequency.
CPU
Caution: In Flash devices, Timer A functionality has the following restrictions:
● TAOC2HR and TAOC2LR registers are write only
● Input capture 2 is not implemented
● The corresponding interrupts cannot be used (ICF2, OCF2 forced by hardware to zero)
a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout
description. When reading an input signal on a non-bonded pin, the value is always ‘1’.
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Figure 32. Timer block diagram
ST7 internal bus
f
CPU
MCU-peripheral interface
EXTCLK
pin
CC[1:0]
EXEDG
1/2
1/4
1/8
Overflow detect
8 high
Counter register
Alternate counter
circuit
8-bit
buffer
register
8 low
8
88 8
High Low High Low High Low High Low
16
Output
compare
register
1
16
Timer internal bus
16 16
Output compare circuit
6
Output
compare
register
2
8
Input
capture
register
1
Edge detect circuit 1
Edge detect circuit 2
8 8 8
Input
capture
register
2
16 16
ICAP1
pin
ICAP2
pin
Latch1
ICF2ICF1
OCF2OCF1 TOF
TIMD
CSR (control/status register)
CR1 (control register 1)
(1)
Timer interrupt
1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 15: Interrupt mapping on page 53).
0
0
Latch2
OC2E
PWMOC1E
OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TO IE
IEDG2CC0CC1
CR2 (control register 2)
OCMP1
OCMP2
EXEDG
pin
pin
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16-bit read sequence (from either the counter register or alternate counter register)
Figure 33. 16-bit read sequence
Beginning of the sequence
Read MS byte
At t0
Other
instructions
LS byte is buffered
At t0 +∆t
Sequence completed
Read LS byte
Returns buffered LS byte
value at t0
The user must read the MS byte first, then the LS byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
● The TOF bit of the SR register is set
● A timer interrupt is generated if the TOIE bit of the CR1 register is set and the I bit of the
CC register is cleared
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set
2. An access (read or write) to the CLR register
Note: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by wait mode.
In halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a reset).
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External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that triggers the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 34. Counter timing diagram, internal clock divided by 2
CPU clock
Internal reset
Timer clock
FFFD
Counter register
Timer overflow flag (TOF)
FFFE FFFF 0000 0001 0002 0003
Figure 35. Counter timing diagram, internal clock divided by 4
CPU clock
Internal reset
Timer clock
Counter register
Timer overflow flag (TOF)
FFFC
FFFD
0000 0001
Figure 36. Counter timing diagram, internal clock divided by 8
CPU clock
Internal reset
Timer clock
Counter register
Timer overflow flag (TOF)
FFFC
FFFD
0000
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is
running.
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Input capture
In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the
16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see below).
MSB LSB
ICiR ICiHR ICiLR
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter: (
f
CPU
/CC[1:0]).
Procedure
To use the input capture function select the following in the CR2 register:
● The timer clock (CC[1:0]) (see Table 36: CR2 register description)
● The edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Select the following in the CR1 register:
● Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin.
● Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
When an input capture occurs:
● ICFi bit is set
● The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 38).
● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1. By reading the SR register while the ICFi bit is set
2. By accessing (reading or writing) the ICiLR register
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Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi is never
set until the ICiLR register is also read.
2 The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
3 The 2 input capture functions can be used together even if the timer also uses the 2 output
compare functions.
4 In one pulse mode and PWM mode only input capture 2 can be used.
5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR
(see note 1).
6 The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
7 In Flash devices, the ICAP2 registers (TAIC2HR, TAIC2LR) are not available on Timer A.
The corresponding interrupts cannot be used (ICF2 is forced by hardware to 0).
Figure 37. Input capture block diagram
ICAP1
pin
ICAP2
pin
Edge detect
circuit 2
IC2R register
16-bit
16-bit free running counter
Edge detect
circuit 1
IC1R register
CR1 (control register 1)
ICIE
SR (status register)
ICF1 000
ICF2
CR2 (control register 2)
CC0CC1
IEDG1
IEDG2
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Figure 38. Input capture timing diagram
Timer clock
Counter register
ICAPi pin
ICAPi flag
ICAPi register
1. The rising edge is the active edge.
FF01
FF02 FF03
FF03
Output compare
In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the output compare register and the free running counter,
the output compare function:
● Assigns pins with a programmable value if the OCiE bit is set
● Sets a flag in the status register
● Generates an interrupt if enabled
Two 16-bit registers, output compare register 1 (OC1R) and output compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle (see
below).
MSB LSB
OCiROCiHR OCiLR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OC
Timing resolution is one count of the free running counter: (
iR value to 8000h.
f
CPU/
CC[1:0]
).
Procedure
To use the output compare function, select the following in the CR2 register:
● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
● Select the timer clock (CC[1:0]) (see Table 36: CR2 register description)
Select the following in the CR1 register:
● Select the OLVLi bit to applied to the OCMPi pins after the match occurs
● Set the OCIE bit to generate an interrupt if it is needed
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When a match is found between OCRi register and CR register:
● OCFi bit is set
● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)
● A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OC
iR register value required for a specific timing application can be calculated using
the following formula:
∆t * f
∆ OCiR=
CPU
PRESC
Where:
∆t = Output compare period (in seconds)
f
= CPU clock frequency (in hertz)
CPU
= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 36: CR2
PRESC
register description)
If the timer clock is an external clock, the formula is:
∆ OCiR=∆t
* fEXT
Where:
∆t = Output compare period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set
2. Accessing (reading or writing) the OCiLR register
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OC
● Write to the OCiHR register (further compares are inhibited)
● Read the SR register (first step of the clearance of the OCFi bit, which may be already
iR register:
set)
● Write to the OCiLR register (enables the output compare function and clears the OCFi
bit)
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Note: 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit does not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 40 on page 88 for an example with f
Figure 41 on page 88 for an example with f
/4). This behavior is the same in OPM or
CPU
CPU
/2 and
PWM mode.
4 The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
5 The value in the 16-bit OC
iR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
6 In Flash devices, the TAOC2HR, TAOC2LR registers are ‘write only’ in Timer A. The
corresponding event cannot be generated (OCF2 is forced by hardware to 0).
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
Figure 39. Output compare block diagram
16 bit free running counter
16-bit
Output compare circuit
16-bit
OC1R register
16-bit
OC2R register
OC1E CC0CC1OC2E
FOLV2 FOLV1
CR2 (control register 2)
CR1 (control register 1)
OLVL1OLVL2OCIE
000OCF2OCF1
SR (status register)
Latch
1
Latch
2
OCMP1
pin
OCMP2
pin
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Figure 40. Output compare timing diagram, f
Internal CPU clock
Timer clock
Counter register
Output compare register i (OCRi)
Output compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
2ED0 2ED1 2ED2 2ED3 2ED42ECF
Figure 41. Output compare timing diagram, f
Internal CPU clock
Timer clock
Counter register
Output compare register i (OCRi)
Output compare flag i (OCFi)
TIMER=fCPU
2ED3
TIMER=fCPU
2ED0 2ED1 2ED2
2ED3
/2
/4
2ED3
2ED42ECF
OCMPi pin (OLVLi = 1)
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One pulse mode
One pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the input capture1 function and the output compare1 function.
Procedure
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse using
the appropriate formula below according to the timer clock source used
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse
– Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input)
3. Select the following in the CR2 register:
– Set the OC1E bit (the OCMP1 pin is then dedicated to the output compare 1
function)
– Set the OPM bit
– Select the timer clock CC[1:0] (see Table 36: CR2 register description)
Figure 42. One pulse mode sequence
One pulse mode cycle
When event occurs
on ICAP1
When
counter = OCIR
ICR1 = counter
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set
2. Accessing (reading or writing) the ICiLR register
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The OC1R register value required for a specific timing application can be calculated using
the following formula:
OCiR value =
* fCPU
PRESC
- 5
t
Where:
t = Pulse period (in seconds)
f
= CPU clock frequency (in hertz)
CPU
= Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 36: CR2
PRESC
register description)
If the timer clock is an external clock the formula is:
OCiR=t
f
-5
EXT
*
Where:
t = Pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (see Figure 43).
Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an output compare interrupt.
2 When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3 If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
6 In Flash devices, Timer A OCF2 bit is forced by hardware to 0.
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Figure 43. One pulse mode timing example
IC1R
FFFC FFFD FFFE 2ED0 2ED1 2ED2
Counter
ICAP1
OCMP1
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
01F8
OLVL2
01F8
2ED3
OLVL1
Compare1
2ED3
FFFC FFFD
OLVL2
Figure 44. Pulse width modulation mode timing example with 2 output compare
functions
Counter
OCMP1
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
FFFC FFFD FFFE
34E2
Compare2
OLVL2
2ED0 2ED1 2ED2
OLVL1
Compare1
34E2 FFFC
OLVL2
Compare2
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Pulse width modulation mode
Pulse width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse width modulation mode uses the complete output compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the appropriate formula below according to the timer clock source used
2. Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the appropriate formula below according to the timer
clock source used
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register
4. Select the following in the CR2 register:
– Set OC1E bit (the OCMP1 pin is then dedicated to the output compare 1 function)
– Set the PWM bit
– Select the timer clock (CC[1:0]) (see Table 36: CR2 register description)
Figure 45. Pulse width modulation cycle
Pulse width modulation cycle
When
counter = OC1R
When
counter = OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
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The OCiR register value required for a specific timing application can be calculated using
the following formula::
OCiR value =
* fCPU
PRESC
- 5
t
Where:
t = Signal or pulse period (in seconds)
f
= CPU clock frequency (in hertz)
CPU
= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Ta bl e 3 6 )
PRESC
If the timer clock is an external clock the formula is:
OCiR=t
f
-5
EXT
*
Where:
t = Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
The output compare 2 event causes the counter to be initialized to FFFCh (see Figure 44)
Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
compare interrupt is inhibited.
3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5 When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
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10.3.4 Low power modes
Table 32. Effect of low power modes on 16-bit timer
Mode Description
Wait
Halt
No effect on 16-bit timer.
Timer interrupts cause the device to exit from wait mode.
16-bit timer registers are frozen.
In halt mode, the counter stops counting until halt mode is exited. Counting resumes from
the previous count when the MCU is woken up by an interrupt with ‘exit from halt mode’
capability or from the counter reset value when the MCU is woken up by a reset.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with ‘exit from halt mode’
capability, the ICFi bit is set, and the counter value present when exiting from halt mode is
captured into the ICiR register.
10.3.5 Interrupts
Table 33. 16-bit timer interrupt control/wake-up capability
Interrupt event Event flag Enable control bit Exit from wait Exit from halt
Input capture 1 event/counter
reset in PWM mode
Input capture 2 event ICF2
Output compare 1 event
(not available in PWM mode)
Output compare 2 event
(not available in PWM mode)
ICF1
OCF1
OCF2
(1)
ICIE
Ye s N o
OCIE
Timer overflow event TOF TOIE
1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts).
These events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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10.3.6 Summary of timer modes
Table 34. Summary of timer modes
Timer resources
Modes
Input capture
(1)
Output compare
and/or
(1)
and/or
(2)
(2)
Input
capture 1
Ye s
Input
capture 2
(2)
Ye s
Ye s
Output
Output compare
compare 1
Ye s Ye s
2
One pulse mode
PWM mode
1. See note 4 in One pulse mode on page 89
2. See note 5 and 6 in One pulse mode on page 89
3. See note 4 in Pulse width modulation mode on page 92
10.3.7 16-bit timer registers
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
CR1 Reset value: 0000 0000 (00h)
76543210
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
R/W R/W R/W R/W R/W R/W R/W R/W
Table 35. CR1 register description
No
Not
recommended
Not
recommended
(1)
(3)
No
Partially
No
(2)
Bit Bit name Function
Input capture interrupt enable
7ICIE
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the
SR register is set
Output compare interrupt enable
6OCIE
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of
the SR register is set
Timer overflow interrupt enable
5 TOIE
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR
register is set
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Table 35. CR1 register description (continued)
Bit Bit name Function
Forced output compare 2
This bit is set and cleared by software.
4FOLV2
3FOLV1
2OLVL2
1IEDG1
0: No effect on the OCMP2 pin
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E
bit is set and even if there is no successful comparison
Forced output compare 1
This bit is set and cleared by software.
0: No effect on the OCMP1 pin
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is
set and even if there is no successful comparison
Output level 2
This bit is copied to the OCMP2 pin whenever a successful
comparison occurs with the OC2R register and OCxE is set in the
CR2 register. This value is copied to the OCMP1 pin in one pulse
mode and pulse width modulation mode.
Input edge 1
This bit determines which type of level transition on the ICAP1 pin
triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
Output level 1
0OLVL1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful
comparison occurs with the OC1R register and the OC1E bit is set in
the CR2 register.
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Control register 2 (CR2)
CR2 Reset value: 0000 0000 (00h)
76543210
OC1E OC2E OPM PWM CC[1:0] IEDG2 EXEDG
R/W R/W R/W R/W R/W R/W R/W
Table 36. CR2 register description
Bit Bit name Function
Output compare 1 pin enable
This bit is used only to output the signal from the timer on the
OCMP1 pin (OLV1 in output compare mode, both OLV1 and OLV2 in
7OCIE
6OC2E
5OPM
4PWM
3:2 CC[1:0]
PWM and one-pulse mode). Whatever the value of the OC1E bit, the
output compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for
general-purpose I/O)
1: OCMP1 pin alternate function enabled
Output compare 2 pin enable
This bit is used only to output the signal from the timer on the
OCMP2 pin (OLV2 in output compare mode). Whatever the value of
the OC2E bit, the output compare 2 function of the timer remains
active.
0: OCMP2 pin alternate function disabled (I/O pin free for generalpurpose I/O)
1: OCMP2 pin alternate function enabled
One pulse mode
0: One pulse mode is not active
1: One pulse mode is active, the ICAP1 pin can be used to trigger
one pulse on the OCMP1 pin; the active transition is given by the
IEDG1 bit. The length of the generated pulse depends on the
contents of the OC1R register.
Pulse width modulation
0: PWM mode is not active
1: PWM mode is active, the OCMP1 pin outputs a programmable
cyclic signal; the length of the pulse depends on the value of OC1R
register; the period depends on the value of OC2R register.
Clock control
The timer clock mode depends on the following bits:
00: timer clock = f
01: timer clock = f
10: timer clock = f
11: timer clock = external clock (where available)
Note: If the external clock pin is not available, programming the
external clock configuration stops the counter.
CPU
CPU
CPU
/4
/2
/8
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Table 36. CR2 register description (continued)
Bit Bit name Function
Input edge 2
This bit determines which type of level transition on the ICAP2 pin
1IEDG2
0 EXEDG
triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
External clock edge
This bit determines which type of level transition on the external
clock pin EXTCLK triggers the counter register.
0: A falling edge triggers the counter register
1: A rising edge triggers the counter register
Control/status register (CSR)
CSR Reset value: xxxx x0xx (xxh)
76543210
ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved
RRRRRR/W -
Table 37. CSR register description
Bit Bit name Function
Input capture flag 1
0: No input capture (reset value)
7ICF1
6OCF1
5TOF
4ICF2
1: An input capture has occurred on the ICAP1 pin or the counter
has reached the OC2R value in PWM mode. To clear this bit, first
read the SR register, then read or write the low byte of the IC1R
(IC1LR) register.
Output compare flag 1
0: No match (reset value)
1: The content of the free running counter has matched the content
of the OC1R register. To clear this bit, first read the SR register, then
read or write the low byte of the OC1R (OC1LR) register.
Timer overflow flag
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To
clear this bit, first read the SR register, then read or write the low
byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF
Input capture flag 2
0: No input capture (reset value)
1: An input capture has occurred on the ICAP2 pin. To clear this bit,
first read the SR register, then read or write the low byte of the IC2R
(IC2LR) register.
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Table 37. CSR register description (continued)
Bit Bit name Function
Output compare flag 2
0: No match (reset value)
3OCF2
2TIMD
1:0 - Reserved, must be kept cleared
1: The content of the free running counter has matched the content
of the OC2R register. To clear this bit, first read the SR register, then
read or write the low byte of the OC2R (OC2LR) register.
Timer disable
This bit is set and cleared by software. When set, it freezes the timer
prescaler and counter and disables the output functions (OCMP1
and OCMP2 pins) to reduce power consumption. Access to the timer
registers is still available, allowing the timer configuration to be
changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
IC1HR Reset value: undefined
76543210
MSB LSB
RRRRRRRR
Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
IC1LR Reset value: undefined
76543210
MSB LSB
RRRRRRRR
Output compare 1 high register (OC1HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC1HR Reset value: 1000 0000 (80h)
76543210
MSB LSB
R/W R/W R/W R/W R/W R/W R/W R/W
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Output compare 1 low register (OC1LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC1LR Reset value: 0000 0000 (00h)
76543210
MSB LSB
R/W R/W R/W R/W R/W R/W R/W R/W
Output compare 2 high register (OC2HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC2HR Reset value: 1000 0000 (80h)
76543210
MSB LSB
R/W R/W R/W R/W R/W R/W R/W R/W
Output compare 2 low register (OC2LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC2LR Reset value: 0000 0000 (00h)
76543210
MSB LSB
R/W R/W R/W R/W R/W R/W R/W R/W
Counter high register (CHR)
This is an 8-bit register that contains the high part of the counter value.
CHR Reset value: 1111 1111 (FFh)
76543210
MSB LSB
RRRRRRRR
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