ST ST7232AK1, ST7232AK2, ST7232AJ1, ST7232AJ2 User Manual
ST7232AK1-Auto ST7232AK2-Auto
Obsolete Product(s) - Obsolete Product(s)
ST7232AJ1-Auto ST7232AJ2-Auto
8-bit MCU for automotive, 16 Kbyte Flash/ROM,
Features
■ Memories
– 8K dual voltage high density Flash
(HDFlash) or ROM with read-out protection
capability. In-application programming and
in-circuit programming for HDFlash devices
– 384 bytes RAM
– HDFlash endurance: 100 cycles, data
retention: 20 years at 55°C
■ Clock, reset and supply management
– Clock sources: crystal/ceramic resonator
oscillators and bypass for external clock
– PLL for 2x frequency multiplication
– Four power saving modes: halt, active halt,
wait and slow
■ Interrupt management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and reset
– 6 external interrupt lines (on 4 vectors)
■ Up to 32 I/O ports
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
■ 4 timers
Table 1. Device summary
10-bit ADC, 4 timers, SPI, SCI
LQFP32 7 x 7
– Main clock controller with: real time base,
beep and clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2
output compares, PWM and pulse
generator modes
■ 2 communications interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
■ 1 analog peripheral (low current coupling)
– 10-bit ADC with up to 12 robust input ports
■ Instruction set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development tools
– Full hardware/software development
package
– In-circuit testing capability
LQFP44 10 x 10
Program memory - bytes RAM (stack) - bytes Operating volt. Temp. range Package
ST72F32AK1-Auto Flash 4K
ST72F32AK2-Auto Flash 8K
ST72F32AJ1-Auto Flash 4K
ST72F32AJ2-Auto Flash 8K
ST7232AK1-Auto ROM 4K
ST7232AK2-Auto ROM 8K
ST7232AJ1-Auto ROM 4K
ST7232AJ2-Auto ROM 8K
January 2008 Rev 1 1/201
384 (256) 3.8V to 5.5V
-40°C to
+125°C
LQFP32
LQFP44
LQFP32
LQFP44
www.st.com
1
Obsolete Product(s) - Obsolete Product(s)
Contents ST7232Axx-Auto
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 Differences between ST7232A-Auto and ST7232A datasheets . . . . . . . . 15
1.2.1 Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.2 Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.3 Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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6.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Contents
6.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.2 Asynchronous external RESET
6.5.3 External power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5.4 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.6 System integrity management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.2 Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.3 Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.4 Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.6 Interrupt related instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.7 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.7.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.8 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.9 Nested interrupts register map and reset value . . . . . . . . . . . . . . . . . . . . 53
7.10 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.4 Active halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.4.1 Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Contents ST7232Axx-Auto
9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.1.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.6 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.7 Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 72
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.9 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.1.10 Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . 73
10.2 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 73
10.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.3 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.7 MCC/RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.2.8 MCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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10.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.4.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.4.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.5 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.6 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.6 10-bit ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.1.1 Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.2 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.3 Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.4 Indexed instructions (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . 147
11.1.5 Indirect instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.6 Indirect indexed instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . 148
11.1.7 Relative mode instructions (direct, indirect) . . . . . . . . . . . . . . . . . . . . . 149
11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.3 Using a pre-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.2 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.5.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 162
12.5.4 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.7 Electromagnetic compatability (EMC) characteristics . . . . . . . . . . . . . . 165
12.7.1 Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 165
12.7.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 167
12.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.2 ICCSEL/V
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
12.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.10.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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12.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 175
12.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 179
12.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.3 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 185
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3 ROM device ordering information and transfer of customer code . . . . . 188
14.4 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 193
14.5 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.1 Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.3 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.1.4 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 196
15.1.5 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 197
15.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
15.1.8 39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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15.2 ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.1 I/O port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
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ST7232Axx-Auto List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4. Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. CC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. ST7 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8. SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 10. CPU CC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 11. ISPRx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 12. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 13. EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 14. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 15. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16. Active halt and halt power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 18. I/O Port Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 19. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 20. Port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 21. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 22. I/O interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 23. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 24. Effect of low power modes on watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 25. WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 26. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 27. Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 28. MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 29. MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 30. MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 31. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 32. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 33. 16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 34. Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 35. CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 36. CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 37. CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 38. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 39. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 40. SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 41. SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 42. SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 43. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 44. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 45. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 46. SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 47. SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 48. SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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Table 49. SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 50. SCIBRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 51. SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 52. SCIETPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 53. Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 54. SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 55. Effect of low power modes on 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 56. ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 57. ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 58. ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 59. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 60. CPU addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 61. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 62. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 63. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 64. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 148
Table 65. Short instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 66. Relative mode instructions (direct and indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 67. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 68. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 69. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 70. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 71. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 72. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 73. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 74. Supply current of clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 75. On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 76. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 77. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 78. Oscillator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 79. Examples of typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 81. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 82. Characteristics of dual VOLTAGE HDFlash MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 83. Electromagnetic test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 85. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 86. Latch up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 87. I/O general port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 88. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 89. Asynchronous RESET
Table 90. ICCSEL/V
Table 91. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 92. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 93. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 94. ADC accuracy with V
Table 95. 32-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 96. 44-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 97. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 98. Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 184
Table 99. Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. Option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
= 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DD
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ST7232Axx-Auto List of tables
Table 101. Option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 103. Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 104. FASTROM factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 105. ROM factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 106. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 107. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 108. Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 109. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
11/201
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List of figures ST7232Axx-Auto
List of figures
Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. 32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. 44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. Memory map and sector addresses of the ST7232X family . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 19. Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 20. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. Wait mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. Active halt Mode Flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25. Halt mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 26. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 28. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 29. Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 30. Exact timeout duration (t
Figure 31. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 32. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 33. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 34. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 35. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 36. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 37. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 38. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 39. Output compare block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 40. Output compare timing diagram, f
Figure 41. Output compare timing diagram, f
Figure 42. One pulse mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 43. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 44. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . . 91
Figure 45. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 46. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 47. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 48. Generic SS
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
min
and t
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
max
TIMER=fCPU
TIMER=fCPU
/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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ST7232Axx-Auto List of figures
Figure 49. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 50. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 51. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 111
Figure 52. Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 53. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 54. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 55. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 56. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 57. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 58. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 59. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 60. f
Figure 61. Typical I
Figure 62. Typical I
Figure 63. Typical I
Figure 64. Typ. I
max versus V
CPU
DD
DD
DD
in slow wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DD
in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 65. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 66. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 67. Integrated PLL jitter vs signal frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 68. Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 69. Typical I
Figure 70. Typical V
Figure 71. Typ. V
Figure 72. Typical V
Figure 73. Typical V
Figure 74. Typical V
Figure 75. Typical V
Figure 76. RESET
Figure 77. Two typical applications with ICCSEL/V
vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
PU
at VDD= 5V (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
OL
at VDD= 5V (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OL
at VDD= 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OH
vs. VDD (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OL
vs. VDD (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
OL
vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
OH
pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
Figure 78. SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 79. SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 80. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 81. R
Figure 82. Recommended C
max. vs f
AIN
ADC
with C
and R
AIN
= 0pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
AIN
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
AIN
Figure 83. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 84. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 85. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 86. 32-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 87. 44-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 88. Flash commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 89. FASTROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 90. ROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Introduction ST7232Axx-Auto
1 Introduction
1.1 Description
The ST7232AK1-Auto, ST7232AK2-Auto, ST7232AJ1-Auto, and ST7232AJ2-Auto devices
are members of the ST7 microcontroller family designed for the 5V operating range.
The 32 and 44-pin devices are designed for mid-range applications
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory.
Under software control, all devices can be placed in wait, slow, active halt or halt mode,
reducing power consumption when the application is in idle or stand-by state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8 x 8 unsigned multiplication and indirect addressing modes.
Figure 1. Device block diagram
8-bit core
ALU
RESET
V
PP
V
SS
V
DD
OSC1
OSC2
V
V
AREF
SSA
Control
OSC
ADDRESS AND DATA BUS
MCC/RTC/beep
PORT F
Timer A
Beep
Por t E
SCI
Por t D
10-bit ADC
Program
memory
(8K bytes)
RAM
(384 bytes)
Watchdog
Por t A
Por t B
Por t C
Timer B
SPI
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ST7232Axx-Auto Introduction
1.2 Differences between ST7232A-Auto and ST7232A datasheets
The differences between the ST7232A-Auto datasheet, version 1, released in January 2008
and the ST7232A datasheet, version 2, released in December 2005 are listed below.
Differences are categorised as follows:
● Principal differences
● Minor content differences
● Editing and formatting differences
1.2.1 Principal differences
1. Changed root part number from ST7232A to ST7232AK1-Auto, ST7232AK2-Auto,
ST7232AJ1-Auto, and ST7232AJ2-Auto throughout document
2. Changed document title on page 1
3. Removed 1 and 5 suffix version temperatures ranges throughout the document
4. Features on page 1: Changed minimum value of data retention time (t
and changed the condition to T
5. Table 2: Device pin description on page 21: Added footnote
= 55°C
A
(5)
6. Section 6.3: Phase locked loop (PLL) on page 36: Added caution regarding use of PLL
with an external clock
7. Reset vector fetch on page 38: Added a ‘caution’ about the reset vector when it is not
programmed
8. Section 9.2.1: Input modes on page 62: Amended note3 of this section
9. Section 9.3: I/O port implementation on page 66: Deleted I/O port implementation
tables
10. Output compare on page 85: Amended text in note 3
11. Figure 41: Output compare timing diagram, fTIMER = fCPU/4 on page 88: Removed
compare register i Latch from diagram
12. Section 10.6: 10-bit A/D converter (ADC) on page 139: Amended text concerning the
EOC bit in Starting the conversion
13. Table 70: Current characteristics on page 155:
– Added data for the LQFP44 package to I
– Updated max I
values for standard I/O and high sink I/O
IO
VDD
and I
VSS
14. Table 72: General operating conditions on page 156: Updated temperature ranges in
the ‘conditions’ column
15. Table 82: Characteristics of dual VOLTAGE HDFlash MEMORY on page 164:
– Changed typical value of supply current (I
– Changed minimum value of data retention time (t
condition to T
= 55°C
A
– Changed the condition of write erase cycle (N
) to < 10µA
DD
RET
RW
) to 20 years and changed the
) to TA = 85°C
16. Section 12.7.3: Absolute maximum ratings (electrical sensitivity) on page 167:
Removed text concerning dynamic latch-up
17. Electro-static discharge (ESD) on page 167: Replaced JESD22-A114A/A115A
standard with AEC-Q100-002/003/011 standard
) to 20 years
RET
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Introduction ST7232Axx-Auto
18. Table 85: ESD absolute maximum ratings on page 167:
– Added test standards to conditions column
– Changed max value of CDM from 250 V to: > 500 V to ≤ 750 V with corner pins >
750 V
– Added ‘class’ information
19. Static latch-up on page 167: Added ‘AEC-Q100/004’ standard
20. Table 86: Latch up results on page 167:
– Removed T
= +25°C, +85°C and +105°C from latch-up conditions
A
– Added AEC-Q100/004 test standard
– Removed dynamic latch-up results
– Changed ‘class’ information
– Removed footnote 1 pertaining to class descriptions and JEDEC standards
21. Table 87: I/O general port pin characteristics on page 168:
– Added footnote
(3)
– Amended footnote
and
(4)
(5)
22. Figure 76: RESET pin protection on page 173: Removed EMC protective circuitry
(device works correctly without these components)
23. Table 92: SPI characteristics on page 175:
– Added footnote
(1)
and
(2)
– Updated max and unit information of tv(MO)
– Updated min values of t
(MO)
h
– Updated min and max values for ‘data output valid’ and ‘data output hold’ times
24. Figure 80: SPI master timing diagram on page 177: Modified figure to reflect changes
made in Table 92: SPI characteristics concerning t
(MO) and th(MO)
v
25. Table 93: 10-bit ADC characteristics on page 178:
– Removed word ‘positive’ from explanation of I
– Updated footnote
(2)
26. Figure 83: Typical A/D converter application on page 179: Changed IL ± 1µA to I
parameter
lkg
lkg
27. Table 94: ADC accuracy with VDD = 5.0V on page 181:
– Made the ‘conditions’ applicable for all parameters
– Updated footnote
(2)
28. Table 97: Thermal characteristics on page 184:
– Amended footnotes
(1)
and
(2)
– Added a value for LQFP44
29. Table 99: Flash option bytes on page 185:
– Changed bits 4 and 3 of option byte 0 to a default value of ‘1’
– Changed the OSCRANGE bits [2:0] of option byte 1 from 111 to 011
– Added footnote 1 concerning package selection
30. Updated Table 100: Option byte 0 description on page 186
31. Updated Table 101: Option byte 1 description on page 186
32. Added Table 102: Package selection (OPT7) on page 187
33. Section 15.1.2: External interrupt missed on page 194: Added section on ‘external
interrupt missed’ bug
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ST7232Axx-Auto Introduction
34. Section 15.1.6: TIMD set simultaneously with OC interrupt on page 197:
– Added section concerning limitation of the 16-bit timer
– Added ‘TBCR1’, ‘TBCSR I’ and ‘TBCSR &’ to the workaround subsection
1.2.2 Minor content differences
1. Removed all references to the SDIP32 and SDIP42 packages (which are unavailable in
automotive) thoughout document
2. Replaced TQFP by LQFP throughout document
3. Table 3: Hardware register map on page 25: Replaced ‘h’ with ‘b’ in the reset status
column for the SCICR1 register
4. System integrity control/status register (SICSR) on page 41: Replaced ‘h’ with ‘b’ in the
reset value cell of the SICSR register
5. Table 43: SPI register map and reset values on page 117: Changed the name of bit 5 in
the SPICSR register from OR to OVR
6. Break character on page 123: SPI replaced by SCI
7. Control register 1 (SCICR1) on page 133: Replaced ‘h’ with ‘b’ in the reset value cell of
the SCICR1 register
8. Changed I
application with an external clock source on page 161 and Table 90: ICCSEL/VPP pin
characteristics on page 174
9. Table 95: 32-pin LQFP mechanical data on page 182 and Table 96: 44-pin LQFP
mechanical data on page 183: Altered ‘inches’ data to four decimal places
10. Section 13.3: Soldering information on page 184:
– Updated environmental information regarding ‘ECOPACK®’ packages
– Replaced ECOPACK
– Updated section on ECOPACK® soldering compatability
11. Table 98: Soldering compatibility (wave and reflow soldering process) on page 184:
Removed footnote on Pb package maximum temperature
12. Updated Table 103: Flash user programmable device types on page 187
13. Added Figure 88: Flash commercial product code structure on page 188
14. Updated Section 14.3: ROM device ordering information and transfer of customer code
on page 188
15. Added Table 104: FASTROM factory coded device types on page 189
16. Added Figure 89: FASTROM commercial product code structure on page 189
17. Added Table 105: ROM factory coded device types on page 190
18. Updated Figure 90: ROM commercial product code structure on page 190
19. Updated ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list on page 191
20. Updated Table 106: STMicroelectronics development tools on page 193
21. Section 14.4: Development tools on page 192:
– Updated Introduction and Programming tools
– Deleted Emulators and In-circuit debugging kit
– Added Evaluation tools and starter kits and Development and debugging tools
22. Section 14.5: ST7 application notes on page 193: Removed list of ST7 application
notes
L
to I
in Table 77: External clock source on page 161, Figure 65: Typical
lkg
TM
with ECOPACK® throughout the document
17/201
Obsolete Product(s) - Obsolete Product(s)
Introduction ST7232Axx-Auto
1.2.3 Editing and formatting differences
1. Reformatted document
2. Converted register and bit decriptions to table format
3. Edited English throughout document
4. Correctly aligned footnotes of tables throughout document
18/201
Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Pin description
2 Pin description
Figure 2. 32-pin LQFP 7x7 package pinout
_2
PE1/RDI
ICCCLK/SCK/PC6
PE0/TDO
ei0
/PC7
AIN15/SS
V
24
23
22
21
20
19
18
17
(HS) PA3
DD
OSC1
OSC2
V
_2
SS
RESET
V
/ICCSEL
PP
PA7 ( H S)
PA6 ( H S)
PA4 ( H S)
V
AREF
V
MCO/AIN8/PF0
Beep/(HS) PF1
OCMP1_A/AIN10/PF4
ICAP1_A/(HS) PF6
EXTCLK_A/(HS) PF7
AIN12/OCMP2_B/PC0
SSA
PD0/AIN0
ei3
PB4 (HS)
PB3
ei2
PB0
PD1/AIN1
32 31 30 29 2827 2625
1
2
3
ei1
4
5
6
7
8
9 10111213141516
AIN14/MOSI/PC5
ICAP2_B/(HS) PC2
ICAP1_B/(HS) PC3
ICCDATA/MISO/PC4
AIN13/OCMP1_B/PC1
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
19/201
Obsolete Product(s) - Obsolete Product(s)
Pin description ST7232Axx-Auto
Figure 3. 44-pin LQFP package pinout
_2
_2
/ICCSEL
SS
RDI/PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
DD
PE0/TDO
V
OSC1
OSC2
44 43 42 41 40 39 38 37 36 35 34
1
2
3
ei2
4
5
ei3
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
ei1
PP
V
PA 6 ( HS )
PA 5 ( HS )
ei0
PA 4 ( HS )
V
33
SS_1
V
32
DD_1
PA3 ( H S )
31
PC7/SS
30
PC6/SCK/ICCCLK
29
PC5/MOSI/AIN14
28
PC4/MISO/ICCDATA
27
PC3 (HS)/ICAP1_B
26
PC2 (HS)/ICAP2_B
25
PC1/OCMP1_B/AIN13
24
PC0/OCMP2_B/AIN12
23
/AIN15
PA 7 ( HS )
V
RESET
SSA
AREF
V
V
AIN5/PD5
MCO/AIN8/PF0
(HS) PF2
Beep/(HS) PF1
ICAP1_A/(HS) PF6
OCMP1_A/AIN10/PF4
DD_0
V
EXTCLK_A/(HS) PF7
SS_0
V
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
For external pin connection guidelines, refer to Section 12: Electrical characteristics on
page 153.
In Table 2: Device pin description below, refer to Section 9: I/O ports on page 62 for more
details on the software configuration of the I/O ports. The RESET
configuration of each pin
is shown in bold. This configuration is valid as long as the device is in reset state. For
external pin connection guidelines refer to Section 12: Electrical characteristics on
page 153.
20/201
Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Pin description
Table 2. Device pin description
Pin
no.
LQFP44
Pin name
LQFP32
Typ e
(1)
Level Port
Input Output
Input
Output
float
(2)
wpu
int
ana
(3)
OD
Main
function
(after
reset)
PP
630PB4 (HS) I/OCTHS X ei3 X X Port B4
7 31 PD0/AIN0 I/O C
8 32 PD1/AIN1 I/O C
(4)
9 -
10 -
11 -
12 -
13 1 V
14 2 V
PD2/AIN2 I/O C
(4)
PD3/AIN3 I/O C
(4)
PD4/AIN4 I/O C
(4)
PD5/AIN5 I/O C
(5)
AREF
(5)
SSA
S Analog reference voltage for ADC
S Analog ground voltage
15 3 PF0/MCO/AIN8 I/O C
16 4 PF1 (HS)/Beep I/O C
(4)
17 -
18 5
PF2 (HS) I/O CTHS X ei1 X X Port F2
PF4/OCMP1_A/
AIN10
I/O C
T
T
T
T
T
T
T
T
T
X X X X X Port D0 ADC analog input 0
X X X X X Port D1 ADC analog input 1
X X X X X Port D2 ADC analog Input 2
X X X X X Port D3 ADC analog Input 3
X X X X X Port D4 ADC analog Input 4
X X X X X Port D5 ADC analog Input 5
Xei1XXXPort F0
HS X ei1 X X Port F1 Beep signal output
XX XX XPort F4
Alternate function
Main clock
out (f
CPU
)
Timer A output
compare 1
ADC analog
input 8
ADC analog
input 10
19 6 PF6 (HS)/ICAP1_A I/O CTHS X X X X Port F6 Timer A input capture 1
20 7
21 - V
22 - V
23 8
24 9
25 10
26 11
27 12
28 13 PC5/MOSI/AIN14 I/O C
29 14 PC6/SCK/ICCCLK I/O C
PF7
(HS)/EXTCLK_A
(5)
DD_0
(5)
SS_0
PC0/OCMP2_B/
AIN12
PC1/OCMP1_B/
AIN13
PC2
(HS)/ICAP2_B
PC3
(HS)/ICAP1_B
PC4/MISO/
ICCDATA
I/O CTHS X X X X Port F7 Timer A external clock source
S Digital main supply voltage
S Digital ground voltage
I/O C
I/O C
I/O C
I/O C
I/O C
T
T
T
T
T
T
T
XX XX XPort C0
XX XX XPort C1
HS X X X X Port C2 Timer B input capture 2
HS X X X X Port C3 Timer B input capture 1
XX XXPort C4
XX XX XPort C5
XX XXPort C6
Timer B output
compare 2
Timer B output
compare 1
SPI master in/
slave out data
SPI master out
/slave in data
SPI serial
clock
ADC analog
input 12
ADC analog
input 13
ICC data
input
ADC analog
input 14
ICC clock
output
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Obsolete Product(s) - Obsolete Product(s)
Pin description ST7232Axx-Auto
Table 2. Device pin description
Pin
no.
Pin name
LQFP44
LQFP32
30 15 PC7/SS/AIN15 I/O C
31 16 PA3 (HS) I/O C
32 - V
33 - V
DD_1
SS_1
(5)
(5)
34 17 PA4 (HS) I/O C
(4)
35 -
PA5 ( H S ) I/ O CTHS X X X X Port A5
36 18 PA6 (HS) I/O C
37 19 PA7 (HS) I/O C
38 20 V
/ICCSEL I
PP
Level Port
Type
Input
T
T
S Digital main supply voltage
S Digital ground voltage
T
T
T
(1)
(continued)
Main
Input Output
ana
(3)
OD
Output
float
(2)
wpu
int
function
(after
reset)
PP
XX XX XPort C7
HS X ei0 X X Port A3
HS X X X X Port A4
HS X T Port A6
HS X T Port A7
Must be tied low. In the Flash
programming mode, this pin acts as the
programming voltage input V
Section 12.9.2 for more details. High
voltage must not be applied to ROM
devices.
Alternate function
SPI slave
select (active
low)
ADC analog
input 15
. See
PP
39 21 RESET I/O C
40 22 V
SS_2
41 23 OSC2
42 24 OSC1
43 25 V
DD_2
(5)
(6)
(6)
(5)
S Digital ground voltage
O Resonator oscillator inverter output
I
S Digital main supply voltage
44 26 PE0/TDO I/O C
127PE1/RDI I/OC
T
T
T
X X X X Port E0 SCI transmit data out
X X X X Port E1 SCI receive data in
Top priority non maskable interrupt.
External clock input or resonator
oscillator inverter input
Caution: Negative current
228PB0 I/OC
(4)
3-
4-
PB1 I/O C
(4)
PB2 I/O C
529PB3 I/OC
1. Legend/abbreviations for Table 2:
Type: I = input, O = output, S = supply
Input level: C
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration inputs: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ports
Port and control configuration outputs: OD = open drain, PP = push-pull
2. ‘eiX’ defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column
(int), then the I/O configuration is pull-up interrupt input; otherwise the configuration is floating interrupt input
= CMOS 0.3VDD/0.7VDD with input trigger
T
T
T
T
T
Xei2 XXPort B0
injection not allowed on this
pin
Xei2 XXPort B1
Xei2 XXPort B2
Xei2XXPort B3
(7)
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Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Pin description
3. ‘T’ defines a true open drain I/O (P-buffer and protection diode to VDD are not implemented). See Section 9: I/O ports on
page 62 and Section 12.8: I/O port pin characteristics for more details
4. Each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The
configuration of these pads must be kept at reset state to avoid added current consumption.
5. It is mandatory to connect all available V
6. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1:
Introduction and Section 12.5: Clock and timing characteristics for more details
7. For details refer to Section 12.8.1: General characteristics on page 168
DD
and V
pins to the supply voltage and all VSS and V
AREF
pins to ground
SSA
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Obsolete Product(s) - Obsolete Product(s)
Register and memory map ST7232Axx-Auto
3 Register and memory map
As shown in <Blue HT>Figure 4, the MCU is capable of addressing 64K bytes of memories
and I/O registers.
The available memory locations consist of 128 bytes of register locations, up to 384 bytes of
RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 256 bytes
for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Caution: Memory locations marked as ‘reserved’ must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 4. Memory map
0000h
007Fh
0080h
047Fh
0480h
E000h
FFDFh
FFE0h
FFFFh
HW registers
Program memory
Interrupt and reset vectors
(see Ta bl e 3)
RAM
(384 bytes)
Reserved
(4K or 8K)
(see Ta bl e 15 )
0080h
00FFh
0100h
01FFh
0200h
027Fh
or 047Fh
Short addressing
RAM (zero page)
256 bytes stack
Reserved
E000h
8 Kbytes
F000h
4 Kbytes
FFFFh
24/201
Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Register and memory map
Table 3. Hardware register map
Address Block Register label Register name Reset status
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h to
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
Por t A
Por t B
Por t C
Por t D
Por t E
Por t F
SPI
ITC
(3)
(3)
(3)
(3)
(3)
PA DR
PADDR
PA OR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDADR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
Port A data register
Port A data direction register
Port A option register
Port B data register
Port B data direction register
Port B option register
Port C data register
Port C data direction register
Port C option register
Port D data register
Port D data direction register
Port D option register
Port E data register
Port E data direction register
Port E option register
Port F data register
Port F data direction register
Port F option register
Reserved area (15 bytes)
SPI data I/O register
SPI control register
SPI control/status register
Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xxh
0xh
00h
FFh
FFh
FFh
FFh
(1)
(4)
(4)
(4)
(4)
(4)
(4)
0028h EICR External interrupt control register 00h R/W
0029h Flash FCSR Flash control/status register 00h R/W
002Ah Watchdog WDGCR Watchdog control register 7Fh R/W
002Bh Reserved area (1 byte)
002Ch
002Dh
002Eh to
0030h
MCC
MCCSR
MCCBCR
Main clock control/status register
Main clock controller: beep control register
Reserved area (3 bytes)
00h
00h
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(3)
R/W
(3)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(2)
25/201
Obsolete Product(s) - Obsolete Product(s)
Register and memory map ST7232Axx-Auto
Table 3. Hardware register map (continued)
00h
00h
xxh
xxh
80h
00h
FFh
xxh
xxh
80h
00h
00h
00h
xxh
xxh
80h
00h
xxh
xxh
80h
00h
xxh
00h
00h
00h
00h
00h
00h
00h
(1)
Remarks
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
Address Block Register label Register name Reset status
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h Reserved area (1 byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h to
006Fh
0070h
0071h
0072h
0073h
007Fh
1. x = undefined
2. R/W = read/write
3. The bits associated with unavailable pins must always keep their reset value
4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents
Timer A
Timer B
SCI
ADC
TAC R2
TAC R1
TAC SR
TA IC 1 H R
TAIC1LR
TAO C1 HR
TAO C1 LR
TAC HR
TAC LR
TAACHR
TA AC L R
TA IC 2 H R
TAIC2LR
TAO C2 HR
TAO C2 LR
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
ADCCSR
ADCDRH
ADCDRL
Timer A control register 2
Timer A control register 1
Timer A control/status register
Timer A input capture 1 high register
Timer A input capture 1 low register
Timer A output compare 1 high register
Timer A output compare 1 low register
Timer A counter high register
Timer A counter low register
Timer A alternate counter high register
Timer A alternate counter low register
Timer A input capture 2 high register
Timer A input capture 2 low register
Timer A output compare 2 high register
Timer A output compare 2 low register
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register
Reserved area (24 bytes)
Control/status register
Data high register
Data low register
Reserved area (13 bytes)
xxxx x0xxb
FCh
FFh
FCh
xxxx x0xxb
FFh
FCh
FFh
FCh
C0h
x000 0000b
(2)
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Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Flash program memory
4 Flash program memory
4.1 Introduction
The ST7 dual voltage high density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external V
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organisation allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2 Main features
● Three Flash programming modes:
– Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased
– ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board
– IAP (in-application programming) In this mode, all sectors except sector 0, can be
programmed or erased without removing the device from the application board
and while the application is running
● ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
● Read-out protection
● Register access security system (RASS) to prevent accidental programming or erasing
supply.
PP
4.3 Structure
The Flash memory is organised in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Ta b l e 4 ). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
sector 0 (F000h-FFFFh).
Table 4. Sectors available in Flash devices
Flash size (bytes) Available sectors
4K Sector 0
8K Sectors 0,1
27/201
Obsolete Product(s) - Obsolete Product(s)
Flash program memory ST7232Axx-Auto
4.3.1 Read-out protection
Read-out protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Read-out protection selection depends on the device type:
● In Flash devices it is enabled and removed through the FMP_R bit in the option byte
● In ROM devices it is enabled by mask option specified in the option list
Figure 5. Memory map and sector addresses of the ST7232X family
4K 10K 24K 48K
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
8K 16K 32K 60K
2Kbytes
4.4 ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
● RESET: device reset
● V
● ICCCLK: ICC output serial clock pin
● ICCDATA: ICC input/output serial data pin
● ICCSEL/V
● OSC1(or OSCIN): main clock input for external source (optional)
● V
: device power supply ground
SS
: programming voltage
PP
: application board power supply (optional, see Figure 6, footnote 3)
DD
8Kbytes 40 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
24 Kbytes
Flash memory size
Sector 2
52 Kbytes
Sector 1
Sector 0
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Obsolete Product(s) - Obsolete Product(s)
ST7232Axx-Auto Flash program memory
Figure 6. Typical ICC interface
Programming tool
ICC connector
ICC cable
(3)
Application
power supply
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to implemented in case another device forces the
signal. Refer to the programming tool documentation for recommended resistor values.
2. During the ICC session, the programming tool must control the RESET
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(push pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application reset
circuit in this case. When using a classical RC network with R > 1K or a reset management IC with open
drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.
C
L2
DD
V
OSC2
(See ‘caution’)
C
L1
OSC1
ST7
975 3
10kΩ
SS
V
ICC connector
1
HE10 connector type
246810
Application reset source
RESET
ICCCLK
ICCSEL/VPP
ICCDATA
pin. This can lead to conflicts
Application board
Application I/O
(2)
(1)
Caution: External clock ICC entry mode is mandatory. Pin 9 must be connected to the OSC1 or
OSCIN pin of the ST7 and OSC2 must be grounded.
4.5 In-circuit programming (ICP)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.
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Flash program memory ST7232Axx-Auto
4.6 In-application programming (IAP)
This mode uses a Bootloader program previously stored in sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored, ...). For example, it is possible
to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash sectors except sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.7 Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash programming
reference manual and to the ST7 ICC protocol reference manual
Flash control/status register (FCSR)
FCSR Reset value: 0000 0000 (00h)
76543210
.
0
R/W
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Table 5. Flash control/status register address and reset value
Address (Hex.)Register label76543210
0029h
FCSR
Reset value00000000
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