ST ST72325S4, ST72325J4, ST72325K4, ST72325J6, ST72325K6 User Manual

...

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS,

LQFP44

10 x 10

LQFP32

7 x 7

LQFP48

7 x 7

LQFP64

10 x 10

SDIP42 600 mil

SDIP32 400 mil

LQFP64

14 x 14

Features

■ Memories

– 16K to 60K dual voltage High Density Flash

(HDFlash) or up to 32K ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash

devices – 512 to 2048 bytes RAM – HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C

■ Clock, reset and supply management

– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability – Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator and bypass for

external clock – PLL for 2x frequency multiplication – Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow – Clock Security System

■ Interrupt management

– Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – Top Level Interrupt (TLI) pin on 64-pin devices – 9/6 external interrupt lines (on 4 vectors)

■ Up to 48 I/O ports

– 48/36/32/24 multifunctional bidirectional I/O

lines – 34/26/22/17 alternate function lines – 16/13/12/10 high sink outputs

■ 5 timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

ST72325xx

5 timers, SPI, SCI, I

– Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one timer, PWM and pulse generator modes

– 8-bit PWM Auto-reload timer with: 2 input cap-

tures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

■ 3 Communication interfaces

– SPI synchronous serial interface – SCI asynchronous serial interface

C multimaster interface

–I

■ 1 Analog peripheral (low current coupling)

– 10-bit ADC with up to 16 robust input ports

■ Instruction set

– 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction

■ Development tools

– Full hardware/software development package – DM (Debug module)

C interface

Table 1. Device summary

Features

Program memory - bytes Flash/ROM 16K Flash/ROM 32K Flash 48K Flash 60K RAM (stack) - bytes 512 (256) 1024(256) 1536 (256) 2048(256) Operating Voltage 3.8V to 5.5V Temp. Range up to -40°C to +125°C

Package

October 2008 Rev 4 1/197

LQFP48(S), LQFP44/SDIP42 (J),

ST72325S4 /

ST72325J4 / ST72325K4

LQFP48(S) , LQFP44/ SDIP42 (J),

LQFP32/DIP32 (K)

ST72325S6 /

ST72325J6 / ST72325K6

LQFP32/DIP32 (K)

ST72325J7

LQFP44 (J)

ST72325R9 /

ST72325AR9 /

ST72325C9 /ST72325J9

LQFP64 14x14(R), LQFP64

10x10(AR), LQFP48(C),

LQFP44 (J)

Table of Contents

1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 43

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

197

2/197

Table of Contents

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . . 61

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.4.6 Summary of Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

197

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12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 145

12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 156

12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 158

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

12.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

12.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 166

12.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

12.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

12.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

12.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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Table of Contents

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 181

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 183

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.4 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.1.1 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 193

15.1.4 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

15.1.5 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

15.1.7 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

15.1.8 Pull-up always active on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

15.1.9 ADC accuracy 16/32K Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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197

ST72325xx

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

CONTROL

PROGRAM

(16K - 60K Bytes1))

RESET

PORT F

PF7:0

TIMER A

BEEP

RAM

(512 - 2048 Bytes1))

PORT C

10-BIT ADC

AREF

SSA

PB7:0

PORT E

PE7:0

(2 bits on C/J/K devices)

SCI

TIMER B

PA7:0

(5 bits on C/J devices)

PORT D

PD7:0

SPI

PC7:0

(8 bits)

WATCHDOG

OSC

LVD

OSC2

MEMORY

MCC/RTC/BEEP

(4 bits on K devices)

(5 bits on C/J devices) (3 bits on K devices)

(6 bits on C/J devices) (2 bits on K devices)

(6 bits on C/J devices) (5 bits on K devices)

PORT A

PORT B

PWM ART

I2C

EVD

AVD

(8 bits on AR devices)

TLI

ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.

DEBUG MODULE

1 DESCRIPTION

The ST72F325 Flash and ST72325 ROM devices are members of the ST7 microcontroller family designed for mid-range applications.

They are derivatives of the ST72321 and ST72324 devices, with enhanced characteristics and robust Clock Security System.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code.

The on-chip peripherals include an A/D converter, a PWM Autoreload timer, 2 general purpose tim-

C bus, SPI interface and an SCI interface.

ers, I For power economy, microcontroller can switch

dynamically into WAIT, SLOW, ACTIVE-HALT or

Figure 1. Device Block Diagram

HALT mode when the application is in idle or stand-by state.

Typical applications are consumer, home, office and industrial products.

The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Main Differences with ST72321:

– LQFP48 and LQFP32 packages – Clock Security System – Internal RC, Readout protection, LVD and PLL

without limitations

– Negative current injection not allowed on I/O port

PB0 (instead of PC6).

– External interrupts have Exit from Active Halt

mode capability.

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ST72325xx

AREF

SSA

DD_3

SS_3

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP2_A / AIN9 / PF3

OCMP1_A / AIN10 / PF4

ICAP2_A / AIN11 / PF5

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

47 46 45 44 43

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ei2

ei3

ei0

ei1

PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3

ARTCLK / (HS) PB4

ARTIC1 / PB5 ARTIC2 / PB6

PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3

(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7

PA1 PA0 PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12 V

SS_0

DD_0

SS_1

DD_1

PA3 (HS) PA2

OSC1

OSC2

TLI

EVD

RESET

/ ICCSEL

PA7 (HS) / SCLI

PA6 (HS) / SDAI

PA5 (HS)

PA4 (HS)

PE3

PE2

PE1 / RDI

PE0 / TDO

(HS) 20mA high sink capability eix associated external interrupt vector

2 PIN DESCRIPTION

Figure 2. 64-Pin LQFP 14x14 and 10x10 Package Pinout

8/197

Figure 3. 48-Pin LQFP 7x7 Device Pinout

44 43 42 41 40 39 38 37

36 35 34

33 32 31 30 29 28 27 26 25

13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

48 47 46 45

AIN4 / PD3

DD_0

PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12

SS_1

SS_0

OSC2

PA7 (HS) / SCLI

PA6 (HS) / SDAI

PA5 (HS)

PA4 (HS)

PE1/ RDI

PE0 / TDO

OSC1

RESET

/ICCSEL

PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B

DD_1

PA3 (HS) PA2 PC7 / SS / AIN15

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN4 / PD4

AIN5 / PD5

PWM1 / PB2 PWM0 / PB3

ARTCLK / (HS) PB4

ARTIC1 / PB5

AIN0 / PD0 AIN1 / PD1 AIN3 / PD2

PE2

(HS) PE4 PWM3 / PB0 PWM2 / PB1

ei2

ei3

ei0

ei1

eix associated external interrupt vector

(HS) 20mA high sink capability

= Pin not connected in ST72325S devices

Legend

Caution: 48-pin ‘C’ devices have unbonded pins that require software initialization. Refer

to Note 4 on page 16 for details on initializing the I/O registers for these devices.

ST72325xx

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ST72325xx

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

DD_0

SS_0

AIN5 / PD5

AREF

SSA

44 43 42 41 40 39 38 37 36 35 34

33 32 31 30 29 28 27 26 25 24 23

12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

ei2

ei3

ei0

ei1

PB3

(HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4

RDI / PE1

PB0

PB1

PB2

PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12

SS_1

DD_1

PA3 (HS) PC7 / SS

/ AIN15

RESET

/ ICCSEL

PA7 (HS) / SCLI

PA6 (HS) / SDAI

PA5 (HS)

PA4 (HS)

PE0 / TDO

OSC1

OSC2

38 37 36 35 34 33 32 31 30 29 28 27

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(HS) PB4

AIN0 / PD0

AIN12 / OCMP2_B / PC0

EXTCLK_A / (HS) PF7

ICAP1_A / (HS) PF6

AIN10 / OCMP1_A / PF4

(HS) PF2

BEEP / (HS) PF1

MCO / AIN8 / PF0

AIN5 / PD5

AIN4 / PD4

AIN3 / PD3

AIN2 / PD2

AIN1 / PD1

SSA

AREF

PB3 PB2

PA4 (HS)

PA5 (HS)

PA6 (HS) / SDAI

PA7 (HS) / SCLI

/ ICCSEL

RESET

VSS_2

PE0 / TDO

PE1 / RDI

PB0

PB1

OSC1 OSC2

ei3

ei0

ei2

ei1

17 18 19

AIN14 / MOSI / PC5

ICCDATA / MISO / PC4

ICAP1_B / (HS) PC3

ICAP2_B/ (HS) PC2

AIN13 / OCMP1_B / PC1

26 25 24 23 22

PC6 / SCK / ICCCLK

PC7 / SS

/ AIN15

PA3 (HS)

DD_1

SS_1

eix associated external interrupt vector

(HS) 20mA high sink capability

Figure 4. 44/42-Pin LQFP Package Pinouts

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Figure 5. 32-Pin LQFP/DIP Package Pinouts

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

ICCCLK / SCK / PC6

AIN15 / SS / PC7

(HS) PA3

AIN13 / OCMP1_B / PC1

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10111213141516

1 2 3 4 5 6 7 8

ei1

ei3

ei0

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

/ ICCSEL PA7 (HS)/SCLI PA6 (HS) / SDAI PA4 (HS)

OSC1 OSC2 V

RESET

PB0 / PWM3

PE1 / RDI

PE0 / TDO

PD1 / AIN1

PD0 / AIN0

PB4 (HS) / ARTCLK

PB3 / PWM0

ei2

28 27 26 25 24 23 22 21 20 19 18 17

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(HS) PB4

AIN0 / PD0

AIN14 / MOSI / PC5

ICCDATA/ MISO / PC4

ICAP1_B / (HS) PC3

ICAP2_B / (HS) PC2

AIN13 / OCMP1_B / PC1

AIN12 / OCMP2_B / PC0

EXTCLK_A / (HS) PF7

BEEP / (HS) PF1

MCO / AIN8 / PF0

SSA

AREF

AIN1 / PD1

ICAP1_A / (HS) PF6

OCMP1_A / AIN10 / PF4

PB3

PB0

PC6 / SCK / ICCCLK

PC7 / SS / AIN15

PA3 (HS)

PA4 (HS)

PA6 (HS) / SDAI

PA7 (HS) / SCLI

/ ICCSEL

OSC2

OSC1

PE0 / TDO

PE1 / RDI

VSS_2 RESET

ei0

ei3

ei2

ei1

eix associated external interrupt vector

(HS) 20mA high sink capability

ST72325xx

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ST72325xx

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 142.

Legend / Abbreviations for Table 2 and Table 3:

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3V

CT= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

– Output: OD = open drain Refer to “I/O PORTS” on page 50 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

= Pin not connected in ST72325S devices

Table 2. LQFP64/48/44 and SDIP42 Device Pin Descriptions

/0.7V

, PP = push-pull

, ana = analog

LQFP64

Pin n°

LQFP48S

LQFP48C

Pin Name

SDIP42

LQFP44

Level Port

Type

Input

Output

float

Input Output

int

ana

wpu

Main

function

(after

reset)

Alternate function

12- - -PE4 (HS) I/OCTHS X XXXPort E4

234-

---PE5 (HS) I/OCTHS X XXXPort E5

---PE6 (HS) I/OCTHS X XXXPort E6

---PE7 (HS) I/OCTHS X XXXPort E7 PWM Output 3

533239PB0/PWM3 I/OC

X ei2 X X Port B0

Caution: Negative cur-

rent injection not allowed on this pin

644340PB1/PWM2 I/OC 755441PB2/PWM1 I/OC 866542PB3/PWM0 I/OC

9 7 7 6 1 PB4 (HS)/ARTCLK I/O C

10 8 - - - PB5 / ARTIC1 I/O C

11 -

12 -

- - - PB6 / ARTIC2 I/O C

---PB7 I/OCTX ei3 X X Port B7

139972PD0/AIN0 I/OC 14 19 10 8 3 PD1/AIN1 I/O C 15 11 11 9 4 PD2/AIN2 I/O C 16 12 12 10 5 PD3/AIN3 I/O C

X ei2 X X Port B1 PWM Output 2 X ei2 X X Port B2 PWM Output 1 X ei2 X X Port B3 PWM Output 0

HS X ei3 X X Port B4

X ei3 X X Port B5

X ei3 X X Port B6

PWM-ART External Clock

PWM-ART Input Capture 1

PWM-ART Input Capture 2

X X X X X Port D0 ADC Analog Input 0 X X X X X Port D1 ADC Analog Input 1 X X X X X Port D2 ADC Analog Input 2 X X X X X Port D3 ADC Analog Input 3

12/197

ST72325xx

Pin n°

Pin Name

Type

LQFP64

LQFP48S

LQFP48C

SDIP42

LQFP44

17 13 13 11 6 PD4/AIN4 I/O C 18 14 14 12 7 PD5/AIN5 I/O C

19 20 -

21 15 15 13 8 V

22 16 16 14 9 V 23----V 24----V

- - - PD6/AIN6 I/O C

- - - PD7/AIN7 I/O C

AREF

SSA

DD_3

SS_3

S Analog Ground Voltage S Digital Main Supply Voltage S Digital Ground Voltage

25 17 17 15 10 PF0/MCO/AIN8 I/O C

26 18 18 16 11 PF1 (HS)/BEEP I/O C 27 19 19 17 12 PF2 (HS) I/O C

28 -

---

29 20 20 18 13

30 -

---

PF3/OCMP2_A/ AIN9

PF4/OCMP1_A/ AIN10

PF5/ICAP2_A/ AIN11

I/O C

31 21 21 19 14 PF6 (HS)/ICAP1_A I/O C

32 22 22 20 15

33 23 23 21 - V 34 24 24 22 - V

35 25 25 23 16

36 26 26 24 17

PF7 (HS)/ EXTCLK_A

DD_0

SS_0

PC0/OCMP2_B/ AIN12

PC1/OCMP1_B/ AIN13

I/O C

S Digital Main Supply Voltage S Digital Ground Voltage

I/O C

37 27 27 25 18 PC2 (HS)/ICAP2_B I/O C 38 28 28 26 19 PC3 (HS)/ICAP1_B I/O C

39 29 29 27 20

PC4/MISO/ICCDATA

I/O C

40 30 30 28 21 PC5/MOSI/AIN14 I/O C

41 31 31 29 22 PC6/SCK/ICCCLK I/O C

Level Port

Input Output

Input

Output

X X X X X Port D4 ADC Analog Input 4 X X X X X Port D5 ADC Analog Input 5 X X X X X Port D6 ADC Analog Input 6 X X X X X Port D7 ADC Analog Input 7

float

int

wpu

ana

Main

function

(after

reset)

Alternate function

Analog Reference Voltage for ADC

/2)

ADC Analog Input 8

ADC Analog Input 9

ADC Analog Input 10

ADC Analog Input 11

ADC Analog Input 12

ADC Analog Input 13

ICC Data Input

ADC Analog Input 14

ICC Clock Output

X ei1 X X X Port F0

HS X ei1 X X Port F1 Beep signal output HS X ei1 X X Port F2

Main clock out (f

OSC

Timer A

X XXXXPort F3

Output Compare 2

Timer A

X XXXXPort F4

Output Compare 1

Timer A In-

X XXXXPort F5

put Capture 2

HS X X X X Port F6 Timer A Input Capture 1

HS X XXXPort F7

Timer A External Clock Source

Timer B

X XXXXPort C0

Output Compare 2

Timer B

X XXXXPort C1

Output Compare 1

HS X X X X Port C2 Timer B Input Capture 2

HS X X X X Port C3 Timer B Input Capture 1

SPI Master

X XXXPort C4

In / Slave Out Data

SPI Master

X XXXXPort C5

Out / Slave In Data

X XXXPort C6

SPI Serial Clock

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ST72325xx

LQFP64

Pin n°

LQFP48S

LQFP48C

Pin Name

SDIP42

LQFP44

Level Port

Type

Input

Output

float

Input Output

int

ana

wpu

Main

function

(after

reset)

Alternate function

SPI Slave

42 32 32 30 23 PC7/SS/AIN15 I/O C

X XXXXPort C7

Select (active low)

43 44 45 33 - - - PA2 I/O C 46 34 34 31 24 PA3 (HS) I/O C 47 35 35 32 25 V 48 36 36 33 26 V 49 37 37 34 27 PA4 (HS) I/O C 50 38 38 35 28 PA5 (HS) I/O C 51 39 39 36 29 PA6 (HS)/SDAI I/O C 52 40 40 37 30 PA7 (HS)/SCLI I/O CTHS X TPort A7 I

---PA0 I/OCTX ei0 X X Port A0

---PA1 I/OCTX ei0 X X Port A1

X ei0 X X Port A2

HS X ei0 X X Port A3

HS X XXXPort A4 HS X XXXPort A5 HS X TPort A6 I

DD_1

SS_1

S Digital Main Supply Voltage S Digital Ground Voltage

C Data

C Clock

Must be tied low. In flash programming mode, this pin acts as the

53 41 41 38 31 VPP/ ICCSEL I

programming voltage input V See Section 12.9.2 for more details. High voltage must not be applied to ROM devices

54 42 42 39 32 RESET

I/O C

Top priority non maskable inter-

rupt. 55 - - - - EVD External voltage detector 56----TLI IC 57 43 43 40 33 V

58 44 44 41 34 OSC2

59 45 45 42 35 OSC1

60 46 46 43 36 V

SS_2

DD_2

61 47 47 44 37 PE0/TDO I/O C 62 48 48 1 38 PE1/RDI I/O C 63 1 - - - PE2 I/O C

64 -

---PE3 I/OCTX XXXPort E3

S Digital Ground Voltage

I/O

S Digital Main Supply Voltage

X Top level interrupt input pin

Resonator oscillator inverter out-

put

External clock input or Resonator

oscillator inverter input

X X X X Port E0 SCI Transmit Data Out X X X X Port E1 SCI Receive Data In X XX

4)X4)

Port E2

ADC Analog Input 15

14/197

Table 3. LQFP32/DIP32 Device Pin Description

ST72325xx

Pin n°

Pin Name

DIP32

LQFP32

14V 25V

AREF

SSA

3 6 PF0/MCO/AIN8 I/O C

4 7 PF1 (HS)/BEEP I/O C

PF4/OCMP1_A/ AIN10

6 9 PF6 (HS)/ICAP1_A I/O C

710

811

912

PF7 (HS)/ EXTCLK_A

PC0/OCMP2_B/ AIN12

PC1/OCMP1_B/

AIN13 10 13 PC2 (HS)/ICAP2_B I/O C 11 14 PC3 (HS)/ICAP1_B I/O C

12 15

PC4/MISO/ICCDA-

13 16 PC5/MOSI/AIN14 I/O C

14 17 PC6/SCK/ICCCLK I/O C

15 18 PC7/SS

/AIN15 I/O C

16 19 PA3 (HS) I/O C 17 20 PA4 (HS) I/O C 18 21 PA6 (HS)/SDAI I/O C 19 22 PA7 (HS)/SCLI I/O CTHS X TPort A7 I

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

function

(after

reset)

Main

Alternate function

I Analog Reference Voltage for ADC

S Analog Ground Voltage

Main clock out

/2)

OSC

Timer A Output Compare 1

Timer B Output Compare 2

Timer B Output Compare 1

SPI Master In / Slave Out Data

SPI Master Out / Slave In Data

SPI Slave Select (active low)

C Data

C Clock

I/O C

X ei1 X X X Port F0

HS X ei1 X X Port F1 Beep signal output

X XXXXPort F4

HS X X X X Port F6 Timer A Input Capture 1

HS X X X X Port F7 Timer A External Clock Source

X XXXXPort C0

X XXXXPort C1

HS X X X X Port C2 Timer B Input Capture 2 HS X X X X Port C3 Timer B Input Capture 1

X XXXPort C4

X XXXXPort C5

X X X X Port C6 SPI Serial Clock

X XXXXPort C7

HS X ei0 X X Port A3 HS X XXXPort A4 HS X TPort A6 I

Must be tied low. In flash programming mode, this pin acts as the programming

20 23 VPP/ ICCSEL I

voltage input VPP. See Section 12.9.2 for more details. High voltage must not be ap-

plied to ROM devices 21 24 RESET 22 25 V

SS_2

23 26 OSC2

24 27 OSC1

25 28 V

DD_2

I/O C

S Digital Ground Voltage

I/O Resonator oscillator inverter output

S Digital Main Supply Voltage 26 29 PE0/TDO I/O C 27 30 PE1/RDI I/O C

X X X X Port E0 SCI Transmit Data Out X X X X Port E1 SCI Receive Data In

Top priority non maskable interrupt.

External clock input or Resonator oscillator inverter input

ADC Analog Input 8

ADC Analog Input 10

ADC Analog Input 12

ADC Analog Input 13

ICC Data Input

ADC Analog Input 14

ICC Clock Output

ADC Analog Input 15

15/197

ST72325xx

Pin n°

Pin Name

DIP32

LQFP32

28 31 PB0/PWM3 I/O C

29 32 PB3/PWM0 I/O C 30 1 PB4 (HS)/ARTCLK I/O C 31 2 PD0/AIN0 I/O C 32 3 PD1/AIN1 I/O C

Level Port

Type

Input

Output

float

X ei2 X X Port B0

X ei2 X X Port B3 PWM Output 0

HS X ei3 X X Port B4 PWM-ART External Clock

X X X X X Port D0 ADC Analog Input 0 X X X X X Port D1 ADC Analog Input 1

Input Output

wpu

int

ana

function

(after

reset)

Main

Alternate function

PWM Output 3 Caution: Negative current injec-

tion not allowed on this pin

Notes for Table 2 and Table 3:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V are not implemented). See See “I/O PORTS” on page 50. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 DESCRIPTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.

4. On the chip, each I/O port may have up to 8 pads: – In all devices except 48-pin ST72325C, pads that are not bonded to external pins are forced by hardware

in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

– In 48-pin ST72325C devices, unbonded pads PA0, PA1, PB6, PB7, PD6, PD7, PE3, PE5, PE6, PE7,

PF3 and PF5) are in input floating configuration after reset. To avoid added current consumption, the application must force these ports in input pull-up state by writing to the OR and DDR registers after reset. This initialization is not necessary in 48-pin ST72325S devices.

5. Pull-up always activated on PE2 see limitation Section 15.1.8.

6. It is mandatory to connect all available V pins to ground.

and V

pins to the supply voltage and all VSS and V

REF

SSA

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3 REGISTER & MEMORY MAP

0000h

RAM

Program Memory

(60,48, 32 or 16K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 4)

1000h

FFDFh FFE0h

FFFFh

(see Table 9)

0880h

Reserved

087Fh

Short Addressing RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

0100h

01FFh

027Fh

0080h

0200h

00FFh

32 KBytes

8000h

FFFFh

(2048, 1536, 1024,

or 047Fh

16 KBytes

C000h

or 512 Bytes)

60 KBytes

48 KBytes

1000h

4000h

or 087Fh

or 067Fh

ST72325xx

As shown in Figure 6, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 6. Memory Map

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

4 FLASH PROGRAM MEMORY

4 Kbytes

2Kbytes

SECTOR 1 SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K

FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8Kbytes 40 Kbytes

52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

ST72325xx

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V

supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ Three Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be programmed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be programmed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 5). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 7). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 5. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0 8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 7. Memory Map and Sector Address

21/197

ST72325xx

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10kΩ

ICCSEL/VPP

ST7

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See Note 4)

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 8). These pins are:

– RESET –V

: device reset

: device power supply ground

Figure 8. Typical ICC Interface

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V

: programming voltage

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

: application board power supply (option-

–V

al, see Figure 8, Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET flicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-

22/197

pin. This can lead to con-

agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

FLASH PROGRAM MEMORY (Cont’d)

ST72325xx

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 8). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 0000 0000 (00h)

00000000

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Figure 9. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

0029h

Label

FCSR

Reset Value00000000

76543210

23/197

ST72325xx

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 10. CPU Registers

5.3 CPU REGISTERS

The six CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

24/197

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

11I1HI0NZ

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re-

sult 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

instructions. Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

ST72325xx

25/197

ST72325xx

PCH PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCL

PCH

PCH PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh Stack Lower Address =

0100h

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write Reset Value: 01 FFh

15 8

00000001

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 2).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack

tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 2.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

higher address.

Figure 11. Stack Manipulation Example

26/197

6 SUPPLY, RESET AND CLOCK MANAGEMENT

PLL OPTION BIT

PLL x 2

OSC2

/ 2

OSC

LOW VOLTAGE

DETECTOR

(LVD)

OSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

EVD

RESET SEQUENCE

MANAGER

(RSM)

CLOCK

FILTER

SAFE

OSC

CLOCK SECURITY SYSTEM

(CSS)

OSC2

MAIN CLOCK

CSS Interrupt Request

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD

AVD AVD

LVD

CSS

WDG

OSC

OSC2

(option)

CPU

ST72325xx

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 13.

For more details, refer to dedicated parametric section.

Main features

■ Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators – 1 Internal RC oscillator

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) – Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply

– Clock Security System (CSS) with Clock Filter

and Backup Safe Oscillator (enabled by option byte)

Figure 13. Clock, Reset and Supply Block Diagram

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an f

OSC2

of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2 = fOSC

/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 154.

Figure 12. PLL Block Diagram

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ST72325xx

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

OSC1 OSC2

ST7

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 6. Refer to the electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 14.1 on page 181 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has

the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 6. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator

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6.3 RESET SEQUENCE MANAGER (RSM)

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

WATCHDOG RESET LVD RESET

INTERNAL RESET

PULSE

GENERATOR

Filter

ST72325xx

6.3.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 15:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases

as shown in Figure 14:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

option byte)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 14.1 on page 181).

The RESET vector fetch phase duration is 2 clock cycles.

Figure 14. RESET Sequence Phases

Caution: When the ST7 is unprogrammed or fully

erased, the Flash is blank and the RESET vector is not programmed.

For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.

6.3.2 Asynchronous External RESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See

“CONTROL PIN CHARACTERISTICS” on page 162 for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

Figure 15. Reset Block Diagram

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ST72325xx

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

w(RSTL)out

RUN

h(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

w(RSTL)out

RUN RUN RUN

RESET

RESET SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 T

CPU

)

VECTOR FETCH

w(RSTL)out

PHASE

ACTIVE PHASE

DELAY

RESET SEQUENCE MANAGER (Cont’d) The RESET

plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

If the external RESET t

w(RSTL)out

signal on the RESET wise the delay will not be applied (see long ext. Reset in Figure 16). Starting from the external RESET pulse recognition, the device RESET as an output that is pulled low during at least t

w(RSTL)out

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V level specified for the selected f (see “OPERATING CONDITIONS” on page 144)

Figure 16. RESET Sequences

pin is an asynchronous signal which

pulse is shorter than

(see short ext. Reset in Figure 16), the

pin may be stretched. Other-

pin acts

is over the minimum

frequency.

OSC

A proper reset signal for a slow rising V

supply

can generally be provided by an external RC network connected to the RESET

pin.

6.3.4 Internal Low Voltage Detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 16.

The LVD filters spikes on V

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is pulled

w(RSTL)out

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