ST ST72324LJ6, ST72324LK6, ST72324LJ4, ST72324LK4, ST72324LS4 User Manual

...

3V range 8-bit MCU with 8 to 32K Flash/ROM,

10-bit ADC, 4 timers, SPI, SCI interface

Features

■ Memories

– 8 to 32K dual voltage High Density Flash (HD-

Flash) or ROM with read-out protection capability. In-Application Programming and In-

Circuit Programming for HDFlash devices – 384 to 1K bytes RAM – HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C

■ Clock, Reset And Supply Management

– Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator, and bypass for

external clock – PLL for 2x frequency multiplication – Four power saving modes: Halt, Active-Halt,

Wait and Slow

■ Interrupt Management

– Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 9/6 external interrupt lines (on 4 vectors)

■ Up to 32 I/O Ports

– 32/24 multifunctional bidirectional I/O lines – 22/17 alternate function lines – 12/10 high sink outputs

■ 4 Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities – Configurable watchdog timer – 16-bit Timer A with: 1 input capture, 1 output

compare, external clock input, PWM and

pulse generator modes – 16-bit Timer B with: 2 input captures, 2 output

compares, PWM and pulse generator modes

ST72324Lxx

LQFP32

LQFP44

10 x 10

LQFP48

7 x 7

■ 2 Communication Interfaces

– SPI synchronous serial interface – SCI asynchronous serial interface

■ 1 Analog Peripheral

– 10-bit ADC with up to 12 input ports

■ Instruction Set

– 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction

■ Development Tools

– Full hardware/software development package – In-Circuit Testing capability

7 x 7

SDIP32 400 mil

Table 1. Device Summary

Features

Program memory bytes

RAM (stack) - bytes 1024 (256) 512 (256) 384 (256) Voltage Range 2.85 to 3.6V Temp. Range up to -40°C to +85°C Packages LQFP44 10x10 (J), LQFP48 7x7 (S), SDIP32, LQFP32 7x7 (K)

ST72324LJ6 ST72324LK6

Flash 32K Flash/ROM 16K Flash/ROM 8K

ST72324LJ4 ST72324LK4 ST72324LS4

ST72324LJ2 ST72324LK2 ST72324LS2

Rev. 5

September 2007 1/154

Table of Contents

1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 33

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 50

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.5.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

154

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Table of Contents

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 121

12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 123

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 130

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 140

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 142

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.3.4 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1.1 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1.2 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1.4 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1.5 ADC Conversion Spurious Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1.6 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

15.1.7 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

15.2 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

15.2.1 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

15.3 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15.3.1 Timer A Restrictions in Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15.3.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15.3.3 39-Pulse ICC Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

154

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ST72324Lxx

1 DESCRIPTION

The ST72F324L and ST72324BL devices are members of the ST7 microcontroller family de signed for mid-range applications running at 3.3V. Different package options offer up to 32 I/O pins. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc tion set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers,

Figure 1. Device Block Diagram

8-BIT CORE

ALU

RESET

OSC1 OSC2

PF7:6,4,2:0

(6 bits on J and S devices) (5 bits on K devices)

PE1:0

(2 bits)

(6 bits on J and S devices) (2 bits on K devices)

PD5:0

AREF

SSA

CONTROL

OSC

MCC/RTC/BEEP

PORT F

TIMER A

BEEP

PORT E

SCI

PORT D

10-BIT ADC

enabling the design of highly efficient and compact application code.

The on-chip peripherals include an A/D converter, 2 general purpose timers, an SPI interface and an SCI interface.

For power economy, microcontroller can switch dynamically into WAIT, SLOW, ACTIVE-HALT or HALT mode when the application is in idle or stand-by state.

Typical applications are consumer, home, office and industrial products.

PROGRAM

MEMORY

(8K - 32K Bytes)

RAM

(384 - 2048 Bytes)

WATCHDOG

ADDRESS AND DATA BUS

PORT A

PORT B

PORT C

TIMER B

SPI

PA7:3 (5 bits on J and S devices) (4 bits on K devices)

PB4:0

(5 bits on J and S devices) (3 bits on K devices)

PC7:0

(8 bits)

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2 PIN DESCRIPTION

Figure 2. 48-Pin LQFP 7x7 Device Pinout

ST72324Lxx

AIN0 / PD0 AIN1 / PD1 AIN3 / PD2 AIN4 / PD3

Legend

NC = Not Connected (not bonded)

NC PB0 PB1 PB2

PB3

(HS) PB4

PE1/ RDI

PE0 / TDO

48 47 46 45

/ICCSEL

OSC2

OSC1

RESET

44 43 42 41 40 39 38 37

1 2 3 4

ei2

5 6

ei3

7 8 9 10 11

ei1

13 14 15 16 17 18 19 20 21 22

SSA

AREF

AIN4 / PD4

AIN5 / PD5

(HS) PF2

BEEP / (HS) PF1

MCO / AIN8 / PF0

OCMP1_A / AIN10 / PF4

PA7 (HS)

ICAP1_A / (HS) PF6

PA6 (HS)

PA5 (HS)

PA4 (HS)

SS_1

DD_1

PA3 (HS)

PC7 / SS / AIN15

ei0

DD_0

PC6 / SCK / ICCCLK

31 30

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

SS_0

EXTCLK_A / (HS) PF7

(HS) 20mA high sink capability eix associated external interrupt vector

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ST72324Lxx

Figure 3. 44-Pin LQFP Package Pinout

RDI / PE1

PB0 PB1

PB2 PB3

(HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4

PE0 / TDO

OSC1

OSC2

44 43 42 41 40 39 38 37 36 35 34

_2 V

/ ICCSEL

RESET

PA7 (HS)

PA6 (HS)

2 3

ei2

ei0

ei3

6 7 8 9 10 11

12 13 14 15 16 17 18 19 20 21 22

AIN5 / PD5

ei1

SSA

AREF

(HS) PF2

BEEP / (HS) PF1

MCO / AIN8 / PF0

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

OCMP1_A / AIN10 / PF4

PA5 (HS)

PA4 (HS)

SS_1

DD_1

PA3 (HS)

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

SS_0

DD_0

eix associated external interrupt vector

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PIN DESCRIPTION (Cont’d)

Figure 4. 32-Pin SDIP Package Pinout

ST72324Lxx

(HS) PB4

AIN0 / PD0 AIN1 / PD1

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

ICCDATA/ MISO / PC4

AIN14 / MOSI / PC5

Figure 5. 32-Pin LQFP 7x7 Package Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ei3

ei1

ei0

ei2

PB3

PB0

PE1 / RDI

PE0 / TDO

VDD_2

OSC1

OSC2

25 24 23 22 21 20 19 18 17

RESET

PA7 (HS) PA6 (HS)

PA4 (HS) PA3 (HS) PC7 / SS / AIN15

PC6 / SCK / ICCCLK

/ ICCSEL

(HS) 8mA high sink capability eix associated external interrupt vector

AREF

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

SSA

PB0

PD1 / AIN1

PD0 / AIN0

PB4 (HS)

32 31 30 29 28 27 26 25

ei3

2 3

ei1

4 5 6 7 8

9 10111213141516

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

AIN13 / OCMP1_B / PC1

PB3

ei2

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

PE1 / RDI

ICCCLK / SCK / PC6

PE0 / TDO

ei0

AIN15 / SS / PC7

24 23 22 21 20 19 18 17

(HS) PA3

OSC1 OSC2 VSS_2 RESET V

/ ICCSEL

PA7 (HS) PA6 (HS) PA4 (HS)

(HS) 8mA high sink capability eix associated external interrupt vector

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ST72324Lxx

PIN DESCRIPTION (Cont’d)

For more details, refer to “ELECTRICAL CHARACTERISTICS” on page 110

Legend / Abbreviations for Table 2:

Type: I = input, O = output, S = supply In/Output level: C = CMOS

CT= CMOS with input trigger

Output level: HS = high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt – Output: OD = open drain

, PP = push-pull Refer to “I/O PORTS” on page 40 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

Table 2. Device Pin Description

, ana = analog ports

Pin n°

LQFP48

LQFP44

SDIP32

LQFP32

Pin Name

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

function

(after

reset)

Main

Alternate Function

7 6 30 1 PB4 (HS) I/O CTHS X ei3 X X Port B4

9 7 31 2 PD0/AIN0 I/O C 10 8 32 3 PD1/AIN1 I/O C 11 9 PD2/AIN2 I/O C 12 10 PD3/AIN3 I/O C 13 11 PD4/AIN4 I/O C 14 12 PD5/AIN5 I/O C 15 13 1 4 V 16 14 2 5 V

AREF

SSA

S Analog Reference Voltage for ADC S Analog Ground Voltage

17 15 3 6 PF0/MCO/AIN8 I/O C

X X X X X Port D0 ADC Analog Input 0 X X X X X Port D1 ADC Analog Input 1 X X X X X Port D2 ADC Analog Input 2 X X X X X Port D3 ADC Analog Input 3 X X X X X Port D4 ADC Analog Input 4 X X X X X Port D5 ADC Analog Input 5

X ei1 X X X Port F0

Main clock out (f

OSC

ADC Analog

/2)

Input 8 18 16 4 7 PF1 (HS)/BEEP I/O CTHS X ei1 X X Port F1 Beep signal output 19 17 PF2 (HS) I/O CTHS X ei1 X X Port F2

Timer A Output Compare 1

ADC Analog

Input 10

20 18 5 8

PF4/OCMP1_A/ AIN10

I/O C

X X X X X Port F4

21 19 6 9 PF6 (HS)/ICAP1_A I/O CTHS X X X X Port F6 Timer A Input Capture 1

22 20 7 10

23 21 V 24 22 V

25 23 8 11

26 24 9 12

PF7 (HS)/ EXTCLK_A

DD_0

SS_0

PC0/OCMP2_B/ AIN12

PC1/OCMP1_B/ AIN13

I/O CTHS X X X X Port F7

S Digital Main Supply Voltage S Digital Ground Voltage

I/O C

X X X X X Port C0

X X X X X Port C1

Timer A External Clock Source

Timer B Output Compare 2

Timer B Output Compare 1

ADC Analog

Input 12

ADC Analog

Input 13

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ST72324Lxx

Pin n°

LQFP48

LQFP44

SDIP32

LQFP32

Pin Name

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

function

(after

reset)

Main

Alternate Function

27 25 10 13 PC2 (HS)/ICAP2_B I/O CTHS X X X X Port C2 Timer B Input Capture 2 28 26 11 14 PC3 (HS)/ICAP1_B I/O CTHS X X X X Port C3 Timer B Input Capture 1

29 27 12 15

PC4/MISO/ICCDATA

I/O C

30 28 13 16 PC5/MOSI/AIN14 I/O C

31 29 14 17 PC6/SCK/ICCCLK I/O C

32 30 15 18 PC7/SS/AIN15 I/O C

X X X X Port C4

X X X X X Port C5

X X X X Port C6

X X X X X Port C7

SPI Master In / Slave Out Data

SPI Master Out / Slave In Data

SPI Serial Clock

SPI Slave Select (ac tive low)

ICC Data In-

put

ADC Analog

Input 14

ICC Clock

Output

ADC Analog

Input 15

34 31 16 19 PA3 (HS) I/O CTHS X ei0 X X Port A3 35 32 V 36 33 V

DD_1

SS_1

S Digital Main Supply Voltage S Digital Ground Voltage

37 34 17 20 PA4 (HS) I/O CTHS X X X X Port A4 38 35 PA5 (HS) I/O CTHS X X X X Port A5 39 36 18 21 PA6 (HS) I/O CTHS X T Port A6 40 37 19 22 PA7 (HS) I/O CTHS X T Port A7

Must be tied low. In the flash programming mode, this pin acts as the

41 38 20 23 V

/ICCSEL I

programming voltage input V

Section 12.9.2 for more details. High

. See

voltage must not be applied to ROM

devices. 42 39 21 24 RESET I/O C 43 40 22 25 V

SS_2

S Digital Ground Voltage

Top priority non maskable interrupt.

44 41 23 26 OSC2 O Resonator oscillator inverter output

45 42 24 27 OSC1 I

46 43 25 28 V

DD_2

S Digital Main Supply Voltage 47 44 26 29 PE0/TDO I/O C 48 1 27 30 PE1/RDI I/O C

3 2 28 31 PB0 I/O C 4 3 PB1 I/O C 5 4 PB2 I/O C 6 5 29 32 PB3 I/O C

X X X X Port E0 SCI Transmit Data Out X X X X Port E1 SCI Receive Data In X ei2 X X Port B0 X ei2 X X Port B1 X ei2 X X Port B2 X ei2 X X Port B3

External clock input or Resonator oscillator inverter input

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V

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ST72324Lxx

are not implemented). See See “I/O PORTS” on page 40. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 2 PIN DESCRIPTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.

4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

5. It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground.

12/154

3 REGISTER & MEMORY MAP

ST72324Lxx

As shown in Figure 6, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of RAM and up to 32 Kbytes of user program memo

ry. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

Figure 6. Memory Map

0000h

007Fh 0080h

087Fh 0880h

7FFFh 8000h

FFDFh FFE0h

FFFFh

HW Registers

(see Table 3)

RAM

(1024,

512 or 384 Bytes)

Reserved

Program Memory (32K, 16K or 8K)

Interrupt & Reset Vectors

(see Table 9)

0080h

00FFh

0100h

01FFh

0200h

027Fh

or 047Fh

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

Short Addressing RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

8000h

C000h

E000h

FFFFh

32 KBytes

16 KBytes

8 Kbytes

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ST72324Lxx

Table 3. Hardware Register Map

Address Block

0000h 0001h

Port A

0002h

0003h 0004h

Port B

0005h

0006h 0007h

Port C

0008h

0009h 000Ah

Port D

000Bh

000Ch 000Dh

Port E

000Eh

000Fh 0010h

Port F

0011h

0012h

0020h

Label

PADR PADDR PAOR

PBDR PBDDR PBOR

PCDR PCDDR PCOR

PDADR PDDDR PDOR

PEDR PEDDR PEOR

PFDR PFDDR PFOR

Port A Data Register Port A Data Direction Register Port A Option Register

Port B Data Register Port B Data Direction Register Port B Option Register

Port C Data Register Port C Data Direction Register Port C Option Register

Port D Data Register Port D Data Direction Register Port D Option Register

Port E Data Register Port E Data Direction Register Port E Option Register

Port F Data Register Port F Data Direction Register Port F Option Register

Reset

Status

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

Remarks

R/W R/W R/W

R/W

R/W R/W R/W

Reserved Area (15 Bytes)

0021h 0022h 0023h

0024h 0025h 0026h 0027h

SPI

ITC

SPIDR SPICR SPICSR

ISPR0 ISPR1 ISPR2 ISPR3

SPI Data I/O Register SPI Control Register SPI Control/Status Register

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3

xxh 0xh 00h

FFh FFh FFh FFh

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh Reserved Area (1 Byte)

002Ch 002Dh

MCC

MCCSR MCCBCR

Main Clock Control / Status Register Main Clock Controller: Beep Control Register

00h 00h

002Eh

Reserved Area (3 Bytes)

0030h

14/154

R/W R/W R/W

R/W R/W R/W R/W

R/W R/W

ST72324Lxx

Address Block

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h

TIMER A 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

Label

TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

0040h Reserved Area (1 Byte)

0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

TIMER B

TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

3)4)

Reset

Status

00h 00h

xxxx x0xxb

xxh xxh 80h

00h FFh FCh FFh

FCh

xxh

80h

00h

xxxx x0xxb

xxh

80h

00h FFh FCh FFh FCh

xxh

80h

00h

Remarks

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h

0058h

006Fh

0070h 0071h 0072h

0073h 007Fh

SCI

ADC

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR

SCIETPR

ADCCSR ADCDRH ADCDRL

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register

Reserved Area (24 Bytes)

Control/Status Register Data High Register Data Low Register

Reserved Area (13 Bytes)

C0h

xxh

00h

x000 0000h

00h

---

00h

Read Only R/W R/W R/W R/W R/W

R/W

R/W Read Only Read Only

15/154

ST72324Lxx

Legend: x=undefined, R/W=read/write Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. The Timer A Input Capture 2 pin is not available (not bonded). – In Flash devices:

The TAIC2HR and TAIC2LR registers are not present. Bit 4 of the TACSR register (ICF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used.

4. The Timer A Output Compare 2 pin is not available (not bonded). – In ROM devices:

The TAOC2HR and TAOC2LR Registers can be used in PWM mode or for timebase generation.

– In Flash devices:

The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values. Bit 3 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used.

Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in the ST72F324L but are present in the emulator. For compatibility with the emulator, it is recommended to per form a dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.

16/154

4 FLASH PROGRAM MEMORY

ST72324Lxx

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individu

al sectors and programmed on a Byte-by-Byte basis using an external VPP supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ Three Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro

grammed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro

grammed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro

grammed or erased without removing the device from the application board and while the application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see

Table 4). Each of these sectors can

be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes

Figure 7). They are mapped in the upper part

(see of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 4. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0 8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content ex

traction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcon

troller.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 7. Memory Map and Sector Address

4K 10K 24K 48K

1000h 3FFFh

7FFFh

9FFFh

BFFFh

D7FFh

DFFFh

EFFFh

FFFFh

8K 16K 32K 60K

2Kbytes

8Kbytes 40 Kbytes

16 Kbytes 4 Kbytes 4 Kbytes

24 Kbytes

FLASH MEMORY SIZE

SECTOR 2

52 Kbytes

SECTOR 1 SECTOR 0

17/154

ST72324Lxx

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 5 and up to 6 pins to be connected to the programming tool (see

Figure 8).

These pins are:

– RESET: device reset –VSS: device power supply ground

Figure 8. Typical ICC Interface

PROGRAMMING TOOL

APPLICATION POWER SUPPLY

(See Note 3)

OSC2

(See Note 4)

OSC1

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another de vice forces the signal. Refer to the Programming Tool documentation for recommended resistor val ues.

2. During the ICC session, the programming tool must control the flicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the appli cation RESET circuit in this case. When using a classical RC network with R>1K or a reset man

RESET pin. This can lead to con-

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/VPP: programming voltage – OSC1(or OSCIN): main clock input for exter-

nal source

–VDD: application board power supply (option-

al, see Figure 8, Note 3)

ICC CONNECTOR

975 3

10kΩ

ICCSEL/VPP

ICC Cable

RESET

ICCCLK

HE10 CONNECTOR TYPE

246810

ICCDATA

APPLICATION BOARD

ICC CONNECTOR

APPLICATION RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin

must be connected when using most ST Program ming Tools (it is used to monitor the application

power supply). Please refer to the Programming Tool manual.

4. External clock ICC entry mode is mandatory in this device. Pin 9 must be connected to the OSC1 or OSCIN pin of the ST7 and OSC2 must be grounded.

18/154

FLASH PROGRAM MEMORY (Cont’d)

ST72324Lxx

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool us

ing 36-pulse mode. Depending on the ICP code downloaded in RAM,

Flash memory programming can be fully custom

ized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the spe

cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap

plication board (see Figure 8). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us

er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase pro tected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Refer-

ence Manual.

4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read / Write Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 0 0

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Table 5. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

0029h

Label

FCSR

Reset Value 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

19/154

ST72324Lxx

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 9. CPU Registers

5.3 CPU REGISTERS

The six CPU registers shown in Figure 9 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the fol lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

RESET VALUE = XXh

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

1C1I1HI0NZ

1X11X1XX

PCL

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

20/154

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

7 0

1 1 I1 H I0 N Z

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in structions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re sult 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

ST72324Lxx

Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions. Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri ority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

21/154

ST72324Lxx

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write Reset Value: 01 FFh

15 8

0 0 0 0 0 0 0 1

7 0

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see

Figure 10).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruc

tion (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 10. Stack Manipulation Example

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD in

struction. Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with

out indicating the stack overflow. The previously stored information is then overwritten and there

fore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc

tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 10.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

RET

or RSP

@ 0100h

@ 01FFh

X PCH PCL

PCH PCL

Stack Higher Address = 01FFh Stack Lower Address =

PCH PCL

0100h

A X

PCH

PCL

PCH

PCL

A X

PCH

PCL

PCH

PCL

PCH PCL

22/154

6 SUPPLY, RESET AND CLOCK MANAGEMENT

ST72324Lxx

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re

ducing the number of external components. An overview is shown in

Figure 11.

For more details, refer to dedicated parametric section.

Main features

■ Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators – 1 Internal RC oscillator

Figure 11. Clock, Reset and Supply Block Diagram

PLL Block

OSC2

OSC1

MULTI-

OSCILLATOR

(MO)

OSC

PLL x 2

/ 2

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an f

OSC2

of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2 = fOSC

/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See

Section 6.1 on page 23.

Caution: The PLL must not be used with the internal RC oscillator.

OSC2

PLL OPTION BIT

MAIN CLOCK

CONTROLLER

WITH REALTIME

CLOCK (MCC/RTC)

CPU

RESET

RESET SEQUENCE

MANAGER

(RSM)

WATCHDOG

TIMER (WDG)

23/154

ST72324Lxx

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in

Table 6. Refer to the

electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not

be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this con figuration, could generate an f

clock frequency

OSC

in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnect

ed.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer

Section 14.1 on page 140 for more details on

to the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscil

lator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resis tor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require ac curate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 6. ST7 Clock Sources

Hardware Configuration

ST7

OSC1 OSC2

External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator

EXTERNAL

SOURCE

OSC1 OSC2

CAPACITORS

OSC1 OSC2

ST7

LOAD

ST7

24/154

6.3 RESET SEQUENCE MANAGER (RSM)

ST72324Lxx

6.3.1 Introduction

The reset sequence manager includes two RESET sources as shown in Figure 13:

■ External RESET source pulse

■ Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

Figure 12:

option byte)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 12. RESET Sequence Phases

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated R This pull-up has no fixed value but varies in ac

weak pull-up resistor.

cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

order to be recognized. This detection is asynchro

nous and therefore the MCU can enter reset state even in HALT mode.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris

tics section.

6.3.3 External Power-On RESET

To start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V the minimum level specified for the selected f

is over

OSC

frequency. A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net

work connected to the RESET pin.

6.3.4 Internal Watchdog RESET

Starting from the Watchdog counter underflow, the device low during at least t

RESET pin acts as an output that is pulled

w(RSTL)out

Figure 13. Reset Block Diagram

RESET

Filter

PULSE

GENERATOR

INTERNAL RESET

WATCHDOG RESET

25/154

ST72324Lxx

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non maskable events: RESET, TRAP

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nest

ed) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see

Table 7). The process-

ing flow is shown in Figure 14

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 7. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main) Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

Low

High

1 0

Figure 14. Interrupt Processing Flowchart

RESET

RESTORE PC, X, A, CC

FROM STACK

26/154

PENDING

INTERRUPT

FETCH NEXT

INSTRUCTION

“IRET”

EXECUTE

INSTRUCTION

THE INTERRUPT

STAYS PENDING

TRAP

Interrupt has the same or a

lower software priority

than current one

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

I1:0

software priority

than current one

Interrupt has a higher

INTERRUPTS (Cont’d)

ST72324Lxx

Servicing Pending Interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account is deter

mined by the following two-step process: – the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 15 describes this decision process.

Figure 15. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware pri

ority becomes the highest one. Note 1: The hardware priority is exclusive while

the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET and TRAP can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 14). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced accord

ing to the flowchart in Figure 14.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the high

est hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two condi

tions is false, the interrupt is latched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitiv

ity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral inter

rupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se

quence is executed.

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ST72324Lxx

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exit

ing HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision proc

ess shown in Figure 15.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 16. Concurrent Interrupt Management

TRAP

IT0

TRAP

IT0

IT1

RIM

IT2

IT1

IT4

IT3

IT1

HARDWARE PRIORITY

MAIN

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7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 16 and Figure 17 show two different interrupt management modes. The first is called concurrent mode and does not allow an in terrupt to be interrupted, unlike the nested mode in

Figure 17. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is giv en for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

SOFTWARE PRIORITY LEVEL

IT3

IT4

MAIN

3 3 3 3 3 3 3/0

11 11 11 11 11 11

USED STACK = 10 BYTES

Figure 17. Nested Interrupt Management

IT4

IT3

TRAP

IT0

HARDWARE PRIORITY

MAIN

RIM

IT2

IT1

IT4

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IT4

IT0

IT3

IT1

SOFTWARE PRIORITY LEVEL

IT2

MAIN

I1 I0

3 3 2 1 3 3 3/0

11 11 00 01 11 11

USED STACK = 20 BYTES

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

ST72324Lxx

CPU CC REGISTER INTERRUPT BITS

Read / Write Reset Value: 111x 1010 (xAh)

7 0

1 1 I1 H I0 N Z C

Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft-

ware priority.

Interrupt Software Priority Level I1 I0

Level 0 (main) Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1

Low

High

1 0

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri

ority registers (ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP in

structions (see “Interrupt Dedicated Instruction Set” table).

*Note: TRAP and RESET events can interrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

7 0

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This corre

spondance is shown in the following table.

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits* FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex

ample: previous=CFh, write=64h, result=44h)

The RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following be

haviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ

ous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the inter

rupt x).

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ST72324Lxx

INTERRUPTS (Cont’d)

Table 8. Dedicated Interrupt Instruction Set

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 (level 3) I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

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