ST ST72321M6, ST72321M9 User Manual

80-pin 8-bit MCU with 32 to 60 Kbytes Flash, ADC,

LQFP80

14 x 14

Features

■ Memories

– 32 Kbytes to 60 Kbytes dual voltage High

Density Flash (HDFlash) with read-out protection capability. In-application programming

and In-circuit programming. – 1 Kbyte to 2 Kbytes RAM – HDFlash endurance: 100 cycles at 85 °C;

data retention: 40 years at 85 °C

■ Clock, reset and supply management

– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability – Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator and bypass for

external clock – PLL for 2x frequency multiplication – Four power saving modes: Halt, Active-Halt,

Wait and Slow

■ Interrupt management

– Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – Top Level Interrupt (TLI) pin – 15 external interrupt lines (on 4 vectors)

■ Up to 64 I/O ports

– 64 multifunctional bidirectional I/O lines – 34 alternate function lines – 16 high sink outputs

■ 5 timers

– Main clock controller with: Real-time base,

Beep and Clock-out capabilities – Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and pulse generator modes – 8-bit PWM Auto-Reload timer with: 2 input

captures, 4 PWM outputs, output compare

and time base interrupt, external clock with

ST72321M6 ST72321M9

five timers, SPI, SCI, I

event detector

■ 4 Communication interfaces

– SPI synchronous serial interface – SCI asynchronous serial interface

C multimaster interface

–I

(SMbus V1.1 compliant)

■ Analog periperal (low current coupling)

– 10-bit ADC with 16 input robust input ports

■ Instruction set

– 8-bit data manipulation – 63 basic Instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction

■ Development tools

– Full hardware/software development package – In-circuit testing capability

C interface

Table 1. Device summary

Features ST72321M9 ST72321M6

Flash program memory 60 Kbytes 32 Kbytes RAM (stack) - bytes 2048 bytes (256 bytes) 1024 (256 bytes) Operating voltage 3.8 V to 5.5 V Temperature range -40 °C to +85 °C Package LQFP80 14x14

May 2009 Doc ID 12706 Rev 2 1/175

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.4.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 39

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.4.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 51

9.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.2 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC) . . 53

9.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.2.3 Real-Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.4.6 Summary of Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

9.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

9.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

9.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

9.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

9.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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9.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

9.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

9.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

9.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

10.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

10.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

11.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

11.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

11.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 137

11.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

11.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

175

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11.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

11.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

11.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

11.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

11.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

11.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

11.5.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

11.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 148

11.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

11.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 150

11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

11.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

11.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

11.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

11.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 158

11.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

11.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

11.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

11.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

11.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

12 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12.3 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

13 ST72321Mx DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . 167

13.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

13.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

14 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

14.1 SAFE CONNECTION OF OSC1/OSC2 PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

14.2 RESET PIN PROTECTION WITH LVD ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

14.3 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

14.4 EXTERNAL INTERRUPT MISSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

14.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . . 171

14.6 SCI WRONG BREAK DURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

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Table of Contents

14.7 16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

14.8 TIMD SET SIMULTANEOUSLY WITH OC INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . 172

14.9 I2C MULTIMASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

14.10INTERNAL RC OSCILLATOR WITH LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

14.11I/O BEHAVIOUR DURING ICC MODE ENTRY SEQUENCE . . . . . . . . . . . . . . . . . . . . 172

14.12READ-OUT PROTECTION WITH LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

15 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

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175

ST72321M6 ST72321M9

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

CONTROL

PROGRAM

(32 - 60 Kbytes)

RESET

PORT F

PF7:0

(8-bits)

TIMER A

BEEP

PORT A

RAM

(1024-2048 Bytes)

PORT C

10-BIT ADC

AREF

SSA

PORT B

PB7:0

(8-bits)

PWM ART

PORT E

PE7:0 (8-bits)

SCI

TIMER B

PA7:0

(8-bits)

PORT D

PD7:0

(8-bits)

SPI

PC7:0

(8-bits)

WATCHDOG

TLI

OSC

LVD

OSC2

MEMORY

MCC/RTC/BEEP

EVD

AVD

I2C

PORT G

PG7:0

(8-bits)

PORT H

PH7:0

(8-bits)

1 INTRODUCTION

The ST72321Mx Flash devices are members of the ST7 microcontroller family designed for midrange applications.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with Flash memory.

Under software control, all devices can be placed in Wait, Slow, Active-halt or Halt mode, reducing

Figure 1. Device Block Diagram

power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

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ST72321M6 ST72321M9

3 4 5 6 7 8

262827

56 55 54 53 52 51

60 59

666865

727473

PA4 (HS)

SS_1

DD_1

PA3 (HS)

PC3 (HS) /ICAP1_B PC2(HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B /AIN12

PA7 (HS) / SCLI

PA6 (HS) / SDAI

PA5 (HS)

PA2 PA1 PA0 PC7 / SS / AIN15

PH2

PC5 / MOSI / AIN14

PWM0 / PB3

PG0

PG1 PG2

AIN3 / PD3

(HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2

PG3

ARTCLK / (HS) PB4

ARTIC1 / PB5 ARTIC2 / PB6

PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2

(HS) PE4 (HS) PE5 (HS) PE6

DD3

SS3

MCO /AIN8 / PF0

BEEP / (HS) PF1

ICAP1_A / (HS) / PF6

AIN6 / PD6

AIN7 / PD7

AREF

SSA

(HS) PF2

OCMP2_A / AIN9 /PF3

OCMP1_A/AIN10 /PF4

EXTCLK_A / (HS) PF7

222423

PG6

PG7

AIN4/PD4

AIN5 / PD5

PE0 / TDO

TLI

EVD

RESET

/ ICCSEL

PE3

PE2

PE1 / RDI

PH7

PH6

OSC1

OSC2

PC4 / MISO / ICCDATA

PH1

PH3

PC6 / SCK /ICCCLK

PH4

PH5

PG4

PG5

VSS_0 VDD_0

ICAP2_A/ AIN11 /PF5

PH0

(HS) 20 mA high sink capability eix associated external interrupt vector

ei1

ei3

ei2

ei0

2 PIN DESCRIPTION

Figure 2. 80-Pin LQFP 14x14 Package Pinout

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ST72321M6 ST72321M9

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations for Table 2 :

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3V

CT= CMOS 0.3VDD/0.7VDD with input trigger

= TTL 0.8 V / 2 V with Schmitt trigger

Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt – Output: OD = open drain

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

Table 2. Device Pin Description

/0.7V

, PP = push-pull

, ana = analog

Pin n°

Pin Name

LQFP80

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

function

Main

(after reset)

1PE4 (HS) I/OCTHS X XXXPort E4

2PE5 (HS) I/OC

3PE6 (HS) I/OC

4PE7 (HS) I/OC

5 PB0/PWM3 I/O C

6 PB1/PWM2 I/O C

7 PB2/PWM1 I/O C

8 PB3/PWM0 I/O C

9PG0 I/OT

10 PG1 I/O T

11 PG2 I/O T

12 PG3 I/O T

13 PB4 (HS)/ARTCLK I/O C

14 PB5/ARTIC1 I/O C

15 PB6/ARTIC2 I/O C

16 PB7 I/O C

17 PD0 /AIN0 I/O C

18 PD1/AIN1 I/O C

19 PD2/AIN2 I/O C

20 PD3/AIN3 I/O C

21 PG6 I/O T

22 PG7 I/O T

23 PD4/AIN4 I/O C

24 PD5/AIN5 I/O C

25 PD6/AIN6 I/O C

HS X XXXPort E5

HS X XXXPort E6

HS X XXXPort E7

X ei2 X X Port B0 PWM Output 3

X ei2 X X Port B1 PWM Output 2

X ei2 X X Port B2 PWM Output 1

X ei2 X X Port B3 PWM Output 0

X XXXPort G0

X XXXPort G1

X XXXPort G2

X XXXPort G3

HS X ei3 X X Port B4 PWM-ART External Clock

X ei3 X X Port B5 PWM-ART Input Capture 1

X ei3 X X Port B6 PWM-ART Input Capture 2

X ei3 X X Port B7

X X X X X Port D0 ADC Analog Input 0

X X X X X Port D1 ADC Analog Input 1

X X X X X Port D2 ADC Analog Input 2

X X X X X Port D3 ADC Analog Input 3

X XXXPort G6

X XXXPort G7

X X X X X Port D4 ADC Analog Input 4

X X X X X Port D5 ADC Analog Input 5

X X X X X Port D6 ADC Analog Input 6

Alternate function

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ST72321M6 ST72321M9

Pin n°

Pin Name

LQFP80

26 PD7/AIN7 I/O C

27 V

28 V

29 V

30 V

AREF

SSA

DD_3

SS_3

31 PG4 I/O T

32 PG5 I/O T

33 PF0/MCO/AIN8 I/O C

34 PF1 (HS)/BEEP I/O C

35 PF2 (HS) I/O C

36 PF3/OCMP2_A/AIN9 I/O C

37 PF4/OCMP1_A/AIN10 I/O C

38 PF5/ICAP2_A/AIN11 I/O C

39 PF6 (HS)/ICAP1_A I/O C

40 PF7 (HS)/EXTCLK_A I/O C

41 V

42 V

DD_0

SS_0

43 PC0/OCMP2_B/AIN12 I/O C

44 PC1/OCMP1_B/AIN13 I/O C

45 PC2 (HS)/ICAP2_B I/O C

46 PC3 (HS)/ICAP1_B I/O C

47 PC4/MISO/ICCDATA I/O C

48 PC5/MOSI/AIN14 I/O C

49 PH0 I/O T

50 PH1 I/O T

51 PH2 I/O T

52 PH3 I/O T

Level Port

Type

Input

Output

float

X X X X X Port D7 ADC Analog Input 7

Input Output

wpu

int

ana

function

Main

(after reset)

Alternate function

I Analog Reference Voltage for ADC

S Analog Ground Voltage

S Digital Main Supply Voltage

S Digital Ground Voltage

X XXXPort G4

X XXXPort G5

X ei1 X X X Port F0

Main clock out (f

CPU

)

ADC Analog Input 8

HS X ei1 X X Port F1 Beep signal output

HS X ei1 X X Port F2

Timer A Out-

X XXXXPort F3

put Compare 2

Timer A Out-

X XXXXPort F4

put Compare 1

X XXXXPort F5

Timer A Input Capture 2

ADC Analog Input 9

ADC Analog Input 10

ADC Analog Input 11

HS X X X X Port F6 Timer A Input Capture 1

HS X XXXPort F7

Timer A External Clock Source

S Digital Main Supply Voltage

S Digital Ground Voltage

Timer B Out-

X XXXXPort C0

put Compare 2

Timer B Out-

X XXXXPort C1

put Compare 1

HS X X X X Port C2 Timer B Input Capture 2

HS X X X X Port C3 Timer B Input Capture 1

SPI Master In

X XXXPort C4

/ Slave Out Data

SPI Master

X XXXXPort C5

Out / Slave In Data

X XXXPort H0

X XXXPort H1

X XXXPort H2

X XXXPort H3

ADC Analog Input 12

ADC Analog Input 13

ICC Data Input

ADC Analog Input 14

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ST72321M6 ST72321M9

Pin n°

Pin Name

LQFP80

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

function

Main

(after reset)

Alternate function

SPI Serial Clock

53 PC6/SCK/ICCCLK I/O C

X XXXPort C6

Caution: Negative current

injection not allowed on this pin

SPI Slave

54 PC7/SS/AIN15 I/O C

X XXXXPort C7

Select (active low)

55 PA0 I/O C

56 PA1 I/O C

57 PA2 I/O C

58 PA3 (HS) I/O C

59 V

60 V

DD_1

SS_1

61 PA4 (HS) I/O C

62 PA5 (HS) I/O C

63 PA6 (HS)/SDAI I/O C

S Digital Main Supply Voltage

S Digital Ground Voltage

64 PA7 (HS)/SCLI I/O CTHS X TPort A7 I

X ei0 X X Port A0

X ei0 X X Port A1

X ei0 X X Port A2

HS X ei0 X X Port A3

HS X XXXPort A4

HS X XXXPort A5

HS X TPort A6 I

C Data

C Clock

Must be tied low. In Flash programming

65 V

66 RESET

/ ICCSEL I

I/O C

mode, this pin acts as the programming voltage input V

Top priority non maskable interrupt.

67 EVD External voltage detector

68 TLI I C

69 PH4 I/O T

70 PH5 I/O T

71 PH6 I/O T

72 PH7 I/O T

73 V

74 OSC2

75 OSC1

76 V

SS_2

DD_2

S Digital Ground Voltage

I/O Resonator oscillator inverter output

S Digital Main Supply Voltage

77 PE0/TDO I/O C

78 PE1/RDI I/O C

79 PE2 I/O C

80 PE3 I/O C

X X Top level interrupt input pin

X XXXPort H4

X XXXPort H5

X XXXPort H6

X XXXPort H7

External clock input or Resonator oscillator inverter input

X X X X Port E0 SCI Transmit Data Out

X X X X Port E1 SCI Receive Data In

X Port E2

X XXXPort E3

ICC Clock Output

ADC Analog Input 15

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. It is mandatory to connect all available V

and V

pins to the supply voltage and all VSS and V

REF

SSA

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ST72321M6 ST72321M9

pins to ground.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator.

4. On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

5. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V are not implemented).

12/175

3 REGISTER & MEMORY MAP

0000h

RAM

Program Memory

(60 Kbytes or 32 Kbytes)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 3)

1000h

FFDFh FFE0h

FFFFh

0880h

Reserved

087Fh

Short Addressing RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

0100h

01FFh

0080h

0200h

00FFh

or 087Fh

32 Kbytes

8000h

60 Kbytes

FFFFh

1000h

(2048 or 1024 Bytes)

or 067Fh

or 047Fh

ST72321M6 ST72321M9

As shown in Figure 3, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 3. Memory Map

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

4 FLASH PROGRAM MEMORY

4 Kbytes

2Kbytes

SECTOR 1 SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K

FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8Kbytes 40 Kbytes

52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

ST72321M6 ST72321M9

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V

supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ Three Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be programmed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be programmed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 4). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 4). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 4. Sectors available in Flash devices

Flash Size (Kbytes) Available Sectors

4Sector 0

8 Sectors 0,1

> 8 Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection is enabled and removed through the FMP_R bit in the option byte.

Note: The LVD is not supported if read-out protection is enabled.

Figure 4. Memory Map and Sector Address

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ST72321M6 ST72321M9

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10kΩ

ICCSEL/VPP

ST7

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See Note 4)

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 5). These pins are:

– RESET –V

: device reset

: device power supply ground

Figure 5. Typical ICC Interface

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V

: programming voltage

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

: application board power supply (option-

–V

al, see Figure 5, Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET flicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1 kΩ). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1 kΩ or

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pin. This can lead to con-

a reset management IC with open drain output and pull-up resistor>1 kΩ, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

ST72321M6 ST72321M9

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 5). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 0000 0000 (00h)

00000000

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Figure 6. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

0029h

Label

FCSR

Reset Value00000000

76543210

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ST72321M6 ST72321M9

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 7. CPU Registers

5.3 CPU REGISTERS

The six CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

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ST72321M6 ST72321M9

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

11I1HI0NZ

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re-

sult 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

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ST72321M6 ST72321M9

PCH PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCH PCL

PCL

PCH

PCH PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh Stack Lower Address =

0100h

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write Reset Value: 01 FFh

15 8

00000001

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 2).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack

tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 2.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

higher address.

Figure 8. Stack Manipulation Example

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ST72321M6 ST72321M9

PLL OPTION BIT

PLL x 2

OSC2

/ 2

OSC

LOW VOLTAGE

DETECTOR

(LVD)

OSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

EVD

RESET SEQUENCE

MANAGER

(RSM)

OSC2

MAIN CLOCK

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD

AVD AVD

LVD

WDG

OSC

(option)

CPU

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10.

For more details, refer to dedicated parametric section.

Main features

■ Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators – 1 Internal RC oscillator

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) – Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply or the EVD pin

Figure 10. Clock, Reset and Supply Block Diagram

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an f

OSC2

of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2 = fOSC

/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 146.

Figure 9. PLL Block Diagram

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ST72321M6 ST72321M9

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

OSC1 OSC2

ST7

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 5. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an f

clock frequency

OSC

in excess of the allowed maximum (>16 MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 13.1 on page 167 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 5. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator

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ST72321M6 ST72321M9

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

WATCHDOG RESET

LVD RESET

INTERNAL RESET

PULSE

GENERATOR

Filter

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 12:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases

as shown in Figure 11:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

option byte)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 13.1 on page 167).

Figure 12. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. RESET Sequence Phases

6.3.2 Asynchronous External RESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See

“CONTROL PIN CHARACTERISTICS” on page 154 for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

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ST72321M6 ST72321M9

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

w(RSTL)out

RUN

h(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

w(RSTL)out

RUN RUN RUN

RESET

RESET SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 T

CPU

)

VECTOR FETCH

w(RSTL)out

PHASE

ACTIVE

PHASE

ACTIVE PHASE

DELAY

RESET SEQUENCE MANAGER (Cont’d)

The RESET plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

If the external RESET t

w(RSTL)out

signal on the RESET wise the delay will not be applied (see long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the device RESET as an output that is pulled low during at least t

w(RSTL)out

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V level specified for the selected f (see “OPERATING CONDITIONS” on page 136)

Figure 13. RESET Sequences

pin is an asynchronous signal which

pulse is shorter than

(see short ext. Reset in Figure 13), the

pin may be stretched. Other-

pin acts

is over the minimum

frequency.

OSC

A proper reset signal for a slow rising V

supply

can generally be provided by an external RC network connected to the RESET

pin.

6.3.4 Internal Low Voltage Detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 13.

The LVD filters spikes on V

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is pulled

w(RSTL)out

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ST72321M6 ST72321M9

IT+

RESET

IT-

hys

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD), and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the V below a V

reference value. This means that it

IT-

supply voltage is

secures the power-up as well as the power-down keeping the ST7 in reset.

The V than the V

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

is below:

when VDD is rising

–V

IT+

when VDD is falling

–V

IT-

The LVD function is illustrated in Figure 14. The voltage threshold can be configured by option

byte to be low, medium or high.

Provided the minimum V the oscillator frequency) is above V

value (guaranteed for

, the MCU

IT-

can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. If the medium or low thresholds are selected, the

detection may occur outside the specified operating voltage range. Below 3.8 V, device operation is not guaranteed.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the V

supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Figure 14. Low Voltage Detector vs Reset

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ST72321M6 ST72321M9

IT+(AVD)

IT-(AVD)

AVDF bit 0 0RESET VALUE

IF AVDIE bit = 1

hyst

AVD INTERRUPT REQUEST

INTERRUPT PROCESS

IT+(LVD)

IT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

VOLTAGE RISE TIME

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a V V

IT+(AVD)

reference value and the VDD main sup-

IT-(AVD)

ply or the external EVD pin voltage level (V The V than the V

reference value for falling voltage is lower

IT-

reference value for rising voltage in

IT+

order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly read-

able by the application software through a realtime status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the V

Main Supply

This mode is selected by clearing the AVDS bit in the SICSR register.

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see section 13.1 on page 167).

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V V

IT-(AVD)

threshold (AVDF bit toggles).

Figure 15. Using the AVD to Monitor V

and

EVD

IT+(AVD)

(AVDS bit=0)

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 15.

The interrupt on the rising edge is used to inform the application that the V

If the voltage rise time t

warning state is over.

is less than 256 or 4096

CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V

is greater than 256 or 4096 cycles then:

If t

IT+(AVD)

is reached.

– If the AVD interrupt is enabled before the

IT+(AVD)

threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached.

– If the AVD interrupt is enabled after the V

threshold is reached then only one AVD interrupt will occur.

IT+(AVD)

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ST72321M6 ST72321M9

EVD

IT+(EVD)

IT-(EVD)

AVDF 0 01

IF AVDIE = 1

hyst

AVD INTERRUPT REQUEST

INTERRUPT PROCESS

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin

This mode is selected by setting the AVDS bit in the SICSR register.

The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This interrupt is generated on the rising and falling edges

Figure 16. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)

of the comparator output. This means it is generated when either one of these two events occur:

–V –V

rises up to V

EVD

falls down to V

EVD

IT+(EVD)

The EVD function is illustrated in Figure 16. For more details, refer to the Electrical Character-

istics section.

IT-(EVD)

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ST72321M6 ST72321M9

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Low Power Modes

Mode Description

WAIT

HALT The CRSR register is frozen.

6.4.3.1 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

set and the interrupt mask in the CC register is reset (RIM instruction).

Flag

Enable

Control

Bit

Interrupt Event

AVD event AVDF AVDIE Yes No

Event

Exit from Wait

Exit

from

Halt

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