ST ST72321AR6, ST72321R6, ST72321AR7, ST72321J7, ST72321R7 User Manual

8-bit MCU for automotive with 32/60 Kbyte Flash/ROM,

LQFP64

10 x 10

LQFP64

14 x 14

LQFP44

10 x 10

ADC, 5 timers, SPI, SCI, I2C interface

Features

Memories

■ 32 to 60 Kbyte dual voltage High Density Flash

(HDFlash) or ROM ROM with readout
protection capability. In-application
programming and in-circuit programming for
HDFlash devices

■ 1 to 2 Kbyte RAM

■ HDFlash endurance: 100 cycles, data retention

20 years

Clock, reset and supply management

■ Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector
(AVD) with interrupt capability

■ Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and bypass
for external clock

■ PLL for 2x frequency multiplication

■ 4 power saving modes: Halt, Active Halt, Wait

and Slow

Interrupt management

■ Nested interrupt controller

■ 14 interrupt vectors plus TRAP and RESET

■ Top Level Interrupt (TLI) pin on 64-pin devices

■ 15 external interrupt lines (on 4 vectors)

1 analog peripheral

■ 10-bit ADC with up to 16 input ports

Up to 48 I/O ports

■ 48//32 multifunctional bidirectional I/O lines

■ 34//22 alternate function lines

■ 16//12 high sink outputs

ST72321xx-Auto

5 timers

■ Main clock controller with Real-time base,

Beep and Clock-out capabilities

■ Configurable watchdog timer

■ Two 16-bit timers with 2 input captures, 2

output compares, external clock input on 1
timer, PWM and pulse generator modes

■ 8-bit PWM auto-reload timer with 2 input

captures, 4 PWM outputs, output compare and
time base interrupt, external clock with event
detector

3 communications interfaces

■ SPI synchronous serial interface

■ SCI asynchronous serial interface

2

■ I

C multimaster interface

Instruction set

■ 8-bit data manipulation

■ 63 basic instructions

■ 17 main addressing modes

■ 8x8 unsigned multiply instruction

Development tools

■ Full hardware/software development package,

ICT capability

Table 1. Device summary

Reference Part number

ST72321AR6-Auto,
ST72321R6-Auto,

ST72321xx-Auto

ST72321AR7-Auto,
ST72321J7-Auto, ST72321R7-Auto
ST72321AR9-Auto,
ST72321J9-Auto, ST72321R9-Auto

August 2010 Doc ID 13829 Rev 1 1/243

www.st.com

1

Contents ST72321xx-Auto

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1 Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.8 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.4 Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.5 Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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6.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.5.3 External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.5.4 Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 41

6.5.5 Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.6 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.6.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.6.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.6.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.6.5 System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 47

7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.5 Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 54

7.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.6.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.6.2 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 59

8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.4 Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.4.1 Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.6 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.7 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 80

10.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.9.1 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11 Main clock controller with real-time clock and beeper (MCC/RTC) . . 82

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.2 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.3 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.4 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.5 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

11.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

11.8 Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.8.1 MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.8.2 MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 85

12 PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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12.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12.2.2 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12.2.3 Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12.2.4 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12.2.5 Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.2.6 Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 90

12.2.7 External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 90

12.2.8 Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.2.9 External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.3 ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.3.1 Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.3.2 Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.3.3 Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.3.4 PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3.5 Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.3.6 Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . . 96

12.3.7 Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

13 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

13.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.3 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.4 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.3.5 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.3.6 One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.3.7 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.7.1 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.7.2 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

13.7.3 Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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13.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 116

13.7.5 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 117

13.7.6 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 117

13.7.7 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 117

13.7.8 Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 117

13.7.9 Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 118

13.7.10 Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

13.7.11 Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

13.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 118

13.7.13 Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 119

13.7.14 Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 119

13.7.15 Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.3.2 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.3.3 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.3.4 Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

14.3.5 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

14.3.6 Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

14.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

14.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.5.1 Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.5.2 Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.5.3 Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.5.4 Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

14.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.6.1 Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 130

14.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

14.8.1 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

14.8.2 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

14.8.3 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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15 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 135

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

15.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.4.1 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

15.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

15.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

15.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

15.7.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

15.7.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.7.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

15.7.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

15.7.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

15.7.6 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 152

15.7.7 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 153

16 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16.2.1 I2C master features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16.2.2 I2C slave features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

16.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

16.3.2 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

16.3.3 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

16.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

16.4.1 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

16.4.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

16.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

16.7.1 I2C control register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

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16.7.2 I2C status register 1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

16.7.3 I2C status register 2 (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

16.7.4 I2C clock control register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

16.7.5 I2C data register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

16.7.6 I2C own address register (OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

16.7.7 I2C own address register (OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

17 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

17.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

17.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

17.3.1 A/D converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

17.3.2 Starting the conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

17.3.3 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

17.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

17.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

17.6 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

17.6.1 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

17.6.2 Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

17.6.3 Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

17.6.4 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

18 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

18.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

18.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

18.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

18.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

18.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

18.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

18.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

18.1.7 Relative (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

18.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

18.2.1 Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

19 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

19.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

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19.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

19.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

19.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

19.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

19.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

19.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

19.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

19.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

19.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

19.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

19.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

19.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 189

19.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 189

19.3.4 External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . 190

19.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

19.4.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

19.4.2 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

19.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

19.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

19.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

19.5.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

19.5.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 196

19.5.4 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

19.5.5 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

19.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

19.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

19.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

19.7 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 200

19.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 200

19.7.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

19.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 202

19.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

19.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

19.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

19.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

19.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

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19.9.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

19.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

19.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 211

19.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

19.11.2 I

2

C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

19.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

19.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 217

19.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

19.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

20 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

20.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

20.2 Ecopack information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

20.3 Packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

21 Device configuration and ordering information . . . . . . . . . . . . . . . . . 223

21.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

21.1.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

21.1.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

21.2 ROM device ordering information and transfer of customer code . . . . . 227

21.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

21.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

21.3.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

21.3.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

21.3.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

21.3.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 232

21.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

22 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

22.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

22.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

22.1.2 Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 234

22.1.3 Reset pin protection with LVD enabled . . . . . . . . . . . . . . . . . . . . . . . . 234

22.1.4 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

22.1.5 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

22.1.6 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 238

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22.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

22.1.8 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

22.1.9 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 240

22.1.10 I

22.1.11 Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

2

C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

22.2 All Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

22.2.1 Internal RC oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

22.3 Limitations specific to ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

22.3.1 LVD operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

22.3.2 LVD startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

22.3.3 AVD not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

22.3.4 Internal RC oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

22.3.5 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

22.3.6 Pull-up not present on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

22.3.7 Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

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List of tables ST72321xx-Auto

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 4. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 5. Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6. Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. Arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8. Interrupt management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 9. Interrupt software priority selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 10. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 11. Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 12. AVD interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 13. SICSR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 14. Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 15. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 16. CPU CC register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 17. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 18. Interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 19. Interrupt dedicated instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 20. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 21. EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 22. Interrupt sensitivity - ei2 (port B3..0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 23. Interrupt sensitivity - ei3 (port B7..4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 24. Interrupt sensitivity - ei0 (port A3..0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 25. Interrupt sensitivity - ei1 (port F2..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 26. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 27. MCC/RTC low power mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 28. I/O output mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 29. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 30. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 31. I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 32. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 33. I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 34. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 35. Effect of low power modes on WDG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 36. WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 37. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 38. Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 39. MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 40. MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 41. Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 42. MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 43. Beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 44. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 45. ARTCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 46. Prescaler selection for ART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 47. ARTCAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 48. ARTAAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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Table 49. PWM frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 50. PWMCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 51. PWM output signal polarity selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 52. PWMDCRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 53. ARTICCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 54. ARTICRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 55. PWM auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 56. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 57. 16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 58. Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 59. CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 60. CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 61. Timer clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 62. CSR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 63. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 64. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 65. SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 66. SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 67. SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 68. SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 69. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 70. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 71. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 72. SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 73. SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 74. SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 75. SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 76. SCIBRR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 77. SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 78. SCIETPR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 79. Baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 80. SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 81. Effect of low power modes on I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 82. I2C interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 83. CR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 84. SR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 85. SR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 86. CCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 87. DR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 88. OAR1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 89. OAR2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 90. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 91. Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 92. ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 93. ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 94. ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 95. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 96. Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 97. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 98. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 99. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 100. Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes 180

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Table 101. Available relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 102. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 103. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 104. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 105. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 106. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 107. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 108. Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 109. Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 110. External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 111. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 112. Oscillators,PLL and LVD current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 113. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 114. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 115. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 116. Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 117. OSCRANGE selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 118. RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 119. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 120. RAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 121. Dual voltage HDFlash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 122. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 123. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 124. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 125. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 126. I/O port pin general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 127. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 128. Asynchronous RESET
Table 129. ICCSEL/V

pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

PP

pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 130. 8-bit PWM-ART auto-reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 131. 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 132. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 133. I

2

C control interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 134. SCL frequency table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 135. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 136. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Table 137. 64-pin (14x14) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 220

Table 138. 64-pin (10x10) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 221

Table 139. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 140. Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 141. Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 142. Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 143. Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 144. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 145. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 146. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

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ST72321xx-Auto List of figures

List of figures

Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2. 64-pin LQFP 14x14 and 10x10 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 3. 44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5. Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 8. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 9. Clock, reset and supply block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 10. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 11. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 12. RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13. RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 14. Low voltage detector versus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 15. Using the AVD to monitor V

Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1). . . . . . . . . . . . . . . . . . . 46

Figure 17. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 18. Priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 19. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 20. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 21. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 22. Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 23. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 24. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 25. Active Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 26. Active Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 27. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 28. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 29. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 30. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 31. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 32. Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 33. Exact timeout duration (t

Figure 34. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 35. PWM auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 36. Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 37. PWM auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 38. PWM signal from 0% to 100% duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 39. External event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 40. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 41. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 42. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 43. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 44. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 45. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 46. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 47. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 48. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

(AVDS bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DD

min

and t

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

max

Doc ID 13829 Rev 1 15/243

List of figures ST72321xx-Auto

Figure 49. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 50. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 51. One pulse mode cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 52. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 53. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . 110

Figure 54. Pulse width modulation cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 55. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 56. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 57. Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 58. Hardware/Software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 59. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence . . . . . . . . . . . . . . . . . . 129

Figure 61. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 62. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 63. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 64. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 65. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 66. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 67. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 68. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 69. Interrupt control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 70. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 71. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 72. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 73. f
Figure 74. Typical I
Figure 75. Typical I
Figure 76. Typical I
Figure 77. Typical I

max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

CPU

in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

DD

in Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

DD

in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

DD

in Slow Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

DD

Figure 78. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 79. Typical application with a crystal or ceramic resonator) . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 80. Typical f

OSC(RCINT)

versus TA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 81. Integrated PLL jitter versus signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 82. Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 83. Typical I

vs VDD with VIN=V

PU

SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 84. Typical VOL at VDD= 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 85. Typical V
Figure 86. Typical V
Figure 87. Typical V
Figure 88. Typical V
Figure 89. Typical V
Figure 90. RESET
Figure 91. RESET
Figure 92. Two typical applications with ICCSEL/V

at VDD= 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

OL

at VDD= 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

OH

versus VDD (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

OL

versus VDD (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

OL
DD-VOH

versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

PP

Figure 93. SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 94. SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 95. SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 96. Typical application with I
Figure 97. R
Figure 98. Recommended C

maximum versus f

AIN

AIN

2

C BUS and timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . 215

ADC

and R

with C

values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

AIN

= 0pF(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

AIN

Figure 99. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 100. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

16/243 Doc ID 13829 Rev 1

ST72321xx-Auto List of figures

Figure 101. ADC error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 102. 64-pin (14x14) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 103. 64-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 104. Pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 105. ST72F321xxx-Auto Flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 106. ST72P321xxx-Auto FastROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . 228

Figure 107. ST72321xxx-Auto ROM commercial product structure. . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 108. LVD startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Doc ID 13829 Rev 1 17/243

Description ST72321xx-Auto

1 Description

The ST72321xx-Auto Flash and ROM devices are members of the ST7 microcontroller
family designed for mid-range automotive applications running from 3.8 to 5.5V.

All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash program memory. The ST7 family architecture
offers both power and flexibility to software developers, enabling the design of highly
efficient and compact application code.

The on-chip peripherals include an A/D converter, a PWM autoreload timer, two general
purpose timers, I

2

C, SPI, SCI interfaces.

For power economy, the microcontroller can switch dynamically into Wait, Slow, Active Halt
or Halt mode when the application is in idle or standby state.

Table 2. Product overview

Reference Program memory RAM (stack) Voltage range Temp. range Package

ST72321R9-Auto

ST72321AR9-Auto LQFP64 10x10

ST72321J9-Auto LQFP48 10x10

ST72321R7-Auto

ST72321AR7-Auto LQFP64 10x10

ST72321J7-Auto LQFP48 10x10

ST72321R6-Auto

ST72321AR6-Auto LQFP64 10x10

60 Kbytes

Flash/ROM

48 Kbytes

Flash/ROM

32 Kbytes

Flash/ROM

2048 (256) bytes

1536 (256) byte

1024 (256) byte

3.8V to 5.5V

Up to

-40°C to 125°C

LQFP64 14x14

LQFP64 14x14

LQFP64 14x14

Typical applications include

● all types of car body applications such as window lift, DC motor control, rain sensors

● safety microcontroller in airbag and engine management applications

● auxiliary functions in car radios

18/243 Doc ID 13829 Rev 1

ST72321xx-Auto Description

8-bit CORE

ALU

ADDRESS AND DATA BUS

OSC1

V

PP

CONTROL

PROGRAM

(32 or 60 Kbytes)

V

DD

RESET

PORT F

PF7:0

(8-bits)

TIMER A

BEEP

PORT A

RAM

(1024 or 2048 bytes)

PORT C

10-bit ADC

V

AREF

V

SSA

PORT B

PB7:0

(8-bits)

PWM ART

PORT E

PE7:0

(8-bits)

SCI

TIMER B

PA 7: 0

(8-bits)

PORT D

PD7:0

(8-bits)

SPI

PC7:0

(8-bits)

V

SS

WATCHD OG

TLI

OSC

LV D

OSC2

MEMORY

MCC/RTC/BEEP

EVD

AVD

I2C

Figure 1. Device block diagram

Doc ID 13829 Rev 1 19/243

Package pinout and pin description ST72321xx-Auto

V

AREF

V

SSA

V

DD_3

V

SS_3

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP2_A / AIN9 / PF3

OCMP1_A / AIN10 / PF4

ICAP2_A / AIN11 / PF5

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47
46
45
44
43

42

41

40

39

38

37

36

35

34

33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

ei2

ei3

ei0

ei1

PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3

ARTCLK / (HS) PB4

ARTIC1 / PB5
ARTIC2 / PB6

PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3

(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7

PA 1
PA 0
PC7 / SS

/ AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
V

SS_0

V

DD_0

V

SS_1

V

DD_1

PA3 (HS )
PA 2

V

DD

_

2

OSC1

OSC2

V

SS

_

2

TLI

EVD

RESET

V

PP

/ ICCSEL

PA7 (HS) / SCLI

PA6 (HS ) / SDAI

PA5 (HS )

PA4 (HS )

PE3

PE2

PE1 / RDI

PE0 / TDO

(HS) 20mA high sink capability
eix associated external interrupt vector

2 Package pinout and pin description

2.1 Package pinout

Figure 2. 64-pin LQFP 14x14 and 10x10 package pinout

For external pin connection guidelines, refer to Section 19: Electrical characteristics.

20/243 Doc ID 13829 Rev 1

ST72321xx-Auto Package pinout and pin description

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

V

DD_0

V

SS_0

AIN5 / PD5

V

AREF

V

SSA

44 43 42 41 40 39 38 37 36 35 34

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18 19 20 21 22

1
2
3
4
5
6
7
8
9
10
11

ei2

ei3

ei0

ei1

PWM0 / PB3

ARTCLK / (HS) PB4

AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4

RDI / PE1
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2

PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12

V

SS_1

V

DD_1

PA3 (HS )
PC7 / SS

/ AIN15

V

SS

_2

RESET

V

PP

/ ICCSEL

PA7 (HS) / SCLI

PA6 (HS) / SDAI

PA5 (HS )

PA4 (HS )

PE0 / TDO

V

DD

_2

OSC1

OSC2

(HS) 20mA high sink capability
eix associated external interrupt vector

Figure 3. 44-pin LQFP package pinout

Doc ID 13829 Rev 1 21/243

Package pinout and pin description ST72321xx-Auto

2.2 Pin description

In the device pin description table, the RESET configuration of each pin is shown in bold.
This configuration is valid as long as the device is in reset state.

Refer to Section 9: I/O ports on page 70 for more details on the software configuration of the
I/O ports.

Table 3. Device pin description

Pin No.

Pin name

LQFP64

LQFP44

1

2

3

4

PE4(HS) I/O CTHS X XXXPort E4

-

PE5(HS) I/O CTHS X XXXPort E5

-

PE6(HS) I/O CTHS X XXXPort E6

-

PE7(HS) I/O CTHS X XXXPort E7

-

5 2 PB0/PWM3 I/O C

6 3 PB1/PWM2 I/O C

7 4 PB2/PWM1 I/O C

8 5 PB3/PWM0 I/O C

Level Port

Input Output

Typ e

Input

Output

float

T

T

T

T

X ei2 X X Port B0 PWM Output 3

X ei2 X X Port B1 PWM Output 2

X ei2 X X Port B2 PWM Output 1

X ei2 X X Port B3 PWM Output 0

Main

function

(after

int

wpu

ana

OD

reset)

PP

9 6 PB4(HS)/ARTCLK I/O CTHS X ei3 X X Port B4

10

11

12

PB5 / ARTIC1 I/O C

-

PB6 / ARTIC2 I/O C

-

PB7 I/O C

-

13 7 PD0/AIN0 I/O C

14 8 PD1/AIN1 I/O C

15 9 PD2/AIN2 I/O C

16 10 PD3/AIN3 I/O C

17 11 PD4/AIN4 I/O C

18 12 PD5/AIN5 I/O C

19

20

21 13 V

22 14 V

23 - V

24 - V

PD6/AIN6 I/O C

-

PD7/AIN7 I/O C

­(1)

AREF

(1)

SSA

(1)

DD_3

(1)

SS_3

I Analog Reference Voltage for ADC

S Analog Ground Voltage

S Digital Main Supply Voltage

S Digital Ground Voltage

T

T

T

T

T

T

T

T

T

T

T

X ei3 X X Port B5

X ei3 X X Port B6

X ei3 X X Port B7

X X X X X Port D0 ADC Analog Input 0

X X X X X Port D1 ADC Analog Input 1

X X X X X Port D2 ADC Analog Input 2

X X X X X Port D3 ADC Analog Input 3

X X X X X Port D4 ADC Analog Input 4

X X X X X Port D5 ADC Analog Input 5

X X X X X Port D6 ADC Analog Input 6

X X X X X Port D7 ADC Analog Input 7

Alternate function

PWM-ART External
Clock

PWM-ART Input
Capture 1

PWM-ART Input
Capture 2

22/243 Doc ID 13829 Rev 1

ST72321xx-Auto Package pinout and pin description

Table 3. Device pin description (continued)

Pin No.

LQFP64

Pin name

LQFP44

Type

25 15 PF0/MCO/AIN8 I/O C

26 16 PF1 (HS)/BEEP I/O C

27 17 PF2 (HS) I/O C

28

29 18

30

PF3/OCMP2_A/

-

AIN9

PF4/OCMP1_A/
AIN10

PF5/ICAP2_A/

-

AIN11

I/O C

I/O C

I/O C

31 19 PF6(HS)/ICAP1_A I/O C

32 20

33 21 V

34 22 V

35 23

PF7(HS)/
EXTCLK_A

(1)

DD_0

(1)

SS_0

PC0/OCMP2_B/
AIN12

I/O C

S Digital Main Supply Voltage

S Digital Ground Voltage

I/O C

Level Port

Input Output

Input

Output

float

T

T

T

T

T

T

T

T

T

X ei1 X X X Port F0

HS X ei1 X X Port F1 Beep signal output

HS X ei1 X X Port F2

X XXXXPort F3

X XXXXPort F4

X XXXXPort F5

HS X X X X Port F6 Timer A Input Capture 1

HS X XXXPort F7

X XXXXPort C0

int

wpu

ana

OD

function

PP

Main

(after

reset)

Alternate function

/2)

ADC
Analog
Input 8

ADC
Analog
Input 9

ADC
Analog
Input 10

ADC
Analog
Input 11

Main clock
out (f

OSC

Timer A
Output
Compare 2

Timer A
Output
Compare 1

Timer A
Input
Capture 2

Timer A External Clock
Source

Timer B
Output
Compare 2

ADC
Analog
Input 12

36 24

37 25

38 26

39 27

PC1/OCMP1_B/
AIN13

PC2(HS)/
ICAP2_B

PC3(HS)/
ICAP1_B

PC4/MISO/
ICCDATA

I/O C

I/O C

I/O C

I/O C

40 28 PC5/MOSI/AIN14 I/O C

Timer B

T

X XXXXPort C1

Output
Compare 1

HS X X X X Port C2 Timer B Input Capture 2

T

HS X X X X Port C3 Timer B Input Capture 1

T

SPI Master

T

X XXXPort C4

In / Slave
Out Data

SPI Master

T

X XXXXPort C5

Out / Slave
In Data

ADC
Analog
Input 13

ICC Data
Input

ADC
Analog
Input 14

Doc ID 13829 Rev 1 23/243

Package pinout and pin description ST72321xx-Auto

Table 3. Device pin description (continued)

Pin No.

LQFP64

Pin name

LQFP44

Level Port

Input Output

Type

Input

Output

float

Main

function

(after

int

wpu

ana

OD

PP

reset)

Alternate function

SPI Serial
Clock

41 29 PC6/SCK/ICCCLK I/O C

T

X XXXPort C6

Caution: Negative

current injection not
allowed on this pin
(Flash devices only)

SPI Slave

42 30 PC7/SS/AIN15 I/O C

T

X XXXXPort C7

Select
(active low)

43

44

PA0 I/O C

-

PA1 I/O C

-

45 - PA2 I/O C

46 31 PA3(HS) I/O C

47 32 V

48 33 V

DD_1

SS_1

(1)

(1)

S Digital Main Supply Voltage

S Digital Ground Voltage

49 34 PA4(HS) I/O C

50 35 PA5(HS) I/O C

51 36 PA6(HS)/SDAI I/O C

52 37 PA7(HS)/SCLI I/O C

T

T

T

T

T

T

T

T

X ei0 X X Port A0

X ei0 X X Port A1

X ei0 X X Port A2

HS X ei0 X X Port A3

HS X XXXPort A4

HS X XXXPort A5

HS X T Port A6 I2C Data

HS X T Port A7 I2C Clock

Must be tied low. In Flash
programming mode, this pin acts
as the programming voltage input

53 38 V

/ ICCSEL I

PP

VPP. See Section 19.9.2:

ICCSEL/VPP pin for more details.

High voltage must not be applied
to ROM devices.

54 39 RESET

I/O C

T

Top priority non-maskable interrupt

55 - EVD I A External voltage detector

ICC Clock
Output

ADC
Analog
Input 15

56 - TLI I C

57 40 V

SS_2

58 41 OSC2

59 42 OSC1

60 43 V

DD_2

(1)

(2)

(2)

(1)

S Digital Ground Voltage

I/O Resonator oscillator inverter output

I

S Digital Main Supply Voltage

61 44 PE0/TDO I/O C

62 1 PE1/RDI I/O C

T

T

T

X X X X Port E0 SCI Transmit Data Out

X X X X Port E1 SCI Receive Data In

X Top level interrupt input pin

24/243 Doc ID 13829 Rev 1

External clock input or Resonator
oscillator inverter input

ST72321xx-Auto Package pinout and pin description

Table 3. Device pin description (continued)

Pin No.

LQFP64

Pin name

LQFP44

PE2
(Flash device)

Level Port

Input Output

Type

Input

Output

float

X

Main

function

(after

int

wpu

ana

OD

PP

reset)

Alternate function

Por t E2
Caution: In Flash devices this port
is always input with weak pull-up.

Por t E2
Caution: In ROM devices, no

63 -

PE2
(ROM device)

I/O C

T

X XX

weak pull-up present on this port.
In LQFP44 this pin is not
connected to an internal pull-up
like other unbonded pins. It is
recommended to configure it as
output push-pull to avoid added
current consumption.

64

1. It is mandatory to connect all available VDD and V

2. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; see Section 6:

Supply, reset and clock management and Section 19.5: Clock and timing characteristics on page 195 for more details.

PE3 I/O C

-

T

X XXXPort E3

pins to the supply voltage and all VSS and V

AREF

SSA

pins to ground.

Legend / Abbreviations for Tabl e 3 :

Type: I = input

O = output
S = supply

Input level: A = dedicated analog input

In/Output level: C = CMOS 0.3V

DD

/0.7V

DD

CT= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

● Input: float = floating

wpu = weak pull-up
int = interrupt

(a)

ana = analog

● Output: OD = open-drain

(b)

PP = push-pull

a. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column

(wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, otherwise
the configuration is floating interrupt input.

b. In the open-drain output column, “T” defines a true open-drain I/O (P-Buffer and protection diode to V

implemented). See Section 9: I/O ports on page 70 and Section 19.8: I/O port pin characteristics on page 203
for more details.

are not

DD

Doc ID 13829 Rev 1 25/243

Register and memory map ST72321xx-Auto

0000h

RAM

Program Memory

(60K or 32K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 4)

1000h

FFDFh
FFE0h

FFFFh

(see Ta bl e 2 0 )

0880h

Reserved

087Fh

Short Addressing
RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

0100h

01FFh

0080h

0200h

00FFh

or 087Fh

32 KBytes

8000h

60 KBytes

FFFFh

1000h

(2048 or 1024 Bytes)

or 067Fh

or 047Fh

3 Register and memory map

As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.

The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of
RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256
bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing
a reserved area can have unpredictable effects on the device.

Related documentation

Executing Code in ST7 RAM (AN 985)

Figure 4. Memory map

Table 4. Hardware register map

Address Block Register label Register name Reset status Remarks

0000h
0001h

Por t A

0002h

0003h
0004h

Por t B

0005h

0006h
0007h
0008h

0009h
000Ah
000Bh

Por t C

Por t D

26/243 Doc ID 13829 Rev 1

PA DR
PA DDR
PA OR

PBDR
PBDDR
PBOR

PCDR
PCDDR
PCOR

PDDR
PDDDR
PDOR

Port A Data Register
Port A Data Direction Register
Port A Option Register

Port B Data Register
Port B Data Direction Register
Port B Option Register

Port C Data Register
Port C Data Direction Register
Port C Option Register

Port D Data Register
Port D Data Direction Register
Port D Option Register

00h

00h
00h

00h

00h
00h

00h

00h
00h

00h

00h
00h

(1)

(1)

(1)

(1)

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

ST72321xx-Auto Register and memory map

Table 4. Hardware register map (continued)

Address Block Register label Register name Reset status Remarks

(1)

(1)

R/W

(2)

R/W

(2)

R/W

R/W
R/W
R/W

R/W
Read Only
Read Only
R/W
R/W
R/W
R/W

000Ch
000Dh
000Eh

000Fh

0010h

0011h

0018h

0019h
001Ah
001Bh
001Ch
001Dh
001Eh

Por t E

Por t F

2

C

I

PEDR
PEDDR
PEOR

PFDR
PFDDR
PFOR

I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR

Port E Data Register
Port E Data Direction Register
Port E Option Register

Port F Data Register
Port F Data Direction Register
Port F Option Register

2

C Control Register

I

2

C Status Register 1

I
I2C Status Register 2
I2C Clock Control Register

2

C Own Address Register 1

I
I2C Own Address Register2
I2C Data Register

00h

00h
00h

00h

00h
00h

00h
00h
00h
00h
00h
00h
00h

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

SPI

ITC

SPIDR
SPICR
SPICSR

ISPR0
ISPR1
ISPR2
ISPR3

SPI Data I/O Register
SPI Control Register
SPI Control/Status Register

Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3

Reserved Area (2 bytes)

xxh
0xh
00h

FFh
FFh
FFh
FFh

R/W
R/W
R/W

R/W
R/W
R/W
R/W

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh SICSR System Integrity Control/Status Register 000x 000x b R/W

002Ch
002Dh

MCC

MCCSR
MCCBCR

Main Clock Control / Status Register
Main Clock Controller: Beep Control Register

00h
00h

R/W
R/W

002Eh

to

Reserved Area (3 bytes)

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh

TIMER A

TACR2
TACR1
TA CS R
TA I C1 H R
TAIC1LR
TA OC 1 H R
TA OC 1 L R
TACHR
TA CL R
TA AC H R
TA AC L R
TA I C2 H R
TAIC2LR
TA OC 2 H R
TA OC 2 L R

Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register

00h
00h

xxxx x0xx b

xxh
xxh
80h
00h

FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

Doc ID 13829 Rev 1 27/243

Register and memory map ST72321xx-Auto

Table 4. Hardware register map (continued)

Address Block Register label Register name Reset status Remarks

0040h Reserved Area (1 byte)

0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h

0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h
006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h
007Ah

007Bh
007Ch
007Dh

TIMER B

SCI

ADC

PWM ART

TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR

ADCCSR
ADCDRH
ADCDRL

PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2

Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register

Reserved Area (24 Bytes)

Control/Status Register
Data High Register
Data Low Register

PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1

00h
00h

xxxx x0xx b

xxh
xxh
80h

00h
FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

C0h

xxh

00h

x000 0000b

00h

00h

---

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

Read Only
R/W
R/W
R/W
R/W
R/W

R/W

R/W
Read Only
Read Only

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only

007Eh
007Fh

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

Reserved Area (2 bytes)

Note: Legend: x = undefined, R/W = read/write

28/243 Doc ID 13829 Rev 1

ST72321xx-Auto Flash program memory

4 Flash program memory

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by­byte basis using an external V

The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).

The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.

4.2 Main features

● 3 Flash programming modes:

– Insertion in a programming tool. In this mode, all sectors including option bytes

can be programmed or erased.

– ICP (in-circuit programming). In this mode, all sectors including option bytes can

be programmed or erased without removing the device from the application board.

– IAP (in-application programming). In this mode, all sectors except Sector 0 can be

programmed or erased without removing the device from the application board
and while the application is running.

● ICT (in-circuit testing) for downloading and executing user application test patterns in

RAM

● Readout protection

● Register Access Security System (RASS) to prevent accidental programming or

erasing

supply.

PP

4.3 Structure

The Flash memory is organized in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Ta b l e 5 ). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.

Table 5. Sectors available in Flash devices

The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).

Flash size (bytes) Available sectors

4K Sector 0

8K Sectors 0, 1

> 8K Sectors 0, 1, 2

Doc ID 13829 Rev 1 29/243

Flash program memory ST72321xx-Auto

4 Kbytes

4 Kbytes

2Kbytes

SECTOR 1

SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K

FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8Kbytes 40 Kbytes

52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

Figure 5. Memory map and sector address

4.3.1 Readout protection

Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.

In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.

Note:

4.4 ICC interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see

Figure 6). These pins are:

RESET
V
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/V
OSC1 (or OSCIN): main clock input for external source (optional)
V

: device reset

: device power supply ground

SS

: programming voltage

PP

: application board power supply (optional, see Figure 6, Note 3)

DD

30/243 Doc ID 13829 Rev 1

ST72321xx-Auto Flash program memory

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

V

DD

HE10 CONNECTOR TYPE

APPLICATION
POWER SUPPLY

1

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10k

V

SS

ICCSEL/VPP

ST7

C

L2

C

L1

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION
RESET SOURCE

APPLICATION

I/O

(See Note 4)

Figure 6. Typical ICC interface

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the
programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to
implemented in case another device forces the signal. Refer to the programming tool documentation for recommended
resistor values.

2. During the ICC session, the programming tool must control the RESET
programming tool and the application reset circuit if it drives more than 5mA at high level (push-pull output or pull-up
resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical
RC network with R > 1K or a reset management IC with open-drain output and pull-up resistor > 1K, no additional
components are needed. In all cases the user must ensure that no external reset is generated by the application during the
ICC session.

3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when
using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool
manual.

4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the
selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2
grounded in this case.

pin. This can lead to conflicts between the

4.5 ICP (in-circuit programming)

To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.

Doc ID 13829 Rev 1 31/243

Flash program memory ST72321xx-Auto

4.6 IAP (in-application programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user
application, (such as user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored). For example, it is possible to
download code from the interface and program it in the Flash. IAP mode can be used to
program any of the Flash sectors except Sector 0, which is write/erase protected to allow
recovery in case errors occur during the programming operation.

4.7 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual

.

4.8 Flash control/status register (FCSR)

FSCR Reset value: 0000 0000 (00h)

76543210

00000000

RW RW RW RW RW RW RW RW

This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.

Table 6. Flash control/status register address and reset value

Address (Hex.) Register label 7 6 5 4 3 2 1 0

0029h

FCSR
Reset value 00000000

32/243 Doc ID 13829 Rev 1

ST72321xx-Auto Central processing unit (CPU)

Accumulator

X index register

Y index register

Stack pointer

Condition code register

Program counter

70

1C1I1HI0NZ

Reset value = reset vector @ FFFEh-FFFFh

70

70

70

0715 8PCH PCL

15 8 7 0

Reset value = stack higher address

Reset value =1 X11X1XX

Reset value = XXh

Reset value = XXh

Reset value = XXh

X = undefined value

5 Central processing unit (CPU)

5.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8­bit data manipulation.

5.2 Main features

● Enable executing 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes (with indirect addressing mode)

● Two 8-bit index registers

● 16-bit stack pointer

● Low power Halt and Wait modes

● Priority maskable hardware interrupts

● Non-maskable software/hardware interrupts

5.3 CPU registers

The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.

Figure 7. CPU registers

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Central processing unit (CPU) ST72321xx-Auto

5.3.1 Accumulator (A)

The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations as well as data manipulations.

5.3.2 Index registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation (the Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

5.3.3 Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).

5.3.4 Condition code (CC) register

The 8-bit condition code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

CC Reset value: 111x1xxx

76543210

11I1HI0NZC

RW RW RW RW RW RW

Table 7. Arithmetic management bits

Bit Name Function

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same

H

4

2N

instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic

1).
This bit is accessed by the JRMI and JRPL instructions.

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ST72321xx-Auto Central processing unit (CPU)

Table 7. Arithmetic management bits (continued)

Bit Name Function

Zero

This bit is set and cleared by hardware. This bit indicates that the result of the last

1Z

C

0

Table 8. Interrupt management bits

Bit Name Function

arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.

Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.

5

3

Table 9. Interrupt software priority selection

Interrupt Software Priority 1

I1

I0

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priority 0

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt software priority Level I1 I0

Level 0 (main)

Level 1 01

Level 2 00

Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.

See Chapter 7: Interrupts on page 49 for more details.

5.3.5 Stack pointer (SP) register

7

SP Reset value: 01 FFh

1514131211109876543210

Low

High

10

00000001SP7SP6SP5SP4SP3SP2SP1SP0

RW RW RW RW RW RW RW RW

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Central processing unit (CPU) ST72321xx-Auto

PCH
PCL

SP

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

SP

Y

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh
Stack Lower Address =

0100h

The stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a reset stack pointer instruction (RSP), the stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the stack pointer (called S) can be directly accessed by an LD
instruction.

Note: When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,

without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. The other registers are then stored in the next locations as shown in

Figure 8.

● When an interrupt is received, the SP is decremented and the context is pushed on the

stack.

● On return from interrupt, the SP is incremented and the context is popped from the

stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

Figure 8. Stack manipulation example

36/243 Doc ID 13829 Rev 1

ST72321xx-Auto Supply, reset and clock management

LOW VOLTAGE

DETECTOR

(LVD)

f

OSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

V

SS

EVD

V

DD

RESET SEQUENCE

MANAGER

(RSM)

OSC2

MAIN CLOCK

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REAL-TIME

CLOCK (MCC/RTC)

AVD

AVD AVD

LV D

RF

IE

WDG

RF

0

1

f

OSC

(option)

0

S

F

f

CPU

00

6 Supply, reset and clock management

6.1 Introduction

The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 9.

For more details, refer to the dedicated parametric section.

6.2 Main features

● Optional PLL for multiplying the frequency by 2 (not to be used with internal RC

oscillator)

● Reset Sequence Manager (RSM)

● Multi-oscillator Clock Management (MO)

– 5 crystal/ceramic resonator oscillators
– 1 internal RC oscillator

● System Integrity Management (SI)

– Main supply low voltage detection (LVD)
– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

supply or the EVD pin

Figure 9. Clock, reset and supply block diagram

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Supply, reset and clock management ST72321xx-Auto

0

1

PLL OPTION BIT

PLL x 2

f

OSC2

/ 2

f

OSC

6.3 Phase locked loop

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f
byte. If the PLL is disabled, then f

OSC2=fOSC

Caution: The PLL is not recommended for applications where timing accuracy is required (see

Section 19.5.5: PLL characteristics on page 198).

Figure 10. PLL block diagram

of 4 to 8 MHz. The PLL is enabled by option

OSC2

/2.

6.4 Multi-oscillator (MO)

The main clock of the ST7 can be generated by three different source types coming from the
multi-oscillator block:

● an external source

● 4 crystal or ceramic resonator oscillators

● an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in

Table 10. Refer to Section 19: Electrical characteristics for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
f

clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an

OSC

unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.

External clock source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.

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ST72321xx-Auto Supply, reset and clock management

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

C

L2

C

L1

OSC1 OSC2

ST7

Crystal/ceramic oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of four oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 21.1.1: Flash

configuration on page 223 for more details on the frequency ranges). In this mode of the

multi-oscillator, the resonator and the load capacitors have to be placed as close as possible
to the oscillator pins in order to minimize output distortion and start-up stabilization time.
The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator start-up phase.

Internal RC oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal
resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency
accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 10. ST7 clock sources

Hardware configuration

External clockCrystal/Ceramic resonatorsInternal RC oscillator

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Supply, reset and clock management ST72321xx-Auto

RESET

R

ON

V

DD

WATCHDOG RESET
LVD RESET

INTERNAL
RESET

PULSE

GENERATOR

Filter

6.5 Reset sequence manager (RSM)

6.5.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 11:

● External RESET source pulse

● Internal LVD RESET (low voltage detection)

● Internal WATCHDOG RESET

These sources act on the RESET

pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.

The basic RESET sequence consists of three phases as shown in Figure 12:

● Active phase depending on the RESET source

● 256 or 4096 CPU clock cycle delay (selected by option byte)

● RESET vector fetch

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

not programmed. For this reason, it is recommended to keep the RESET

pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see Section 21.1.1: Flash configuration on page 223).

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. Reset block diagram

40/243 Doc ID 13829 Rev 1

ST72321xx-Auto Supply, reset and clock management

RESET

ACTIVE PHASE

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

Figure 12. RESET sequence phases

6.5.2 Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 19.9: Control pin

characteristics on page 207for more details.

A RESET signal originating from an external source must have a duration of at least
t

h(RSTL)in

in order to be recognized (see Figure 13). This detection is asynchronous and

therefore the MCU can enter reset state even in Halt mode.

The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In

a noisy environment, it is recommended to follow the guidelines mentioned in Section 19:

Electrical characteristics.

If the external RESET
the signal on the RESET

pulse is shorter than t

w(RSTL)out

pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the
device RESET

pin acts as an output that is pulled low during at least t

6.5.3 External power-on RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f

frequency (see Section 19.3: Operating

OSC

conditions on page 188).

A proper reset signal for a slow rising V
RC network connected to the RESET

supply can generally be provided by an external

DD

pin.

6.5.4 Internal low voltage detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

● Power-on RESET

● Voltage drop RESET

The device RESET
V

DD<VIT-

(falling edge) as shown in Figure 13.

The LVD filters spikes on V

pin acts as an output that is pulled low when VDD<V

larger than t

DD

to avoid parasitic resets.

g(VDD)

(see short ext. Reset in Figure 13),

w(RSTL)out

.

is over

DD

(rising edge) or

IT+

Doc ID 13829 Rev 1 41/243

Supply, reset and clock management ST72321xx-Auto

V

DD

RUN

RESET PIN

EXTERNAL

WATCHDOG

Active Phase

V

IT+(LVD)

V

IT-(LVD)

t

h(RSTL)in

t

w(RSTL)out

RUN

t

h(RSTL)in

Active

WATCHDOG UNDERFLOW

t

w(RSTL)out

RUN RUN RUN

RESET

RESET
SOURCE

SHORT EXT.

RESET

LV D

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 T

CPU

)

VECTOR FETCH

t

w(RSTL)out

Phase

Active
Phase

Active

Phase

DELAY

6.5.5 Internal watchdog RESET

The RESET sequence generated by an internal Watchdog counter overflow is shown in

Figure 13.

Starting from the Watchdog counter underflow, the device RESET
is pulled low during at least t

Figure 13. RESET sequences

w(RSTL)out

pin acts as an output that

.

42/243 Doc ID 13829 Rev 1

ST72321xx-Auto Supply, reset and clock management

6.6 System integrity management (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

6.6.1 Low voltage detector (LVD)

The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a V
the power-down keeping the ST7 in reset.

reference value. This means that it secures the power-up as well as

IT-

The V

reference value for a voltage drop is lower than the V

IT-

reference value for power-

IT+

on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).

The LVD reset circuitry generates a reset when V

–V
–V

when VDD is rising

IT+

when VDD is falling

IT-

is below:

DD

The LVD function is illustrated in Figure 14.

The voltage threshold can be configured by option byte to be low, medium or high.

Provided the minimum V

value (guaranteed for the oscillator frequency) is above V

DD

MCU can only be in two modes:

– under full software control
– in static safe reset

In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.

During a low voltage detector reset, the RESET

pin is held low, thus permitting the MCU to

reset other devices.

Note: The LVD allows the device to be used without any external RESET circuitry.

If the medium or low thresholds are selected, the detection may occur outside the specified
operating voltage range. Below 3.8V, device operation is not guaranteed.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the V

supply voltage rises monotonously when the

DD

device is exiting from Reset, to ensure the application functions properly.

IT-

, the

Doc ID 13829 Rev 1 43/243

Supply, reset and clock management ST72321xx-Auto

V

DD

V

IT+

RESET

V

IT-

V

hys

Figure 14. Low voltage detector versus reset

6.6.2 Auxiliary voltage detector (AVD)

The auxiliary voltage detector function (AVD) is based on an analog comparison between a
V
voltage level (V
reference value for rising voltage in order to avoid parasitic detection (hysteresis).

IT-(AVD)

and V

IT+(AVD)

). The V

EVD

reference value and the VDD main supply or the external EVD pin

reference value for falling voltage is lower than the V

IT-

IT+

The output of the AVD comparator can be read directly by the application software through a
real-time status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte.

Monitoring the VDD main supply

This mode is selected by clearing the AVDS bit in the SICSR register.

The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see Section 21.1.1: Flash configuration on page 223).

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
V

IT+(AVD)

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 15.

The interrupt on the rising edge is used to inform the application that the V
is over.

If the voltage rise time t
selected by option byte), no AVD interrupt will be generated when V

If t

● two AVD interrupts will be received if the AVD interrupt is enabled before the V

● only one AVD interrupt will occur if the AVD interrupt is enabled after the V

or V

is greater than 256 or 4096 cycles

rv

threshold (AVDF bit toggles).

IT-(AVD)

is less than 256 or 4096 CPU cycles (depending on the reset delay

rv

DD

IT+(AVD)

threshold is reached: the first when the AVDIE bit is set, and the second when the
threshold is reached.

threshold is reached.

warning state

is reached.

IT+(AVD)

IT+(AVD)

44/243 Doc ID 13829 Rev 1

ST72321xx-Auto Supply, reset and clock management

V

DD

V

IT+(AVD)

V

IT-(AVD)

AVD F b it 0 0RESET VALUE

IF AVDIE bit = 1

V

hyst

AVD INTERRUPT
REQUEST

INTERRUPT PROCESS

INTERRUPT PROCESS

V

IT+(LVD)

V

IT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not
not yet in reset)

1

1

t

rv

VOLTAGE RISE TIME

Figure 15. Using the AVD to monitor V

(AVDS bit = 0)

DD

Monitoring a voltage on the EVD pin

This mode is selected by setting the AVDS bit in the SICSR register.

The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set.
This interrupt is generated on the rising and falling edges of the comparator output. This
means it is generated when either one of these two events occur:

● V

●

The EVD function is illustrated in Figure 16.

For more details, refer to Section 19: Electrical characteristics.

rises up to V

EVD

V

falls down to V

EVD

IT+(EVD)

IT-(EVD)

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Supply, reset and clock management ST72321xx-Auto

V

EVD

V

IT+(EVD)

V

IT-(EVD)

AVD F 0 01

IF AVDIE = 1

V

hyst

AVD INTERRUPT
REQUEST

INTERRUPT PROCESS

INTERRUPT PROCESS

Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1)

6.6.3 Low power modes

Table 11. Effect of low power modes on SI

Mode Effect

Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode.

Halt The SICSR register is frozen.

6.6.4 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

Table 12. AVD interrupt control/wake-up capability

Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt

AVD event AVDF AVDIE Yes No

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ST72321xx-Auto Supply, reset and clock management

6.6.5 System Integrity (SI) Control/Status register (SICSR)

SICSR Reset value: 000x 000x (00h)

76543210

AVDS AVDIE AVDF LVDRF

Reserved

RW RW RW RW - RW

Table 13. SICSR description

Bit Name Function

Voltage Detection selection

This bit is set and cleared by software. Voltage Detection is available only if the

7AVDS

LVD is enabled by option byte.
0: Voltage detection on V

DD

supply

1: Voltage detection on EVD pin

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated

6

AVD IE

when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled

Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to

5AVDF

Figure 15 and to Monitoring the VDD main supply on page 44 for additional

details.

or V

0: V

DD

1: VDD or V

EVD
EVD

over V
under V

IT+(AVD)

IT-(AVD)

threshold

threshold

LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

4 LVDRF

hardware (LVD reset) and cleared by software (writing zero). See Table 14: Reset

source flags for more details. When the LVD is disabled by OPTION BYTE, the

LVDRF bit value is undefined.

WDGRF

3:1 - Reserved, must be kept cleared.

Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It

0 WDGRF

is set by hardware (watchdog reset) and cleared by software (writing zero) or an
LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given in

Ta ble 1 4 .

Table 14. Reset source flags

Reset sources LVDRF WDGRF

External RESET

pin 0 0

Watchdog 0 1

LV D 1 X

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Supply, reset and clock management ST72321xx-Auto

Application notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the
LVDRF flag remains set to keep trace of the original failure.

In this case, software can detect a watchdog reset but cannot detect an external reset.

Caution: When the LVD is not activated with the associated option byte, the WDGRF flag cannot be

used in the application.

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ST72321xx-Auto Interrupts

7 Interrupts

7.1 Introduction

The ST7 enhanced interrupt management provides the following features:

● Hardware interrupts

● Software interrupt (TRAP)

● Nested or concurrent interrupt management with flexible interrupt priority and level

management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non-maskable events: RESET, TRAP
– 1 maskable Top Level event: TLI

This interrupt management is based on:

● Bit 5 and bit 3 of the CPU CC register (I1:0)

● Interrupt software priority registers (ISPRx)

● Fixed interrupt vector addresses located at the high addresses of the memory map

(FFE0h to FFFFh) sorted by hardware priority order

This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.

7.2 Masking and processing flow

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see Ta bl e

15). The processing flow is shown in Figure 17.

When an interrupt request has to be serviced:

● Normal processing is suspended at the end of the current instruction execution.

● The PC, X, A and CC registers are saved onto the stack.

● I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx

registers of the serviced interrupt vector.

● The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to Table 20: Interrupt

mapping for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

Doc ID 13829 Rev 1 49/243

Interrupts ST72321xx-Auto

“IRET”

RESTORE PC, X, A, CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

TRAP

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Y

N

Y

N

Y

N

Interrupt has the same or a

lower software priority

THE INTERRUPT
STAYS PENDING

than current one

Interrupt has a higher

software priority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Table 15. Interrupt software priority levels

Interrupt software priority Level I1 I0

Level 0 (main)

Low

10

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable) 1 1

High

Figure 17. Interrupt processing flowchart

Servicing pending interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:

● the highest software priority interrupt is serviced,

● if several interrupts have the same software priority then the interrupt with the highest

hardware priority is serviced first.

Figure 18 describes this decision process.

Figure 18. Priority decision process flowchart

50/243 Doc ID 13829 Rev 1

ST72321xx-Auto Interrupts

When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.

Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous

process to succeed with only one interrupt.

2 TLI, RESET and TRAP can be considered as having the highest software priority in the

decision process.

Different interrupt vector sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (RESET, TRAP) and the maskable type (external or from internal peripherals).

Non-maskable sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 17). After stacking the PC, X, A and CC registers (except for RESET), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.

● TRAP (non-maskable software interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be
serviced according to the flowchart in Figure 17.

Caution: TRAP can be interrupted by a TLI.

● RESET

The RESET source has the highest priority in the ST7. This means that the first current
routine has the highest software priority (level 3) and the highest hardware priority.

See Section 6.5: Reset sequence manager (RSM) on page 40 for more details.

Maskable sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.

● TLI (top level hardware interrupt)

Caution: This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. It

will be serviced according to the flowchart in Figure 17 as a trap.
A TRAP instruction must not be used in a TLI service routine.

● External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External
interrupt sensitivity is software selectable through the External Interrupt Control register
(EICR).

External interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.

● Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from Halt mode except those
mentioned in Table 20: Interrupt mapping. A peripheral interrupt occurs when a specific

Doc ID 13829 Rev 1 51/243

Interrupts ST72321xx-Auto

MAIN

IT4

IT2

IT1

TRAP

IT1

MAIN

IT0

I1

HARDWARE PRIORITY

SOFTWARE

3

3

3

3

3

3/0

3

11

11

11

11

11

11 / 10

11

RIM

IT2

IT1

IT4

TRAP

IT3

IT0

IT3

I0

10

PRIORITY
LEVEL

USED STACK = 10 BYTES

flag is set in the peripheral status registers and if the corresponding enable bit is set in
the peripheral control register.

The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.

Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be

serviced) will therefore be lost if the clear sequence is executed.

7.3 Interrupts and low power modes

All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt/Active Halt” in Table 20: Interrupt mapping). When several pending
interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt
with “exit from Halt mode” capability and it is selected through the same decision process
shown in Figure 18.

Note: If an interrupt that is not able to exit from Halt mode is pending with the highest priority when

exiting Halt mode, this interrupt is serviced after the first one serviced.

7.4 Concurrent and nested management

The following Figure 19 and Figure 20 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in Figure 20. The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.

Warning: A stack overflow may occur without notifying the software of

the failure.

Figure 19. Concurrent interrupt management

52/243 Doc ID 13829 Rev 1

ST72321xx-Auto Interrupts

MAIN

IT2

TRAP

MAIN

IT0

IT2

IT1

IT4

TRAP

IT3

IT0

HARDWARE PRIORITY

3

2

1

3

3

3/0

3

11

00

01

11

11

11

RIM

IT1

IT4

IT4

IT1

IT2

IT3

I1

I0

11 / 10

10

SOFTWARE
PRIORITY
LEVEL

USED STACK = 20 BYTES

Figure 20. Nested interrupt management

7.5 Interrupt register description

7.5.1 CPU CC register interrupt bits

CPU CC Reset value: 111x 1010 (xAh)

76543210

11I1 H I0 NZC

RW RW RW RW RW RW

Table 16. CPU CC register interrupt bits description

Bit Name Function

5I1

3I0 Interrupt Software Priority 0

These two bits indicate the current interrupt software priority (see Ta ble 1 7) and are
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 19: Interrupt dedicated instruction set).

Interrupt Software Priority 1

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Interrupts ST72321xx-Auto

Table 17. Interrupt software priority levels

Interrupt software priority Level I1 I0

Level 0 (main)

Level 1 0 1

Level 2 0 0

(1)

Level 3 (= interrupt disable

1. TLI, TRAP and RESET events can interrupt a level 3 program.

)

7.5.2 Interrupt software priority registers (ISPRx)

These four registers are read/write, with the exception of bits 7:4 of ISPR3, which are read
only.

ISPRx Reset value: 1111 1111 (FFh)

76543210

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

● Each interrupt vector (except RESET and TRAP) has corresponding bits in these

registers where its own software priority is stored. This correspondence is shown in the
following Tab l e 1 8.

Table 18. Interrupt priority bits

Low

High

10

11

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

1. Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant

in the interrupt process management.

● Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1

and I0 bits in the CC register.

● Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value

is kept (Example: previous = CFh, write = 64h, result = 44h).

54/243 Doc ID 13829 Rev 1

(1)

ST72321xx-Auto Interrupts

The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the
I1 and I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior

has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).

Table 19. Interrupt dedicated instruction set

Instruction New description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0

IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C

JRM Jump if I1:0 = 11 (level 3) I1:0 = 11 ?

JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?

POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C

RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0

SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1

TRAP Software trap Software NMI 1 1

WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI

instructions change the current software priority up to the next IRET instruction or one of the
previously mentioned instructions.

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Interrupts ST72321xx-Auto

Table 20. Interrupt mapping

No.

Source

block

RESET Reset

Description

Register

label

Priority

order

Exit
from

Halt

(1)

Address

vector

yes FFFEh-FFFFh

N/A

TRAP Software interrupt no FFFCh-FFFDh

0 TLI External top level interrupt EICR yes FFFAh-FFFBh

1 MCC/RTC Main clock controller time base interrupt MCCSR

2 ei0 External interrupt port A3..0

Higher

priority

yes FFF8h-FFF9h

yes FFF6h-FFF7h

3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h

N/A

4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h

5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h

6 Not used FFEEh-FFEFh

(2)

7 SPI SPI peripheral interrupts SPICSR yes

FFECh-FFEDh

8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh

9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h

10 SCI SCI peripheral interrupts SCISR

11 AVD Auxiliary voltage detector interrupt SICSR no FFE4h-FFE5h

12 I2C I2C peripheral interrupts

(see

peripheral)

Lower

priority

13 PWM ART PWM ART interrupt ARTCSR yes

1. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.

2. Exit from HALT possible when SPI is in slave mode.

3. Exit from HALT possible when PWM ART is in external clock mode.

no FFE6h-FFE7h

no FFE2h-FFE3h

(3)

FFE0h-FFE1h

56/243 Doc ID 13829 Rev 1

ST72321xx-Auto Interrupts

7.6 External interrupts

7.6.1 I/O port interrupt sensitivity

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 21). This control allows to have up to four fully independent external
interrupt source sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

● Falling edge

● Rising edge

● Falling and rising edge

● Falling edge and low level

● Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.

Doc ID 13829 Rev 1 57/243

Interrupts ST72321xx-Auto

IS10 IS11

EICR

SENSITIVITY

CONTROL

PBOR.3

PBDDR.3

IPB BIT

PB3

ei2 INTERRUPT SOURCE

PORT B [3:0] INTERRUPTS

PB3
PB2

PB1
PB0

IS10 IS11

EICR

SENSITIVITY

CONTROL

PBOR.7

PBDDR.7

PB7

ei3 INTERRUPT SOURCE

PORT B [7:4] INTERRUPTS

PB7
PB6

PB5
PB4

IS20 IS21

EICR

SENSITIVITY

CONTROL

PAOR.3

PADDR.3

IPA BIT

PA3

ei0 INTERRUPT SOURCE

PORT A [3:0] INTERRUPTS

PA3
PA2

PA1
PA0

IS20 IS21

EICR

SENSITIVITY

CONTROL

PFOR.2

PFDDR.2

PF2

ei1 INTERRUPT SOURCE

PORT F [2:0] INTERRUPTS

PF2
PF1

PF0

Figure 21. External interrupt control bits

58/243 Doc ID 13829 Rev 1

ST72321xx-Auto Interrupts

7.6.2 External interrupt control register (EICR)

EICR Reset value: 0000 0000 (00h)

76543210

IS1[1:0] IPB IS2[1:0] IPA TLIS TLIE

RW RW RW RW RW RW

Table 21. EICR register description

Bit Name Function

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following

7:6 IS1[1:0]

5IPB

external interrupts:

- ei2 (port B3..0) (see Ta bl e 2 2 )

- ei3 (port B7..4) (see Ta bl e 2 3 )
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).

Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion

4:3 IS2[1:0]

2IPA

1TLIS

0TLIE

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:

- ei0 (port A3..0) (see Ta bl e 2 4 )

- ei1 (port F2..0) (see Ta b le 2 5 )
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).

Interrupt polarity for port A

This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion

TLI sensitivity

This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by
software only when TLIE bit is cleared.
0: Falling edge
1: Rising edge

TLI enable

This bit allows to enable or disable the TLI capability on the dedicated pin. It is set
and cleared by software.
0: TLI disabled
1: TLI enabled

Note: A parasitic interrupt can be generated when clearing the TLIE bit.

Doc ID 13829 Rev 1 59/243

Interrupts ST72321xx-Auto

Table 22. Interrupt sensitivity - ei2 (port B3..0)

External interrupt sensitivity

IS11 IS10

IPB bit = 0 IPB bit = 1

0 0 Falling edge and low level Rising edge and high level

0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

Table 23. Interrupt sensitivity - ei3 (port B7..4)

IS11 IS10 External interrupt sensitivity

0 0 Falling edge and low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

Table 24. Interrupt sensitivity - ei0 (port A3..0)

External interrupt sensitivity

IS21 IS20

IPA bit = 0 IPA bit = 1

0 0 Falling edge and low level Rising edge and high level

0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

Table 25. Interrupt sensitivity - ei1 (port F2..0)

IS21 IS20 External interrupt sensitivity

0 0 Falling edge and low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

60/243 Doc ID 13829 Rev 1

ST72321xx-Auto Interrupts

Table 26. Nested interrupts register map and reset values

Address (Hex.)Register label76543210

ei1 ei0 MCC TLI

0024h

ISPR0
Reset value

I1_3

1

I0_3

1

I1_2

1

I0_2

1

I1_1

1

I0_1

111

SPI Reserved ei3 ei2

0025h

ISPR1
Reset value

I1_7

1

I0_7

1

I1_6

1

I0_6

1

I1_5

1

I0_5

1

I1_4

1

I0_4

1

AVD SCI TIMER B TIMER A

0026h

ISPR2
Reset value

I1_111I0_111I1_101I0_101I1_9

1

I0_9

1

I1_8

1

I0_8

1

PWMART I2C

0027h

0028h

ISPR3
Reset value 1 1 1 1

EICR
Reset value

IS11

0

IS10

0

IPB

0

IS21

I1_131I0_131I1_121I0_12

1

IS20

0

0

IPA

0

TLIS

0

TLIE

0

Doc ID 13829 Rev 1 61/243

Power saving modes ST72321xx-Auto

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

HALT

8 Power saving modes

8.1 Introduction

To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 22): Slow, Wait (Slow
Wait), Active Halt and Halt.

After a RESET the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f

From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.

Figure 22. Power saving mode transitions

OSC2

).

8.2 Slow mode

This mode has two targets:

● To reduce power consumption by decreasing the internal clock in the device,

● To adapt the internal clock frequency (f

Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (f

In this mode, the master clock frequency (f
and peripherals are clocked at this lower frequency (f

Note: Slow Wait mode is activated when entering the Wait mode while the device is already in

Slow mode.

62/243 Doc ID 13829 Rev 1

) to the available supply voltage.

CPU

) can be divided by 2, 4, 8 or 16. The CPU

OSC2

CPU

).

CPU

).

ST72321xx-Auto Power saving modes

00 01

SMS

CP1:0

f

CPU

NEW SLOW

NORMAL RUN MODE

MCCSR

FREQUENCY

REQUEST

REQUEST

f

OSC2

f

OSC2/2

f

OSC2/4

f

OSC2

Figure 23. Slow mode clock transitions

8.3 Wait mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU.

This power saving mode is selected by calling the ‘WFI’ instruction.

All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in Wait mode until an interrupt or RESET occurs, whereupon the Program Counter
branches to the starting address of the interrupt or Reset service routine.

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.

Refer to the following Figure 24.

Doc ID 13829 Rev 1 63/243

Power saving modes ST72321xx-Auto

WFI INSTRUCTION

RESET

INTERRUPT

Y

N

N

Y

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON
ON

10

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON

OFF

10

ON

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON
ON

XX

(1)

ON

256 OR 4096 CPU CLOCK

CYCLE DELAY

Figure 24. Wait mode flowchart

1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.

64/243 Doc ID 13829 Rev 1

ST72321xx-Auto Power saving modes

8.4 Active Halt and Halt modes

Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register) as shown in Tabl e 2 7 .

Table 27. MCC/RTC low power mode selection

MCCSR OIE bit Power saving mode entered when HALT instruction is executed

0Halt

1 Active Halt

8.4.1 Active Halt mode

Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see Section 12.3: ART registers on page 93 for
more details on the MCCSR register).

The MCU can exit Active Halt mode on reception of an MCC/RTC interrupt or a RESET.
When exiting Active Halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay
occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector
which woke it up (see Figure 26).

When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).

The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),

entering Active Halt mode while the Watchdog is active does not generate a RESET.

This means that the device cannot spend more than a defined delay in this power saving
mode.

Caution: When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register

must not be cleared before t

after the interrupt occurs (t

DELAY

= 256 or 4096 t

DELAY

CPU

delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining
t

DELAY

period.

Doc ID 13829 Rev 1 65/243

Power saving modes ST72321xx-Auto

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

(1)

RESET

OR

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[MCCSR.OIE = 1]

HALT INSTRUCTION

RESET

Y

N

N

Y

CPU

OSCILLATOR
PERIPHERALS

(1)

I[1:0] BITS

ON

OFF

10

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON

OFF

XX

(2)

ON

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON
ON

XX

(2)

ON

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE = 1)

INTERRUPT

(3)

Figure 25. Active Halt timing overview

1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET.

Figure 26. Active Halt mode flowchart

1. Peripheral clocked with an external clock source can still be active.

2. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and restored when the CC register is
popped.

3. In Flash devices only the MCC/RTC interrupt can exit the MCU from Active Halt mode.

66/243 Doc ID 13829 Rev 1

ST72321xx-Auto Power saving modes

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

OR

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[MCCSR.OIE = 0]

8.4.2 Halt mode

The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see Section 11: Main clock controller with real-time clock and

beeper (MCC/RTC) on page 82 for more details on the MCCSR register).

The MCU can exit Halt mode on reception of either a specific interrupt (see Section Table

20.: Interrupt mapping on page 56) or a RESET. When exiting Halt mode by means of a

RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU
cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching the reset vector which woke it up (see

Figure 28).

When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog RESET (see Section 21.1.1: Flash

configuration on page 223 for more details).

Figure 27. Halt timing overview

Doc ID 13829 Rev 1 67/243

Power saving modes ST72321xx-Auto

HALT INSTRUCTION

RESET

INTERRUPT

(3)

Y

N

N

Y

CPU

OSCILLATOR
PERIPHERALS

(2)

I[1:0] BITS

OFF
OFF

10

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON

OFF

XX

(4)

ON

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON
ON

XX

(4)

ON

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

(1)

0

WATCHDOG

RESET

1

(MCCSR.OIE = 0)

CYCLE

Figure 28. Halt mode flowchart

1. WDGHALT is an option bit. See Section 21.1.1: Flash configuration on page 223 for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 20: Interrupt mapping for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.

68/243 Doc ID 13829 Rev 1

ST72321xx-Auto Power saving modes

Halt mode recommendations

● Make sure that an external event is available to wake up the microcontroller from Halt

mode.

● When using an external interrupt to wake up the microcontroller, re-initialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.

● For the same reason, reinitialize the level sensitiveness of each external interrupt as a

precautionary measure.

● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction

due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.

● As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,

the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).

Related documentation

ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke (AN 980)

How to Minimize the ST7 Power Consumption (AN1014)

Using an active RC to wake up the ST7LITE0 from power saving mode (AN1605)

Doc ID 13829 Rev 1 69/243

I/O ports ST72321xx-Auto

9 I/O ports

9.1 Introduction

The I/O ports offer different functional modes:

● transfer of data through digital inputs and outputs

and for specific pins:

● external interrupt generation

● alternate signal input/output for the on-chip peripherals.

An I/O port contains up to eight pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.

9.2 Functional description

Each port has two main registers:

● Data Register (DR)

● Data Direction Register (DDR)

and one optional register:

● Option Register (OR)

Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers (bit X corresponding to pin X of the port). The same correspondence is used for
the DR register.

The following description takes into account the OR register (for specific ports which do not
provide this register refer to Section 9.3: I/O port implementation on page 74). The generic
I/O block diagram is shown in Figure 29.

9.2.1 Input modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.

2 When switching from input to output mode, the DR register has to be written first to drive the

correct level on the pin as soon as the port is configured as an output.

3 Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this

might corrupt the DR content for I/Os configured as input.

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.

70/243 Doc ID 13829 Rev 1

ST72321xx-Auto I/O ports

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several input pins are selected simultaneously as
interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.

9.2.2 Output modes

The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain. The DR register value and output pin status are shown in the
following Ta bl e 2 8 .

Table 28. I/O output mode selection

DR Push-pull Open-drain

0V

1VDDFloating

SS

V

SS

9.2.3 Alternate functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open-drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate

peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.

Doc ID 13829 Rev 1 71/243

I/O ports ST72321xx-Auto

DR

DDR

OR

DATA BUS

PAD

V

DD

ALTERNATE
ENABLE

ALTERNATE
OUTPUT

1

0

OR SEL

DDR SEL

DR SEL

PULL-UP
CONDITION

P-BUFFER
(see table below)

N-BUFFER

PULL-UP
(see table below)

1

0

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

V

DD

DIODES
(see table below)

EXTERNAL

SOURCE (eix)

INTERRUPT

CMOS
SCHMITT
TRIGGER

REGISTER
ACCESS

Figure 29. I/O port general block diagram

Table 29. I/O port mode options

Configuration mode Pull-up P-buffer

Input

Output

1. The diode to VDD is not implemented in the true open-drain pads. A local protection between the pad and
V

Legend:

72/243 Doc ID 13829 Rev 1

Floating with/without Interrupt Off

Pull-up with/without Interrupt On

Push-pull

Open-drain (logic level) Off

True open-drain NI NI NI

is implemented to protect the device against positive stress.

SS

Off - Implemented not activated
On - Implemented and activated
NI - Not implemented

Diodes

to V

DD

Off

On

On

Off

(1)

to V

On

SS

ST72321xx-Auto I/O ports

CONDITION

PA D

V

DD

R

PU

EXTERNAL INTERRUPT

DATA BUS

PULL-UP

INTERRUPT

DR REGISTER ACCESS

W

R

SOURCE (ei

x

)

DR

REGISTER

CONDITION

ALTERNATE INPUT

NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS

ANALOG INPUT

PA D

R

PU

DATA BUS

DR

DR REGISTER ACCESS

R/W

V

DD

ALTERNATEALTERNATE

ENABLE OUTPUT

REGISTER

NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS

PA D

R

PU

DATA BUS

DR

DR REGISTER ACCESS

R/W

V

DD

ALTERNATEALTERNATE

ENABLE OUTPUT

REGISTER

NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS

Table 30. I/O port configurations

(1)

Input

(2)

Hardware configuration

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate

Open-drain output

(2)

Push-pull output

register will read the alternate function output status.

function reads the pin status given by the DR register content.

Doc ID 13829 Rev 1 73/243

I/O ports ST72321xx-Auto

01

floating/pull-up

interrupt

INPUT

00

floating

(reset state)

INPUT

10

open-drain

OUTPUT

11

push-pull

OUTPUT

XX = DDR, OR

Caution: The alternate function must not be activated as long as the pin is configured as input with

interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.

Warning: The analog input voltage level must be within the limits

stated in the absolute maximum ratings.

9.3 I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open-drain.

Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 30.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.

Figure 30. Interrupt I/O port state transitions

The I/O port register configurations are summarized in the following table.

Table 31. I/O port configuration

Input (DDR = 0) Output (DDR = 1)

Port Pin name

OR = 0 OR = 1 OR = 0 OR = 1

PA7:6 floating true open-drain

Por t A

PA5:4 floating pull-up open-drain push-pull

PA3 floating floating interrupt open-drain push-pull

PA2:0 floating pull-up interrupt open-drain push-pull

74/243 Doc ID 13829 Rev 1

ST72321xx-Auto I/O ports

Table 31. I/O port configuration (continued)

Input (DDR = 0) Output (DDR = 1)

Port Pin name

OR = 0 OR = 1 OR = 0 OR = 1

Por t B

PB7, PB3 floating floating interrupt open-drain push-pull

PB6:5, PB4, PB2:0 floating pull-up interrupt open-drain push-pull

Port C PC7:0 floating pull-up open-drain push-pull

Port D PD7:0 floating pull-up open-drain push-pull

PE7:3, PE1:0 floating pull-up open drain push-pull

Por t E

PE2 (Flash devices) pull-up input only

PE2 (ROM devices) floating open drain push-pull

PF7:3 floating pull-up open-drain push-pull

Por t F

PF2 floating floating interrupt open-drain push-pull

PF1:0 floating pull-up interrupt open-drain push-pull

9.4 Low power modes

Table 32. Effect of low power modes on I/O ports

Mode Effect

Wait No effect on I/O ports. External interrupts cause the device to exit from Wait mode.

Halt No effect on I/O ports. External interrupts cause the device to exit from Halt mode.

9.5 Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).

Table 33. I/O port interrupt control/wake-up capability

Interrupt event Event flag

External interrupt on selected
external event

Table 34. I/O port register map and reset values

Address (Hex.)Register label76543210

Reset value of all I/O port registers00000000

0000h PADR

0002h PAOR

Enable

control bit

Exit from

Wait

Exit from

Halt

- DDRx, ORx Yes Yes

MSB LSB0001h PADDR

Doc ID 13829 Rev 1 75/243

I/O ports ST72321xx-Auto

Table 34. I/O port register map and reset values (continued)

Address (Hex.)Register label76543210

Reset value of all I/O port registers00000000

0003h PBDR

MSB LSB0004h PBDDR

0005h PBOR

0006h PCDR

MSB LSB0007h PCDDR

0008h PCOR

0009h PDDR

MSB LSB000Ah PDDDR

000Bh PDOR

000Ch PEDR

MSB LSB000Dh PEDDR

000Eh PEOR

000Fh PFDR

MSB LSB0010h PFDDR

0011h PFOR

Related documentation

SPI Communication between ST7 and EEPROM (AN 970)

S/W implementation of I2C bus master (AN1045)

Software LCD driver (AN1048)

76/243 Doc ID 13829 Rev 1

ST72321xx-Auto Watchdog timer (WDG)

10 Watchdog timer (WDG)

10.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.

10.2 Main features

● Programmable free-running downcounter

● Programmable reset

● Reset (if watchdog activated) when the T6 bit reaches zero

● Optional reset on HALT instruction (configurable by option byte)

● Hardware Watchdog selectable by option byte

10.3 Functional description

The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is
decremented every 16384 f
be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the RESET
low for typically 30µs.

The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: It counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:

– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments which represents the time delay

before the watchdog produces a reset (see Figure 32: Approximate timeout

duration). The timing varies between a minimum and a maximum value due to the

unknown status of the prescaler when writing to the WDGCR register (see

Figure 33).

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).

OSC2

cycles (approx.), and the length of the timeout period can

pin

If the watchdog is activated, the HALT instruction will generate a Reset.

Doc ID 13829 Rev 1 77/243

Watchdog timer (WDG) ST72321xx-Auto

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

f

OSC2

T6 T0

WDG PRESCALER

WATCHDOG CONTROL REGISTER (WDGCR)

DIV 4

T1T2T3T4T5

12-BIT MCC

RTC COUNTER

MSB

LSB

DIV 64

0611

MCC/RTC

TB[1:0] bits
(MCCSR
Register)

5

CNT Value (hex.)

Watchdog timeout (ms) @ 8 MHz f

OSC2

3F

00

38

128

1.5 65

30

28

20

18

10

08

503418 82 98 114

Figure 31. Watchdog block diagram

10.4 How to program the watchdog timeout

Figure 32 shows the linear relationship between the 6-bit value to be loaded in the

Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 33.

Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 32. Approximate timeout duration

78/243 Doc ID 13829 Rev 1

ST72321xx-Auto Watchdog timer (WDG)

WHERE:

t

min0

= (LSB + 128) x 64 x t

OSC2

t

max0

= 16384 x t

OSC2

t

OSC2

= 125ns if f

OSC2

=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

To calculate the minimum Watchdog Timeout (t

min

):

IF THEN

ELSE

To calculate the maximum Watchdog Timeout (t

max

):

IF THEN

ELSE

Note: In the above formulae, division results must be rounded down to the next integer value.
Example:

With 2ms timeout selected in MCCSR register

TB1 bit

(MCCSR reg.)

TB0 bit

(MCCSR reg.)

Selected MCCSR

timebase

MSB LSB

0 0 2ms 4 59
0 1 4ms 8 53
1 0 10ms 20 35
1 1 25ms 49 54

Value of T[5:0] bits in

WDGCR register (Hex.)

Min. Watchdog

Timeout (ms)

t

min

Max. Watchdog

Timeout (ms)

t

max

00 1.496 2.048
3F 128 128.552

CNT

MSB

4

-------------

<

t

mintmin0

16384 CN T t

osc2

+=

t

mintmin0

16384 CNT

4CNT

MSB

-----------------

–





 192 LS B+64

4CNT

MSB

-----------------

+ t

osc2

+=

CNT

MSB

4

-------------



t

maxtmax0

16384 CN T t

osc2

+=

t

maxtmax0

16384 CNT

4CNT

MSB

-----------------

–





 192 LSB+64

4CNT

MSB

-----------------

+ t

osc2

+=

Figure 33. Exact timeout duration (t

min

and t

max

)

Doc ID 13829 Rev 1 79/243

Watchdog timer (WDG) ST72321xx-Auto

10.5 Low power modes

Table 35. Effect of low power modes on WDG

Mode Effect

Slow No effect on Watchdog

Wait No effect on Watchdog

OIE bit in

MCCSR
register

00

Halt

0 1 A reset is generated.

1x

WDGHALT

bit in

Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode.
The Watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
until the MCU receives an external interrupt or a reset.

If an external interrupt is received, the Watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the Watchdog is disabled (reset state) unless Hardware
Watchdog is selected by option byte. For application
recommendations see Section 10.7 below.

No reset is generated. The MCU enters Active Halt mode. The
Watchdog counter is not decremented. It stop counting. When
the MCU receives an oscillator interrupt or external interrupt,
the Watchdog restarts counting immediately. When the MCU
receives a reset the Watchdog restarts counting after 256 or
4096 CPU clocks.

10.6 Hardware watchdog option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 21.1.1:

Flash configuration on page 223.

10.7 Using Halt mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.

10.8 Interrupts

None.

80/243 Doc ID 13829 Rev 1

ST72321xx-Auto Watchdog timer (WDG)

10.9 Register description

10.9.1 Control register (WDGCR)

WDGCR Reset value: 0111 1111 (7Fh)

76543210

WDGA T[6:0]

RW RW

Table 36. WDGCR register description

Bit Name Function

Activation bit

This bit is set by software and only cleared by hardware after a reset. When

7WDGA

6:0 T[6:0]

Table 37. Watchdog timer register map and reset values

WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

7-bit counter (MSB to LSB)

These bits contain the value of the watchdog counter. It is decremented every 16384
f

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6

OSC2

becomes cleared).

Address

(Hex.)

002Ah

Register

label

WDGCR
Reset Value

76543210

WDGA0T6

1

T5

T4

1

1

T3

T2

1

1

T1

T0

1

1

Doc ID 13829 Rev 1 81/243

Main clock controller with real-time clock and beeper (MCC/RTC) ST72321xx-Auto

11 Main clock controller with real-time clock and beeper

(MCC/RTC)

11.1

11.2

11.3

Caution:

Introduction

The Main Clock Controller consists of three different functions:

●

a programmable CPU clock prescaler

●

a clock-out signal to supply external devices

●

a real-time clock timer with interrupt capability

Each function can be used independently and simultaneously.

Programmable CPU clock prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 62
for more details).

The prescaler selects the f
MCCSR register: CP[1:0] and SMS.

main clock frequency and is controlled by three bits in the

CPU

Clock-out capability

The clock-out capability is an alternate function of an I/O port pin that outputs a f
drive external devices. It is controlled by the MCO bit in the MCCSR register.

When selected, the clock out pin suspends the clock during Active Halt mode.

CPU

clock to

11.4

11.5

82/243 Doc ID 13829 Rev 1

Real-time clock timer (RTC)

The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on f
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.

When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active Halt mode when the
HALT instruction is executed. See Section 8.4: Active Halt and Halt modes on page 65 for
more details.

Beeper

The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).

are available.

OSC2

ST72321xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)

DIV 2, 4, 8, 16

MCC/RTC INTERRUPT

SMSCP1 CP0 TB1 TB0 OIE OIF

CPU CLOCK

MCCSR

12-BIT MCC RTC

COUNTER

TO CPU AND

PERIPHERALS

f

OSC2

f

CPU

MCO

MCO

BC1 BC0

MCCBCR

BEEP

SELECTION

BEEP SIGNAL

1

0

TO

WATCHDOG

TIMER

DIV 64

Figure 34.

Main clock controller (MCC/RTC) block diagram

11.6

11.7

Low power modes

Table 38. Effect of low power modes on MCC/RTC

Mode Effect

Wait

Active Halt

No effect on MCC/RTC peripheral.
MCC/RTC interrupt causes the device to exit from Wait mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt causes the device to exit from Active Halt mode.

MCC/RTC counter and registers are frozen.

Halt

MCC/RTC operation resumes when the MCU is woken up by an interrupt with
“exit from HALT” capability.

Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).

Table 39. MCC/RTC interrupt control/wake-up capability

Time base overflow event OIF OIE Yes No

1. The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.

Interrupt event Event flag

Enable

control bit

Exit from

Wait

Exit from

Halt

(1)

Doc ID 13829 Rev 1 83/243

Main clock controller with real-time clock and beeper (MCC/RTC) ST72321xx-Auto

11.8

Main clock controller registers

11.8.1 MCC control/status register (MCCSR)

MCCSR Reset value: 0000 0000 (00h)

76543210

MCO CP[1:0] SMS

RW RW RW RW RW RW

Table 40. MCCSR register description

Bit Name Function

Main clock out selection

This bit enables the MCO alternate function on the PF0 I/O port. It is set and
cleared by software.

7MCO

6:5 CP[1:0]

4SMS

0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (f

Note: To reduce power consumption, the MCO function is not active in Active Halt
mode.

CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow
modes. Their action is conditioned by the setting of the SMS bit. These two bits are
set and cleared by software.
00: f
01: f
10: f
11: f

in Slow mode = f

CPU

in Slow mode = f

CPU

in Slow mode = f

CPU

in Slow mode = f

CPU

OSC2
OSC2
OSC2
OSC2

/2
/4
/8
/16

Slow mode select

This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See

Section 8.2: Slow mode on page 62

= f

CPU

OSC2

is given by CP1, CP0

CPU

real-time clock and beeper (MCC/RTC) for more details.

OIE OIF

on I/O port)

CPU

TB[1:0]

and Chapter 11: Main clock controller with

Time base control

These bits select the programmable divider time base. They are set and cleared by

3:2

TB[1:0]

software (see
A modification of the time base is taken into account at the end of the current period

Ta ble 4 1 )

.

(previously set) to avoid an unwanted time shift. This allows to use this time base
as a real-time clock.

Oscillator interrupt enable

This bit set and cleared by software.
0: Oscillator interrupt disabled

1OIE

1: Oscillator interrupt enabled
This interrupt can be used to exit from Active Halt mode.
When this bit is set, calling the ST7 software HALT instruction enters the Active Halt
power saving mode

.

84/243 Doc ID 13829 Rev 1

ST72321xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)

Table 40. MCCSR register description (continued)

Bit Name Function

Oscillator interrupt flag

This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time

0OIF

Table 41. Time base selection

Counter prescaler

16000 4ms 2ms 0 0

32000 8ms 4ms 0 1

80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the MCCSR
register to avoid unintentionally clearing the OIF bit.

Time base

TB1 TB0

=4MHz f

f

OSC2

OSC2

=8MHz

11.8.2 MCC beep control register (MCCBCR)

MCCBCR Reset value: 0000 0000 (00h)

76543210

Reserved BC[1:0]

-RW

Table 42. MCCBCR register description

Bit Name Function

7:2 - Reserved, must be kept cleared.

1:0 BC[1:0]

Table 43. Beep frequency selection

BC1 BC0 Beep mode with f

00 Off

0 1 ~2 kHz

1 0 ~1 kHz

11 ~500Hz

Beep control

These 2 bits select the PF1 pin beep capability (see Ta ble 4 3 ).

=8MHz

OSC2

~50% duty cycle

Output

Beep signal

The beep output signal is available in Active Halt mode but has to be disabled to reduce
consumption.

Doc ID 13829 Rev 1 85/243

Main clock controller with real-time clock and beeper (MCC/RTC) ST72321xx-Auto

Table 44. Main clock controller register map and reset values

Address (Hex.) Register label 76543210

002Bh

002Ch

002Dh

SICSR
Reset value

MCCSR
Reset value

MCCBCR
Reset value000000

AVD S0AVD IE0AVD F0LV DR F

x000

MCO

0

CP1

0

CP0

0

SMS

0

TB1

0

TB0

0

OIE

0

BC1

0

WDGRF

x

OIF

0

BC0

0

86/243 Doc ID 13829 Rev 1

ST72321xx-Auto PWM auto-reload timer (ART)

OVF INTERRUPT

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

ARTCSR

f

INPUT

PWMx

PORT

FUNCTION

ALTERNATE

OCRx

COMPARE

REGISTER

PROGRAMMABLE

PRESCALER

ARR

REGISTER

ICRx

REGISTER

LOAD

OPx

POLARITY
CONTROL

OEx

PWMCR

MUX

f

CPU

DCRx

REGISTER

LOAD

f

COUNTER

ARTCLK

f

EXT

ARTICx

ICFxICSx

ICCSR

LOAD

ICx INTERRUPT

ICIEx

INPUT CAPTURE

CONTROL

8-BIT COUNTER

(CAR REGISTER)

12 PWM auto-reload timer (ART)

12.1 Introduction

The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto­reload counter with compare/capture capabilities and of a 7-bit prescaler clock source.

These resources allow five possible operating modes:

● Generation of up to 4 independent PWM signals

● Output compare and Time base interrupt

● Up to 2 input capture functions

● External event detector

● Up to 2 external interrupt sources

The three first modes can be used together with a single counter frequency.

The timer can be used to wake up the MCU from Wait and Halt modes.

Figure 35. PWM auto-reload timer block diagram

Doc ID 13829 Rev 1 87/243

PWM auto-reload timer (ART) ST72321xx-Auto

12.2 Functional description

12.2.1 Counter

The free running 8-bit counter is fed by the output of the prescaler, and is incremented on
every rising edge of the clock signal.

It is possible to read or write the contents of the counter on the fly by reading or writing the
Counter Access register (ARTCAR).

When a counter overflow occurs, the counter is automatically reloaded with the contents of
the ARTARR register (the prescaler is not affected).

12.2.2 Counter clock and prescaler

The counter clock frequency is given by:

/ 2

CC[2:0]

The timer counter’s input clock (f

f

COUNTER

INPUT

= f

INPUT

) feeds the 7-bit programmable prescaler, which
selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the
Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2
(where n = 0, 1,..7).

n

This f
can be either the f

frequency source is selected through the EXCL bit of the ARTCSR register and

INPUT

or an external input frequency f

CPU

The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the
ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter
contents are frozen. When TCE is set, the counter runs at the rate of the selected clock
source.

12.2.3 Counter and prescaler initialization

After RESET, the counter and the prescaler are cleared and f

The counter can be initialized by:

● writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load)

and the TCE (Timer Counter Enable) bits in the ARTCSR register

● writing to the ARTCAR counter access register

In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known
value.

Direct access to the prescaler is not possible.

12.2.4 Output compare control

The timer compare function is based on four different comparisons with the counter (one for
each PWMx output). Each comparison is made between the counter value and an output
compare register (OCRx) value. This OCRx register can not be accessed directly, it is
loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.

EXT

.

INPUT

= f

CPU

.

This double buffering method avoids glitch generation when changing the duty cycle on the
fly.

88/243 Doc ID 13829 Rev 1

ST72321xx-Auto PWM auto-reload timer (ART)

COUNTER

FDh FEh FFh FDh FEh FFh FDh FEh

ARTARR = FDh

f

COUNTER

OCRx

PWMDCRx

FDh

FEh

FDh

FEh

FFh

PWMx

Figure 36. Output compare control

12.2.5 Independent PWM signal generation

This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins with minimum core processing overhead. This function is stopped during Halt
mode.

Each PWMx output signal can be selected independently using the corresponding OEx bit
in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is
configured as output push-pull alternate function.

The PWM signals all have the same frequency which is controlled by the counter period and
the ARTARR register value.

f

PWM

= f

COUNTER

/ (256 - ARTARR)

When a counter overflow occurs, the PWMx pin level is changed depending on the
corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches
the value contained in one of the output compare register (OCRx) the corresponding PWMx
pin level is restored.

It should be noted that the reload values will also affect the value and the resolution of the
duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the
OCRx register must be greater than the contents of the ARTARR register.

The maximum available resolution for the PWMx duty cycle is:

Resolution = 1 / (256 - ARTARR)

Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum

resolution, 0% and 100% can be obtained by changing the polarity.

Doc ID 13829 Rev 1 89/243

PWM auto-reload timer (ART) ST72321xx-Auto

DUTY CYCLE

REGISTER

AUTO-REL OAD

REGISTER

PWMx OUTPUT

t

255

000

WITH OEx=1
AND OPx=0

(ARTARR)

(PWMDCRx)

WITH OEx=1
AND OPx=1

COUNTER

COUNTER

PWMx OUTPUT

t

WITH OEx=1

AND OPx=0

FDh FEh FFh FDh FEh FFh FDh FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

ARTARR = FDh

f

COUNTER

Figure 37. PWM auto-reload timer function

Figure 38. PWM signal from 0% to 100% duty cycle

12.2.6 Output compare and time base interrupt

On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is
generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF
flag must be reset by the user software. This interrupt can be used as a time base in the
application.

12.2.7 External clock and event detector mode

Using the f
external clock event detector. In this mode, the ARTARR register is used to select the
n

number of events to be counted before setting the OVF flag.

EVENT

Caution: The external clock function is not available in Halt mode. If Halt mode is used in the

application, prior to executing the HALT instruction, the counter must be disabled by clearing

90/243 Doc ID 13829 Rev 1

the TCE bit in the ARTCSR register to avoid spurious counter increments.

external prescaler input clock, the auto-reload timer can be used as an

EXT

n

= 256 - ARTARR

EVENT

ST72321xx-Auto PWM auto-reload timer (ART)

COUNTER

t

FDh FEh FFh FDh

OVF

ARTCSR READ

INTERRUPT

ARTARR = FDh

f

EXT=fCOUNTER

FEh FFh FDh

IF OIE = 1

INTERRUPT

IF OIE = 1

ARTCSR READ

Figure 39. External event detector example (3 counts)

12.2.8 Input capture function

This mode allows the measurement of external signal pulse widths through ARTICRx
registers.

Each input capture can generate an interrupt independently on a selected input signal
transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture
Control/Status register (ARTICCSR).

These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.

The active transition (falling or rising edge) is software programmable through the CSx bits
of the ARTICCSR register.

The read only input capture registers (ARTICRx) are used to latch the auto-reload counter
value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register).
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.

Note: After a capture detection, data transfer in the ARTICRx register is inhibited until it is read

(clearing the CFx bit).

The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled
(CIEx bit set). This means that the ARTICRx register has to be read at each capture event to
clear the CFx flag.

The timing resolution is given by auto-reload counter cycle time (1/f

COUNTER

).

Note: During Halt mode, if both the input capture and the external clock are enabled, the ARTICRx

register value is not guaranteed if the input capture pin and the external clock change
simultaneously.

Doc ID 13829 Rev 1 91/243

PWM auto-reload timer (ART) ST72321xx-Auto

04h

COUNTER

t

01h

f

COUNTER

xxh

02h 03h 05h 06h 07h

04h

ARTICx PIN

CFx FLAG

ICRx REGISTER

INTERRUPT

12.2.9 External interrupt capability

This mode allows the input capture capabilities to be used as external interrupt sources. The
interrupts are generated on the edge of the ARTICx signal.

The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR
register) and they are independently enabled through CIEx bits of the ARTICCSR register.
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.

During Halt mode, the external interrupts can be used to wake up the micro (if the CIEx bit is
set).

Figure 40. Input capture timing diagram

92/243 Doc ID 13829 Rev 1

ST72321xx-Auto PWM auto-reload timer (ART)

12.3 ART registers

12.3.1 Control/status register (ARTCSR)

ARTCSR Reset value: 0000 0000 (00h)

76543210

EXCL CC[2:0] TCE FCRL OIE OVF

RW RW RW RW RW RW

Table 45. ARTCSR register description

Bit Name Function

External Clock

This bit is set and cleared by software. It selects the input clock for the 7-bit

7 EXCL

6:4 CC[2:0]

3TCE

2 FCRL

1OIE

0OVF

Table 46. Prescaler selection for ART

prescaler.
0: CPU clock
1: External clock

Counter Clock Control

These bits are set and cleared by software. They determine the prescaler division
ratio from f

(see Ta bl e 4 6 ).

INPUT

Timer Counter Enable

This bit is set and cleared by software. It puts the timer in the lowest power
consumption mode.
0: Counter stopped (prescaler and counter frozen)
1: Counter running

Force Counter Re-Load

This bit is write-only and any attempt to read it will yield a logical zero. When set, it
causes the contents of ARTARR register to be loaded into the counter, and the
content of the prescaler register to be cleared in order to initialize the timer before
starting to count.

Overflow Interrupt Enable

This bit is set and cleared by software. It allows to enable/disable the interrupt which
is generated when the OVF bit is set.
0: Overflow Interrupt disable
1: Overflow Interrupt enable

Overflow Flag

This bit is set by hardware and cleared by software reading the ARTCSR register. It
indicates the transition of the counter from FFh to the ARTARR value.
0: New transition not yet reached
1: Transition reached

f

COUNTER

f

INPUT

f

/ 2 4 MHz 0 0 1

INPUT

/ 4 2 MHz 0 1 0

f

INPUT

With f

= 8 MHz CC2 CC1 CC0

INPUT

8 MHz 000

Doc ID 13829 Rev 1 93/243

PWM auto-reload timer (ART) ST72321xx-Auto

Table 46. Prescaler selection for ART (continued)

f

COUNTER

f

/ 8 1 MHz 0 1 1

INPUT

f

/ 16 500 kHz 1 0 0

INPUT

/ 32 250 kHz 1 0 1

f

INPUT

/ 64 125 kHz 1 1 0

f

INPUT

f

/ 128 62.5 kHz 1 1 1

INPUT

With f

INPUT

12.3.2 Counter access register (ARTCAR)

ARTCAR Reset value: 0000 0000 (00h)

76543210

CA[7:0]

Table 47. ARTCAR register description

Bit Name Function

Counter Access Data

7:0 CA[7:0]

These bits can be set and cleared either by hardware or by software. The
ARTCAR register is used to read or write the auto-reload counter “on the fly”
(while it is counting).

= 8 MHz CC2 CC1 CC0

RW

12.3.3 Auto-reload register (ARTARR)

ARTARR Reset value: 0000 0000 (00h)

76543210

Table 48. ARTAAR register description

Bit Name Function

Counter Auto-Reload Data

These bits are set and cleared by software. They are used to hold the auto-reload

7:0 AR[7:0]

This register has two PWM management functions:

– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution

value which is automatically loaded in the counter when an overflow occurs. At the
same time, the PWM output levels are changed according to the corresponding
OPx bit in the PWMCR register.

AR[7:0]

RW

94/243 Doc ID 13829 Rev 1

ST72321xx-Auto PWM auto-reload timer (ART)

Table 49. PWM frequency versus resolution

f

PWM

ARTARR value Resolution

Min Max

0 8-bit ~0.244 kHz 31.25 kHz

[ 0..127 ] > 7-bit ~0.244 kHz 62.5 kHz

[ 128..191 ] > 6-bit ~0.488 kHz 125 kHz

[ 192..223 ] > 5-bit ~0.977 kHz 250 kHz

[ 224..239 ] > 4-bit ~1.953 kHz 500 kHz

12.3.4 PWM control register (PWMCR)

PWMCR Reset value: 0000 0000 (00h)

76543210

OE[3:0] OP[3:0]

RW RW

Table 50. PWMCR register description

Bit Name Function

PWM Output Enable

These bits are set and cleared by software. They enable or disable the PWM

7:4 OE[3:0]

output channels independently acting on the corresponding I/O pin.
0: PWM output disabled
1: PWM output enabled

PWM Output Polarity

3:0 OP[3:0]

These bits are set and cleared by software. They independently select the polarity
of the four PWM output signals (see Ta bl e 5 1 ).

Table 51. PWM output signal polarity selection

PWMx output level

Counter <= OCRx Counter > OCRx

100

011

1. When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.

OPx

(1)

Doc ID 13829 Rev 1 95/243

PWM auto-reload timer (ART) ST72321xx-Auto

12.3.5 Duty cycle registers (PWMDCRx)

PWMDCRx Reset value: 0000 0000 (00h)

76543210

DC[7:0]

RW

Table 52. PWMDCRx register description

Bit Name Function

7:0 DC[7:0]

Duty Cycle Data

These bits are set and cleared by software.

A PWMDCRx register is associated with the OCRx register of each PWM channel to
determine the second edge location of the PWM signal (the first edge location is common to
all channels and given by the ARTARR register). These PWMDCR registers allow the duty
cycle to be set independently for each PWM channel.

12.3.6 Input capture control / status register (ARTICCSR)

ARTICCSR Reset value: 0000 0000 (00h)

76543210

Reserved CS[2:1] CIE[2:1] CF[2:1]

-RWRWRW

Table 53. ARTICCSR register description

Bit Name Function

7:6 - Reserved, always read as 0.

Capture Sensitivity

5:4 CS[2:1]

3:2 CIE[2:1]

1:0 CF[2:1]

These bits are set and cleared by software. They determine the trigger event
polarity on the corresponding input capture channel.
0: Falling edge triggers capture on channel x
1: Rising edge triggers capture on channel x

Capture Interrupt Enable

These bits are set and cleared by software. They enable or disable the Input
capture channel interrupts independently.
0: Input capture channel x interrupt disabled
1: Input capture channel x interrupt enabled

Capture Flag

These bits are set by hardware and cleared by software reading the
corresponding ARTICRx register. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x
1: An input capture has occurred on channel x.

96/243 Doc ID 13829 Rev 1

ST72321xx-Auto PWM auto-reload timer (ART)

12.3.7 Input capture registers (ARTICRx)

ARTICRx Reset value: 0000 0000 (00h)

76543210

IC[7:0]

RO

Table 54. ARTICRx register description

Bit Name Function

Input Capture Data

7:0 IC[7:0]

Table 55. PWM auto-reload timer register map and reset values

Address (Hex.) Register label 7 6 5 4 3 2 1 0

These read only bits are set and cleared by hardware. An ARTICRx register
contains the 8-bit auto-reload counter value transferred by the input capture
channel x event.

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

PWMDCR3

DC70DC60DC50DC40DC30DC20DC10DC0

Reset value

PWMDCR2

DC70DC60DC50DC40DC30DC20DC10DC0

Reset value

PWMDCR1

DC70DC60DC50DC40DC30DC20DC10DC0

Reset value

PWMDCR0

DC70DC60DC50DC40DC30DC20DC10DC0

Reset value

PWMCR

OE30OE20OE10OE00OP30OP20OP10OP0

Reset value

ARTCSR
Reset value

ARTCAR

EXCL

CA70CA60CA50CA40CA30CA20CA10CA0

CC20CC10CC00TCE0FCRL0RIE0OVF

0

Reset value

ARTARR

AR70AR60AR50AR40AR30AR20AR10AR0

Reset value

ARTICCSR
Reset value 0 0

ARTICR1
Reset value

ARTICR2
Reset value

IC7

0

IC7

0

IC60IC50IC40IC3

IC60IC50IC40IC3

0

0

0

0

0

0

0

0

CS20CS10CIE20CIE10CF20CF1

0

IC2

0

0

IC2

0

0

IC10IC0

0

IC10IC0

0

Doc ID 13829 Rev 1 97/243

16-bit timer ST72321xx-Auto

13 16-bit timer

13.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after an MCU reset as long as the timer
clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).

13.2 Main features

● Programmable prescaler: f

● Overflow status flag and maskable interrupt

● External clock input (must be at least four times slower than the CPU clock speed) with

divided by 2, 4 or 8

CPU

the choice of active edge

● 1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt

● 1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt

● Pulse Width Modulation mode (PWM)

● One Pulse mode

● Reduced Power mode

● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)

The block diagram is shown in Figure 41.

Note: When reading an input signal on a non-bonded pin, the value will always be ‘1’.

(a)

a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout

description.

98/243 Doc ID 13829 Rev 1

ST72321xx-Auto 16-bit timer

13.3 Functional description

13.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.

Counter Register (CR)

● Counter High Register (CHR) is the most significant byte (MS Byte)

● Counter Low Register (CLR) is the least significant byte (LS Byte)

Alternate Counter Register (ACR)

● Alternate Counter High Register (ACHR) is the most significant byte (MS Byte)

● Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte)

These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.

Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM
mode.

The timer clock depends on the clock control bits of the CR2 register, as illustrated in

Table 61: Timer clock selection. The value in the counter register repeats every 131072,

262144 or 524288 CPU clock cycles depending on the CC[1:0] bits.

The timer frequency can be f

CPU

/2, f

CPU

/4, f

/8 or an external frequency.

CPU

Doc ID 13829 Rev 1 99/243

16-bit timer ST72321xx-Auto

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE

REGISTER

OUTPUT COMPARE

EDGE DETECT

OVERFLOW

DETECT

CIRCUIT

1/2
1/4
1/8

8-bit

buffer

ST7 INTERNAL BUS

LATCH1

OCMP1

ICAP1

EXTCLK

f

CPU

TIMER INTERRUPT

ICF2ICF1 TIMD 0 0OCF2OCF1 TOF

PWMOC1E EXEDGIEDG2CC0CC1OC2E OPM

FOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE

ICAP2

LATCH2

OCMP2

8

8

8 low

16

8 high

16 16

16

16

(Control Register 1) CR1

(Control Register 2) CR2

6

16

8 8 8

88 8

high

low

high

high

high

low

low

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

1

OUTPUT
COMPARE
REGISTER

2

INPUT

CAPTURE

REGISTER

1

INPUT

CAPTURE

REGISTER

2

CC[1:0]

COUNTER

pin

pin

pin

pin

pin

REGISTER

REGISTER

(1)

CSR

(Control/Status Register)

Figure 41. Timer block diagram

1. If IC, OC and TO interrupt request have separate vectors, then the last OR is not present (see device interrupt vector table).

100/243 Doc ID 13829 Rev 1