ST72334xx-Auto,
ST72314xx-Auto, ST72124Jx-Auto
8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces
■Memories
–8 or 16 Kbyte Program memory (ROM or single voltage Flash) with readout protection and in-situ programming (remote ISP)
–256 bytes EEPROM Data memory (with readout protection option in ROM devices)
–384 or 512 bytes RAM
■Clock, Reset and Supply Management
–Enhanced reset system
–Enhanced low voltage supply supervisor with 3 programmable levels
–Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
–4 Power Saving Modes: Halt, Active Halt, Wait and Slow
–Beep and clock-out capabilities
■Interrupt Management
–10 interrupt vectors plus TRAP and RESET
–15 external interrupt lines (4 vectors)
■44 or 32 I/O Ports
–44 or 32 multifunctional bidirectional I/O lines:
–21 or 19 alternate function lines
–12 or 8 high sink outputs
■4 Timers
–Configurable watchdog timer
–Real-time base
–Two 16-bit timers with: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes
Device Summary
TQFP64 |
TQFP44 |
14 x 14 |
10 x 10 |
■2 Communications Interfaces
–SPI synchronous serial interface
–SCI asynchronous serial interface (LIN compatible)
■1 Analog Peripheral
–8-bit ADC with 8 input channels (6 only on ST72334Jx, not available on ST72124J2)
■Instruction Set
–8-bit data manipulation
–63 basic instructions
–17 main addressing modes
–8 x 8 unsigned multiply instruction
–True bit manipulation
■Development Tools
–Full hardware/software development package
Features |
ST72124J2 |
ST72314J2 |
ST72314J4 |
ST72314N2 |
ST72314N4 |
ST72334J2 |
ST72334J4 |
ST72334N2 |
ST72334N4 |
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-Auto |
-Auto |
-Auto |
-Auto |
-Auto |
-Auto |
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-Auto |
-Auto |
-Auto |
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Prog. memory |
8 Kbytes |
16 Kbytes |
8 Kbytes |
16 Kbytes |
8 Kbytes |
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16 Kbytes |
8 Kbytes |
16 Kbytes |
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Flash/ROM |
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RAM (stack) |
384 (256) bytes |
512 (256) |
384 (256) |
512 (256) |
384 (256) |
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512 (256) |
384 (256) |
512 (256) |
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EEPROM |
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- |
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256 |
bytes |
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Peripherals |
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Watchdog, Two 16-bit Timers, SPI, SCI |
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ADC |
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Oper. Supply |
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3.2V to 5.5V |
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CPU Freq. |
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Up to 8 MHz (with up to 16 MHz oscillator) |
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Oper. Temp. |
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-40°C to +85°C / -40°C to +125C° Flash or ROM (-40°C to +105°C ROM only) |
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Packages |
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TQFP44 |
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TQFP64 |
TQFP44 |
TQFP64 |
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Rev. 1 |
October 2007 |
1/150 |
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1
Table of Contents
1 PREAMBLE: ST72C334-Auto VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . 7 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 STRUCTURAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 MEMORY READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 READOUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
7.2 |
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
7.3 |
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
8 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2.2 Asynchronous External RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.4.1 |
Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
8.4.2 |
Safe Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
8.4.3 |
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
8.4.4 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
8.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . |
33 |
9 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 NON-MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/150
2
Table of Contents
10.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.4 ACTIVE HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.4.1Active Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.4.2Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
11.2 |
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
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11.2.1Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
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11.2.2Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
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11.2.3Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
11.3 |
I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
11.4 |
LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
11.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.5.1Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.1 |
I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
12.2 |
I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
12.3 |
REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
13 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.1.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1.4Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1.5Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.2 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK TIMER (MCC/RTC) . . . . . . . 53
13.2.1Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.2.2Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.2.3Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.2.4Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.2.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.3.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.3.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.3.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.3.4Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.3.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.3.6Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.3.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.4.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.4.3General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.4.4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto |
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13.4.5Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
13.4.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
13.4.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
13.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
13.5.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
13.5.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
13.5.3General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
13.5.4LIN Protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
13.5.5Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
13.5.6Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
93 |
13.5.7Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
93 |
13.5.8Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
94 |
13.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
98 |
13.6.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.6.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.6.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.6.4Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.6.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.6.6Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
14.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.1.1Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1.2Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1.3Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1.4Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1.5Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1.6Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.1.7Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
15.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
15.1.1Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 15.1.2Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 15.1.3Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 15.1.4Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 15.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
15.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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15.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
109 |
|
15.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
109 |
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15.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
110 |
15.3 |
OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
111 |
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15.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
111 |
|
15.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . |
112 |
15.4 |
SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
114 |
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15.4.1Run and Slow Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
114 |
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15.4.2Wait and Slow Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
115 |
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15.4.3Halt and Active Halt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
116 |
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
15.4.4Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 15.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 15.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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15.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
117 |
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15.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
117 |
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15.5.3Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
118 |
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15.5.4RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
|
15.5.5Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
122 |
15.6 |
MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
|
15.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
|
15.6.2EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
|
15.6.3Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
15.7 |
EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
15.7.1Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 15.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 15.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 15.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
15.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15.9.2ISPSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 15.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
135 |
15.10.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
135 |
15.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
15.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.11.2SCI - Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
16 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
16.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 16.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 16.3 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 143
17.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
17.2 |
OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
|
17.2.1User Option Byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
|
17.2.2User Option Byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
17.3 |
TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
144 |
17.4 |
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
146 |
|
17.4.1Suggested List of Socket Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
147 |
17.5 |
ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
147 |
18 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
18.1 SCI BAUD RATE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
19 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet.
Please also pay special attention to the Section “IMPORTANT NOTES” on page 148
6/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
New Features available on the ST72C334-Auto
■8 or 16K Flash/ROM with In-Situ Programming and Readout protection
■New ADC with a better accuracy and conversion time
■New configurable Clock, Reset and Supply system
■New power saving mode with real-time base: Active Halt
■Beep capability on PF1
■New interrupt source: Clock security system (CSS) or Main clock controller (MCC)
ST72C334-Auto I/O Configuration and Pinout
■Same pinout as ST72E331
■PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331)
■PA3, PB3, PB4 and PF2 have no pull-up configuration (all I/Os present on TQFP44)
■PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pads without high sink capabilities. PA4 and PA5 were 20mA true open drains.
New Memory Locations in ST72C334-Auto
■20h: MISCR register becomes MISCR1 register (naming change)
■29h: new control/status register for the MCC module
■2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the WDGSR register keeping the WDOGF flag compatibility.
■40h: new MISCR2 register
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
The ST72334J/N-Auto, ST72314J/N-Auto and ST72124J-Auto devices are members of the ST7 microcontroller family. They can be grouped as follows:
–ST72334J/N-Auto devices are designed for midrange applications with Data EEPROM, ADC, SPI and SCI interface capabilities.
–ST72314J/N-Auto devices target the same range of applications but without Data EEPROM.
–ST72124J-Auto devices are for applications that do not need Data EEPROM and the ADC peripheral.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.
The ST72C334J/N-Auto, ST72C314J/N-Auto and ST72C124J-Auto versions feature single-voltage
Flash memory with byte-by-byte In-Situ Programming (ISP) capability.
Under software control, all devices can be placed in Wait, Slow, Active Halt or Halt mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
For easy reference, all parametric data is located in Section 15 on page 108.
Figure 1. General Block Diagram
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8-bit CORE |
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PROGRAM |
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ALU |
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MEMORY |
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RESET |
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(8 or 16 Kbytes) |
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CONTROL |
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ISPSEL |
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VDD |
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RAM |
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LVD |
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(384 or 512 bytes) |
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VSS |
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OSC1 |
MULTI-OSC |
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EEPROM |
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+ |
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(256 bytes) |
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OSC2 |
ADDRESS |
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CLOCK FILTER |
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MCC/RTC |
PORT A |
PA7:0 |
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(8-bit for N versions) |
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AND |
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(5-bit for J versions) |
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PORT F |
PORT B |
PB7:0 |
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DATA |
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PF7,6,4,2:0 |
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(8-bit for N versions) |
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(5-bit for J versions) |
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(6-bit) |
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PORT C |
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TIMER A |
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BUS |
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PC7:0 |
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BEEP |
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TIMER B |
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(8-bit) |
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PORT E |
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SPI |
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PE7:0 |
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(6-bit for N versions) |
SCI |
PORT D |
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(2-bit for J versions) |
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PD7:0 |
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8-bit ADC |
(8-bit for N versions) |
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WATCHDOG |
(6-bit for J versions) |
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VDDA |
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VSSA |
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
Figure 2. 64-Pin TQFP Package Pinout (N versions)
|
NC |
NC |
RDI/PE1 |
TDO/PE0 |
V |
OSC1 |
OSC2 |
V |
NC |
NC |
RESET |
ISPSEL |
(HS)PA7 |
(HS)PA6 (HS)PA5 |
(HS)PA4 |
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2 |
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2 |
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DD |
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SS |
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(HS) PE4 |
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 |
VSS_1 |
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1 |
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48 |
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(HS) PE5 |
2 |
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47 |
VDD_1 |
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(HS) PE6 |
3 |
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46 |
PA3 |
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(HS) PE7 |
4 |
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ei0 |
45 |
PA2 |
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PB0 |
5 |
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44 |
PA1 |
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PB1 |
6 |
ei2 |
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43 |
PA0 |
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PB2 |
7 |
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42 |
PC7 / |
SS |
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PB3 |
8 |
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41 |
PC6 / SCK / ISPCLK |
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PB4 |
9 |
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40 |
PC5 / MOSI |
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PB5 |
10 |
ei3 |
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39 |
PC4 / MISO / ISPDATA |
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PB6 |
11 |
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38 |
PC3 (HS) / ICAP1_B |
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PB7 |
12 |
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37 |
PC2 (HS) / ICAP2_B |
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AIN0 / PD0 |
13 |
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36 |
PC1 / OCMP1_B |
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AIN1 / PD1 |
14 |
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35 |
PC0 / OCMP2_B |
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AIN2 / PD2 |
15 |
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ei1 |
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34 |
VSS_0 |
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AIN3 / PD3 |
16 |
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33 |
VDD_0 |
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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AIN4 / PD4 |
AIN5 / PD5 |
AIN6 / PD6 |
AIN7 / PD7 |
V |
V |
V |
V |
MCO / PF0 |
BEEP/ PF1 |
PF2 |
NC |
OCMP1A / PF4 |
NC AICAP1/ (HS) PF6 |
AEXTCLK/ (HS) PF7 |
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DDA |
SSA |
DD3 |
SS3 |
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(HS) |
20mA high sink capability |
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eix |
associated external interrupt vector |
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9/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
PIN DESCRIPTION (Cont’d)
Figure 3. 44-Pin TQFP Package Pinout (J versions)
|
TDO/PE0 |
V |
OSC1 |
OSC2 |
V |
RESET |
ISPSEL (HS)PA7 |
(HS)PA6 |
(HS)PA5 |
(HS)PA4 |
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2 |
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2 |
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DD |
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SS |
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||||||||
PE1 / RDI |
44 43 42 41 40 39 38 37 36 35 34 |
VSS_1 |
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|||||||||
1 |
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33 |
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||
PB0 |
2 |
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32 |
VDD_1 |
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PB1 |
3 |
ei2 |
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ei0 |
31 |
PA3 |
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PB2 |
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4 |
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30 |
PC7 / SS |
||||
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PB3 |
5 |
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29 |
PC6 / SCK / ISPCLK |
||
PB4 |
6 |
ei3 |
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28 |
PC5 / MOSI |
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AIN0 / PD0 |
7 |
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27 |
PC4 / MISO / ISPDATA |
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AIN1 / PD1 |
8 |
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26 |
PC3 (HS) / ICAP1_B |
||
AIN2 / PD2 |
9 |
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25 |
PC2 (HS) / ICAP2_B |
||
AIN3 / PD3 |
10 |
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ei1 |
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24 |
PC1 / OCMP1_B |
||
AIN4 / PD4 |
11 |
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23 |
PC0 / OCMP2_B |
||
|
12 13 14 15 16 17 18 19 20 21 22 |
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|||||||||
|
AIN5 / PD5 |
V |
V |
MCO / PF0 |
BEEP/ PF1 |
PF2 |
OCMP1A / PF4 AICAP1/ (HS) PF6 |
AEXTCLK/ (HS) PF7 |
V |
V |
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DDA |
SSA |
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DD0 |
SS0 |
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(HS) |
20mA high sink capability |
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eix |
associated external interrupt vector |
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10/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 15 "ELECTRICAL CHARACTERISTICS" on page 108.
Legend / Abbreviations for Table 1:
Type: |
I = input, O = output, S = supply |
|
Input level: |
A = Dedicated analog input |
|
In/Output level: C = CMOS 0.3VDD/0.7VDD, |
||
|
|
CT= CMOS 0.3VDD/0.7VDD with input trigger |
Output level: |
HS = 20mA high sink (on N-buffer only) |
|
Port and control configuration: |
||
– |
Input: |
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog |
– |
Output: |
OD = open drain 2), PP = push-pull |
Refer to Section 11 "I/O PORTS" on page 40 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.
Table 1. Device Pin Description
Pin |
|
|
Level |
|
|
Port |
|
|
Main |
|
|||
No. |
|
Type |
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|
||||||
|
Input |
Output |
float |
wpu |
int |
ana |
OD |
PP |
function |
|
|||
TQFP64 |
TQFP44 |
Pin Name |
Alternate function |
||||||||||
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Input |
|
Output |
|||||
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(after |
||||||
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reset) |
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1 |
- |
PE4 (HS) |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port E4 |
|
2 |
- |
PE5 (HS) |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port E5 |
|
3 |
- |
PE6 (HS) |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port E6 |
|
4 |
- |
PE7 (HS) |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port E7 |
|
5 |
2 |
PB0 |
I/O |
CT |
X |
ei2 |
|
X |
X |
Port B0 |
|
||
6 |
3 |
PB1 |
I/O |
CT |
X |
ei2 |
|
X |
X |
Port B1 |
|
||
7 |
4 |
PB2 |
I/O |
CT |
X |
ei2 |
|
X |
X |
Port B2 |
|
||
8 |
5 |
PB3 |
I/O |
CT |
X |
|
ei2 |
|
X |
X |
Port B3 |
|
|
9 |
6 |
PB4 |
I/O |
CT |
X |
|
ei3 |
|
X |
X |
Port B4 |
|
|
10 |
- |
PB5 |
I/O |
CT |
X |
ei3 |
|
X |
X |
Port B5 |
|
||
11 |
- |
PB6 |
I/O |
CT |
X |
ei3 |
|
X |
X |
Port B6 |
|
||
12 |
- |
PB7 |
I/O |
CT |
X |
ei3 |
|
X |
X |
Port B7 |
|
||
13 |
7 |
PD0/AIN0 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D0 |
ADC Analog Input 0 |
|
14 |
8 |
PD1/AIN1 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D1 |
ADC Analog Input 1 |
|
15 |
9 |
PD2/AIN2 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D2 |
ADC Analog Input 2 |
|
16 |
10 |
PD3/AIN3 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D3 |
ADC Analog Input 3 |
|
17 |
11 |
PD4/AIN4 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D4 |
ADC Analog Input 4 |
|
18 |
12 |
PD5/AIN5 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D5 |
ADC Analog Input 5 |
|
19 |
- |
PD6/AIN6 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D6 |
ADC Analog Input 6 |
|
20 |
- |
PD7/AIN7 |
I/O |
CT |
X |
X |
|
X |
X |
X |
Port D7 |
ADC Analog Input 7 |
|
21 |
13 |
VDDA |
S |
|
|
|
|
|
|
|
|
Analog Power Supply Voltage |
|
22 |
14 |
VSSA |
S |
|
|
|
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|
|
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|
Analog Ground Voltage |
|
23 |
- |
VDD_3 |
S |
|
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|
Digital Main Supply Voltage |
11/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
Pin |
|
|
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|
Level |
|
|
Port |
|
|
Main |
|
||||
No. |
|
|
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|
Type |
|
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|
|
|
|||||||
|
|
|
|
|
Input |
|
Output |
float |
wpu |
int |
ana |
OD |
PP |
function |
|
|||
TQFP64 |
TQFP44 |
|
|
Pin Name |
|
Alternate function |
||||||||||||
|
|
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|
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|
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|
Input |
|
Output |
|||||||
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|
(after |
||||||||
|
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reset) |
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|||
24 |
- |
|
VSS_3 |
S |
|
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|
|
|
|
Digital Ground Voltage |
||||
25 |
15 |
|
PF0/MCO |
I/O |
CT |
X |
ei1 |
|
X |
X |
Port F0 |
Main clock output (fOSC/2) |
||||||
26 |
16 |
|
PF1/BEEP |
I/O |
CT |
X |
ei1 |
|
X |
X |
Port F1 |
Beep signal output |
||||||
27 |
17 |
|
PF2 |
I/O |
CT |
X |
|
ei1 |
|
X |
X |
Port F2 |
|
|||||
28 |
- |
|
NC |
|
|
|
|
|
|
|
|
|
Not Connected |
|
||||
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|
|
|
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|
|
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|
|
|
|
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|
||||
29 |
18 |
|
PF4/OCMP1_A |
I/O |
CT |
X |
X |
|
|
X |
X |
Port F4 |
Timer A Output Compare 1 |
|||||
30 |
- |
|
NC |
|
|
|
|
|
|
|
|
|
Not Connected |
|
||||
|
|
|
|
|
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|
|
|
|
|
|
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|
|||
31 |
19 |
|
PF6 (HS)/ICAP1_A |
I/O |
CT |
|
HS |
X |
X |
|
|
X |
X |
Port F6 |
Timer A Input Capture 1 |
|||
32 |
20 |
|
PF7 (HS)/EXTCLK_A |
I/O |
CT |
|
HS |
X |
X |
|
|
X |
X |
Port F7 |
Timer A External Clock Source |
|||
33 |
21 |
|
VDD_0 |
S |
|
|
|
|
|
|
|
|
|
Digital Main Supply Voltage |
||||
34 |
22 |
|
VSS_0 |
S |
|
|
|
|
|
|
|
|
|
Digital Ground Voltage |
||||
35 |
23 |
|
PC0/OCMP2_B |
I/O |
CT |
X |
X |
|
|
X |
X |
Port C0 |
Timer B Output Compare 2 |
|||||
36 |
24 |
|
PC1/OCMP1_B |
I/O |
CT |
X |
X |
|
|
X |
X |
Port C1 |
Timer B Output Compare 1 |
|||||
37 |
25 |
|
PC2 (HS)/ICAP2_B |
I/O |
CT |
|
HS |
X |
X |
|
|
X |
X |
Port C2 |
Timer B Input Capture 2 |
|||
38 |
26 |
|
PC3 (HS)/ICAP1_B |
I/O |
CT |
|
HS |
X |
X |
|
|
X |
X |
Port C3 |
Timer B Input Capture 1 |
|||
39 |
27 |
|
PC4/MISO |
I/O |
CT |
X |
X |
|
|
X |
X |
Port C4 |
SPI Master In / Slave Out Data |
|||||
40 |
28 |
|
PC5/MOSI |
I/O |
CT |
X |
X |
|
|
X |
X |
Port C5 |
SPI Master Out / Slave In Data |
|||||
41 |
29 |
|
PC6/SCK |
I/O |
CT |
X |
X |
|
|
X |
X |
Port C6 |
SPI Serial Clock |
|||||
42 |
30 |
|
|
|
|
|
|
|
|
|
X |
|
|
|
|
|
|
|
PC7/SS |
|
I/O |
CT |
X |
|
|
X |
X |
Port C7 |
SPI Slave Select (active low) |
||||||||
43 |
- |
|
PA0 |
I/O |
CT |
X |
ei0 |
|
X |
X |
Port A0 |
|
||||||
44 |
- |
|
PA1 |
I/O |
CT |
X |
ei0 |
|
X |
X |
Port A1 |
|
||||||
45 |
- |
|
PA2 |
I/O |
CT |
X |
ei0 |
|
X |
X |
Port A2 |
|
||||||
46 |
31 |
|
PA3 |
I/O |
CT |
X |
|
ei0 |
|
X |
X |
Port A3 |
|
|||||
47 |
32 |
|
VDD_1 |
S |
|
|
|
|
|
|
|
|
|
Digital Main Supply Voltage |
||||
48 |
33 |
|
VSS_1 |
S |
|
|
|
|
|
|
|
|
|
Digital Ground Voltage |
||||
49 |
34 |
|
PA4 (HS) |
I/O |
CT |
|
HS |
X |
X |
|
|
X |
X |
Port A4 |
|
|||
50 |
35 |
|
PA5 (HS) |
I/O |
CT |
|
HS |
X |
X |
|
|
X |
X |
Port A5 |
|
|||
51 |
36 |
|
PA6 (HS) |
I/O |
CT |
|
HS |
X |
|
|
|
T |
|
Port A6 |
|
|||
52 |
37 |
|
PA7 (HS) |
I/O |
CT |
|
HS |
X |
|
|
|
T |
|
Port A7 |
|
|||
|
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|
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|
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|
|
|
Must be tied low in user mode. In programming |
|
53 |
38 |
|
ISPSEL |
I |
|
|
|
|
|
|
|
|
|
mode when available, this pin acts as In-Situ |
||||
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|
Programming mode selection. |
|
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|
||
54 |
39 |
|
|
|
|
I/O |
|
C |
|
X |
|
|
|
X |
Top priority non maskable interrupt (active low) |
|||
RESET |
|
|
|
|
|
|||||||||||||
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|
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|
|
|
|
|
|
|
|||
55 |
- |
|
NC |
|
|
|
|
|
|
|
|
|
Not Connected |
|
||||
|
|
|
|
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|
||
56 |
- |
|
NC |
|
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|||||
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|||
57 |
40 |
|
VSS_3 |
S |
|
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|
|
Digital Ground Voltage |
||||
58 |
41 |
|
OSC2 3) |
O |
|
|
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|
|
|
|
|
Resonator oscillator inverter output or capaci- |
||||
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|
|
tor input for RC oscillator |
||||||||
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|
59 |
42 |
|
OSC1 3) |
I |
|
|
|
|
|
|
|
|
|
External clock input or Resonator oscillator in- |
||||
|
|
|
|
|
|
|
|
|
|
verter input or resistor input for RC oscillator |
||||||||
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|
||||
60 |
43 |
|
VDD_3 |
S |
|
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|
|
|
|
Digital Main Supply Voltage |
12/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
Pin |
|
|
No. |
|
|
|
|
Pin Name |
TQFP64 |
TQFP44 |
|
|
|
|
|
|
|
61 |
44 |
PE0/TDO |
62 |
1 |
PE1/RDI |
63 |
- |
NC |
|
|
|
64 |
- |
NC |
|
|
|
Type
I/O
I/O
Level |
|
|
Port |
|
|
Main |
|
|||
|
|
|
|
|
|
|
|
|
function |
Alternate function |
|
|
Output |
|
Input |
|
Output |
||||
Input |
|
float |
ana |
(after |
||||||
|
wpu |
int |
OD |
PP |
|
|||||
|
|
|
|
|
|
|
|
|
reset) |
|
|
|
|
|
|
|
|
|
|
|
|
|
CT |
X |
X |
|
|
X |
X |
Port E0 |
SCI Transmit Data Out |
|
|
CT |
X |
X |
|
|
X |
X |
Port E1 |
SCI Receive Data In |
Not Connected
Notes:
1.In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
2.In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 11 "I/O PORTS" on page 40 and Section 15.8 "I/O PORT PIN CHARACTERISTICS" on page 129 for more details.
3.OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 3 "PIN DESCRIPTION" on page 9 and Section 15.5 "CLOCK AND TIMING CHARACTERISTICS" on page 117 for more details.
13/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
As shown in the Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.
The available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of RAM, up to 256 bytes of data EEPROM and 4 or 8 Kbytes of user program memory. The RAM
space includes up to 256 bytes for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 4. Memory Map
0000h |
HW Registers |
0080h |
Short Addressing RAM |
|
|
|
Zero page |
||
|
(see Table 2) |
|
||
007Fh |
00FFh |
(128 bytes) |
||
|
|
|
||
|
|
0100h |
Stack or |
|
0080h |
|
|
||
|
|
384 bytes RAM |
|
16-bit Addressing RAM |
01FFh |
|
01FFh |
(256 bytes) |
|
|
|
|
||
027Fh |
512 bytes RAM |
|
|
|
|
|
0080h |
Short Addressing RAM |
|
0200h / 0280h |
|
|
||
Reserved |
00FFh |
Zero page |
||
|
(128 bytes) |
|||
0BFFh |
|
|
|
|
|
|
0100h |
Stack or |
|
0C00h |
|
|
||
|
|
|
||
256 bytes Data EEPROM |
|
16-bit Addressing RAM |
||
0CFFh |
|
|||
|
|
01FFh |
(256 bytes) |
|
0D00h |
Reserved |
0200h |
|
|
BFFFh |
16-bit Addressing |
|||
|
|
|
RAM |
|
C000h |
|
|
027Fh |
|
|
|
|
||
E000h |
|
16 Kbytes |
|
|
8 Kbytes |
Program |
C000h |
|
|
|
|
|||
|
Program |
Memory |
|
|
|
|
16 Kbytes |
||
FFDFh |
Memory |
|
E000h |
|
FFE0h |
|
|
8 Kbytes |
|
Interrupt and Reset Vectors |
|
|||
|
FFFFh |
|
||
|
|
|
|
|
FFFFh |
(see Table 6 on page 35) |
|
|
|
|
|
|
|
14/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
REGISTER AND MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address |
Block |
Register |
Register Name |
Reset |
Remarks |
|
Label |
Status |
|||||
|
|
|
|
|||
|
|
|
|
|
|
|
0000h |
|
PADR |
Port A Data Register |
00h1) |
R/W |
|
0001h |
Port A |
PADDR |
Port A Data Direction Register |
00h |
R/W |
|
0002h |
|
PAOR |
Port A Option Register |
00h |
R/W 2) |
|
|
|
|
|
|
|
|
0003h |
|
|
Reserved Area (1 byte) |
|
|
|
|
|
|
|
|
|
|
0004h |
|
PCDR |
Port C Data Register |
00h1) |
R/W |
|
0005h |
Port C |
PCDDR |
Port C Data Direction Register |
00h |
R/W |
|
0006h |
|
PCOR |
Port C Option Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0007h |
|
|
Reserved Area (1 byte) |
|
|
|
|
|
|
|
|
|
|
0008h |
|
PBDR |
Port B Data Register |
00h1) |
R/W |
|
0009h |
Port B |
PBDDR |
Port B Data Direction Register |
00h |
R/W |
|
000Ah |
|
PBOR |
Port B Option Register |
00h |
R/W 2) |
|
|
|
|
|
|
|
|
000Bh |
|
|
Reserved Area (1 byte) |
|
|
|
|
|
|
|
|
|
|
000Ch |
|
PEDR |
Port E Data Register |
00h1) |
R/W |
|
000Dh |
Port E |
PEDDR |
Port E Data Direction Register |
00h |
R/W |
|
000Eh |
|
PEOR |
Port E Option Register |
00h |
R/W 2) |
|
|
|
|
|
|
|
|
000Fh |
|
|
Reserved Area (1 byte) |
|
|
|
|
|
|
|
|
|
|
0010h |
|
PDDR |
Port D Data Register |
00h1) |
R/W |
|
0011h |
Port D |
PDDDR |
Port D Data Direction Register |
00h |
R/W |
|
0012h |
|
PDOR |
Port D Option Register |
00h |
R/W 2) |
|
|
|
|
|
|
|
|
0013h |
|
|
Reserved Area (1 byte) |
|
|
|
|
|
|
|
|
|
|
0014h |
|
PFDR |
Port F Data Register |
00h1) |
R/W |
|
0015h |
Port F |
PFDDR |
Port F Data Direction Register |
00h |
R/W |
|
0016h |
|
PFOR |
Port F Option Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0017h |
|
|
|
|
|
|
to |
|
|
Reserved Area (9 bytes) |
|
|
|
001Fh |
|
|
|
|
|
|
|
|
|
|
|
|
|
0020h |
|
MISCR1 |
Miscellaneous Register 1 |
00h |
R/W |
|
|
|
|
|
|
|
|
0021h |
|
SPIDR |
SPI Data I/O Register |
xxh |
R/W |
|
0022h |
SPI |
SPICR |
SPI Control Register |
0xh |
R/W |
|
0023h |
|
SPISR |
SPI Status Register |
00h |
Read Only |
|
|
|
|
|
|
|
|
0024h |
|
|
|
|
|
|
to |
|
|
Reserved Area (5 bytes) |
|
|
|
0028h |
|
|
|
|
|
|
|
|
|
|
|
|
|
0029h |
MCC |
MCCSR |
Main Clock Control / Status Register |
01h |
R/W |
|
|
|
|
|
|
|
15/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
Address |
Block |
Register |
Register Name |
Reset |
Remarks |
|
Label |
Status |
|||||
|
|
|
|
|||
|
|
|
|
|
|
|
002Ah |
WATCHDOG |
WDGCR |
Watchdog Control Register |
7Fh |
R/W |
|
|
|
|
|
|
|
|
002Bh |
|
CRSR |
Clock, Reset, Supply Control / Status Register |
000x 000x |
R/W |
|
|
|
|
|
|
|
|
002Ch |
Data-EEPROM |
EECSR |
Data-EEPROM Control/Status Register |
00h |
R/W |
|
|
|
|
|
|
|
|
002Dh |
|
|
Reserved Area (4 bytes) |
|
|
|
0030h |
|
|
|
|
||
|
|
|
|
|
||
|
|
|
|
|
|
|
0031h |
|
TACR2 |
Timer A Control Register 2 |
00h |
R/W |
|
0032h |
|
TACR1 |
Timer A Control Register 1 |
00h |
R/W |
|
0033h |
|
TASR |
Timer A Status Register |
xxh |
Read Only |
|
0034h |
|
TAIC1HR |
Timer A Input Capture 1 High Register |
xxh |
Read Only |
|
0035h |
|
TAIC1LR |
Timer A Input Capture 1 Low Register |
xxh |
Read Only |
|
0036h |
|
TAOC1HR |
Timer A Output Compare 1 High Register |
80h |
R/W |
|
0037h |
|
TAOC1LR |
Timer A Output Compare 1 Low Register |
00h |
R/W |
|
0038h |
TIMER A |
TACHR |
Timer A Counter High Register |
FFh |
Read Only |
|
0039h |
|
TACLR |
Timer A Counter Low Register |
FCh |
Read Only |
|
003Ah |
|
TAACHR |
Timer A Alternate Counter High Register |
FFh |
Read Only |
|
003Bh |
|
TAACLR |
Timer A Alternate Counter Low Register |
FCh |
Read Only |
|
003Ch |
|
TAIC2HR |
Timer A Input Capture 2 High Register |
xxh |
Read Only 3) |
|
003Dh |
|
TAIC2LR |
Timer A Input Capture 2 Low Register |
xxh |
Read Only 3) |
|
003Eh |
|
TAOC2HR |
Timer A Output Compare 2 High Register |
80h |
R/W 3) |
|
003Fh |
|
TAOC2LR |
Timer A Output Compare 2 Low Register |
00h |
R/W 3) |
|
|
|
|
|
|
|
|
0040h |
|
MISCR2 |
Miscellaneous Register 2 |
00h |
R/W |
|
|
|
|
|
|
|
|
0041h |
|
TBCR2 |
Timer B Control Register 2 |
00h |
R/W |
|
0042h |
|
TBCR1 |
Timer B Control Register 1 |
00h |
R/W |
|
0043h |
|
TBSR |
Timer B Status Register |
xxh |
Read Only |
|
0044h |
|
TBIC1HR |
Timer B Input Capture 1 High Register |
xxh |
Read Only |
|
0045h |
|
TBIC1LR |
Timer B Input Capture 1 Low Register |
xxh |
Read Only |
|
0046h |
|
TBOC1HR |
Timer B Output Compare 1 High Register |
80h |
R/W |
|
0047h |
|
TBOC1LR |
Timer B Output Compare 1 Low Register |
00h |
R/W |
|
0048h |
TIMER B |
TBCHR |
Timer B Counter High Register |
FFh |
Read Only |
|
0049h |
|
TBCLR |
Timer B Counter Low Register |
FCh |
Read Only |
|
004Ah |
|
TBACHR |
Timer B Alternate Counter High Register |
FFh |
Read Only |
|
004Bh |
|
TBACLR |
Timer B Alternate Counter Low Register |
FCh |
Read Only |
|
004Ch |
|
TBIC2HR |
Timer B Input Capture 2 High Register |
xxh |
Read Only |
|
004Dh |
|
TBIC2LR |
Timer B Input Capture 2 Low Register |
xxh |
Read Only |
|
004Eh |
|
TBOC2HR |
Timer B Output Compare 2 High Register |
80h |
R/W |
|
004Fh |
|
TBOC2LR |
Timer B Output Compare 2 Low Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0050h |
|
SCISR |
SCI Status Register |
C0h |
Read Only |
|
0051h |
|
SCIDR |
SCI Data Register |
xxh |
R/W |
|
0052h |
|
SCIBRR |
SCI Baud Rate Register |
00xx xxxx |
R/W |
|
0053h |
SCI |
SCICR1 |
SCI Control Register 1 |
xxh |
R/W |
|
0054h |
SCICR2 |
SCI Control Register 2 |
00h |
R/W |
||
|
||||||
0055h |
|
SCIERPR |
SCI Extended Receive Prescaler Register |
00h |
R/W |
|
0056h |
|
|
Reserved area |
--- |
|
|
0057h |
|
SCIETPR |
SCI Extended Transmit Prescaler Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0058h |
|
|
Reserved Area (24 bytes) |
|
|
|
006Fh |
|
|
|
|
||
|
|
|
|
|
||
|
|
|
|
|
|
16/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
Address |
Block |
Register |
Register Name |
Reset |
Remarks |
|
Label |
Status |
|||||
|
|
|
|
|||
|
|
|
|
|
|
|
0070h |
ADC |
ADCDR |
Data Register |
xxh |
Read Only |
|
0071h |
ADCCSR |
Control/Status Register |
00h |
R/W |
||
|
||||||
|
|
|
|
|
|
|
0072h |
|
|
|
|
|
|
to |
|
|
Reserved Area (14 bytes) |
|
|
|
007Fh |
|
|
|
|
|
|
|
|
|
|
|
|
Legend: x=undefined, R/W=read/write
Notes:
1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2.The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. These bits must always keep their reset value.
3.External pin not available.
17/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
Flash devices have a single voltage non-volatile Flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by-byte basis.
■Remote In-Situ Programming (ISP) mode
■Up to 16 bytes programmed in the same cycle
■MTP memory (Multiple Time Programmable)
■Readout memory protection against piracy
The Flash program memory is organized in a single 8-bit wide memory block which can be used for storing both code and data constants.
The Flash program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area.
The Flash program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact.
An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification.
Remote ISP Overview
The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin.
The Remote ISP is performed in three steps:
–Selection of the RAM execution mode
–Download of Remote ISP code in RAM
–Execution of Remote ISP code in RAM to program the user program into the Flash
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied with power (VDD and VSS) and a clock signal (oscillator and application crystal circuit for example).
This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are:
–RESET: device reset
–VSS: device ground power supply
–ISPCLK: ISP output serial clock pin
–ISPDATA: ISP input serial data pin
–ISPSEL: Remote ISP mode selection. This pin
must be connected to VSS on the application board through a pull-down resistor.
If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level.
Figure 5 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description.
Figure 5. Typical Remote ISP Interface
|
|
|
HE10 CONNECTOR TYPE |
|
XTAL |
|
TO PROGRAMMING TOOL |
||
CL0 |
|
CL1 |
1 |
|
|
|
|||
OSC2 |
OSC1 |
DD |
ISPSEL |
|
10KΩ |
||||
V |
||||
VSS |
||||
|
|
|
||
|
|
|
RESET |
|
|
ST7 |
|
ISPCLK |
|
|
|
|
||
|
|
|
ISPDATA |
|
|
|
|
47KΩ |
|
|
|
|
APPLICATION |
The readout protection is enabled through an option bit.
For Flash devices, when this option is selected, the program and data stored in the Flash memory are protected against readout piracy (including a re-write protection). When this protection option is removed the entire Flash program memory is first automatically erased. However, the EEPROM data memory (when available) can be protected only with ROM devices.
18/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.
Figure 6. EEPROM Block Diagram
■Up to 16 bytes programmed in the same cycle
■EEPROM mono-voltage (charge pump)
■Chained erase and programming cycles
■Internal control of the global programming cycle duration
■End of programming cycle interrupt flag
■Wait mode management
|
|
|
|
|
|
FALLING |
|
|
EEPROM INTERRUPT |
|
|
|
EDGE |
|
|||
|
|
|
DETECTOR |
|
||||
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
HIGH VOLTAGE |
|
|
|
|
|
|
|
|
|
PUMP |
EECSR |
RESERVED |
|
|
EEPROM |
|
|||
0 |
0 |
0 |
0 |
IE |
LAT |
PGM |
|
|
0 |
|
|||||||
|
|
ADDRESS |
|
4 |
|
EEPROM |
||
|
|
|
ROW |
|
||||
|
|
DECODER |
|
|
|
MEMORY MATRIX |
||
|
|
|
|
DECODER |
|
|||
|
|
|
|
|
|
|
(1 ROW = 16 x 8 BITS) |
|
|
|
|
|
|
|
|
128 |
128 |
|
|
|
|
|
|
4 |
DATA |
16 x 8 BITS |
|
|
|
|
|
|
|
MULTIPLEXER |
DATA LATCHES |
|
|
|
|
|
|
4 |
|
|
|
ADDRESS BUS |
|
|
|
DATA BUS |
19/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
DATA EEPROM (Cont’d)
The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address.
Figure 7. Data EEPROM Programming Flowchart
When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched.
Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit.
It is not possible to read the latched data. This note is illustrated by the Figure 8.
READ MODE |
|
WRITE MODE |
|
LAT=0 |
|
LAT=1 |
|
PGM=0 |
|
PGM=0 |
|
READ BYTES |
WRITE UP TO 16 BYTES |
||
IN EEPROM AREA |
|||
IN EEPROM AREA |
|||
(with the same 11 MSB of the address) |
|||
|
|||
|
START PROGRAMMING CYCLE |
||
|
|
LAT=1 |
|
|
PGM=1 (set by software) |
||
INTERRUPT GENERATION |
|
|
|
IF IE=1 |
0 |
1 |
|
|
|
LAT |
CLEARED BY HARDWARE
20/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
DATA EEPROM (Cont’d)
6.4 POWER SAVING MODES Wait mode
The Data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller. The Data EEPROM will immediately enter this mode if there is no programming in progress, otherwise the Data EEPROM will finish the cycle and then enter Wait mode.
Halt mode
The Data EEPROM immediately enters Halt mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.
If a read access occurs while LAT=1, then the data bus will not be driven.
If a write access occurs while LAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guaranteed.
Figure 8. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE |
READ OPERATION POSSIBLE |
|
INTERNAL |
|
|
PROGRAMMING |
|
|
VOLTAGE |
|
|
ERASE CYCLE |
WRITE CYCLE |
|
WRITE OF |
|
|
DATA LATCHES |
tPROG |
|
|
|
|
|
|
LAT |
|
|
PGM |
|
|
EEPROM INTERRUPT |
21/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
DATA EEPROM (Cont’d)
6.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7 |
0 |
Bit 1 = LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared.
0:Read mode
1:Write mode
0 |
0 |
0 |
0 |
0 |
IE |
LAT |
PGM |
|
|
|
|
|
|
|
|
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 = IE Interrupt enable
This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine.
0:Interrupt disabled
1:Interrupt enabled
Bit 0 = PGM Programming control and status
This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ITE bit is set.
0:Programming finished or not yet started
1:Programming cycle is in progress
Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed
Table 3. Data EEPROM Register Map and Reset Values
Address |
Register |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
(Hex.) |
Label |
|||||||||
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
002Ch |
EECSR |
|
|
|
|
|
IE |
RWM |
PGM |
|
Reset Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
||
|
||||||||||
|
|
|
|
|
|
|
|
|
|
The Data EEPROM can be optionally readout protected in ST72334 ROM devices (see option list on
page 145). ST72C334 Flash devices do not have this protection option.
22/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
■63 basic instructions
■Fast 8-bit by 8-bit multiply
■17 main addressing modes
■Two 8-bit index registers
■16-bit stack pointer
■Low power modes
■Maskable hardware interrupts
■Non-maskable software interrupt
The six CPU registers shown in Figure 9 are not present in the memory mapping and are accessed by specific instructions.
Figure 9. CPU Registers
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
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ACCUMULATOR |
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RESET VALUE = XXh |
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X INDEX REGISTER |
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Y INDEX REGISTER |
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RESET VALUE = RESET VECTOR @ FFFEh-FFFFh |
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CONDITION CODE REGISTER |
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RESET VALUE = 1 |
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STACK POINTER |
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RESET VALUE = STACK HIGHER ADDRESS |
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X = Undefined Value
23/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
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The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.
0:No half carry has occurred.
1:A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.
0:Interrupts are enabled.
1:Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
24/150
Bit 2 = N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0:The result of the last operation is positive or null.
1:The result of the last operation is negative (that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0:The result of the last operation is different from zero.
1:The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0:No overflow or underflow has occurred.
1:An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15 |
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SP7 |
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SP4 |
SP3 |
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SP0 |
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The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 10).
Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
Figure 10. Stack Manipulation Example
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 10.
–When an interrupt is received, the SP is decremented and the context is pushed on the stack.
–On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
CALL |
Interrupt |
PUSH Y |
POP Y |
IRET |
RET |
Subroutine |
Event |
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or RSP |
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CC |
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CC |
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CC |
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SP |
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PCH |
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PCH |
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PCL |
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PCH |
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@ 01FFh PCL |
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Stack Higher Address = 01FFh
Stack Lower Address = 0100h
25/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
The ST72334J/N-Auto, ST72314J/N-Auto and ST72124J-Auto microcontrollers include a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11.
See Section 15 "ELECTRICAL CHARACTERISTICS" on page 108 for more details.
Main Features
■Supply Manager with main supply low voltage detection (LVD)
■Reset Sequence Manager (RSM)
■Multi-Oscillator (MO)
–4 Crystal/Ceramic resonator oscillators
–1 External RC oscillator
–1 Internal RC oscillator
■Clock Security System (CSS)
–Clock Filter
–Backup Safe Oscillator
Figure 11. Clock, Reset and Supply Block Diagram
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CLOCK SECURITY SYSTEM |
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OSC2 |
MULTI- |
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OSCILLATOR |
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RESET SEQUENCE |
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RESET |
MANAGER |
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WATCHDOG |
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VDD |
LOW VOLTAGE |
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LVD |
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CSS |
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RF |
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26/150 |
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
–VIT+ when VDD is rising
–VIT- when VDD is falling
The LVD function is illustrated in the Figure 12.
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes:
–under full software control
–in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
Notes:
1.The LVD allows the device to be used without any external RESET circuitry.
2.Three different reference levels are selectable through the option byte according to the application requirement.
LVD application note
Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register.
This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).
Figure 12. Low Voltage Detector vs Reset
VDD |
Vhyst |
VIT+ |
VIT- |
RESET |
27/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
8.2.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 14:
■External RESET source pulse
■Internal LVD RESET (Low Voltage Detection)
■Internal WATCHDOG RESET
The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock cycles.
Figure 13. RESET Sequence Phases
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at ad- |
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dresses FFFEh-FFFFh in the ST7 memory map. |
DELAY |
INTERNAL RESET |
FETCH |
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The basic RESET sequence consists of three |
4096 CLOCK CYCLES |
VECTOR |
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phases as shown in Figure 13: |
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■Delay depending on the RESET source
■4096 CPU clock cycle delay
■RESET vector fetch
Figure 14. Reset Block Diagram
VDD |
fCPU |
INTERNAL |
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RESET |
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COUNTER |
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RESET |
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WATCHDOG RESET |
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LVD RESET |
28/150
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
RESET SEQUENCE MANAGER (Cont’d)
8.2.2 Asynchronous External RESET Pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See ELECTRICAL CHARACTERISTICS section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the ELECTRICAL CHARACTERISTICS section.
Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 15).
Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
8.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■Power-On RESET
■Voltage Drop RESET
The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 15.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
8.2.4 Internal Watchdog RESET
The RESET sequence generated by an internal Watchdog counter overflow is shown in Figure 15.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
Figure 15. RESET Sequences
VDD |
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VIT+ |
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VIT- |
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LVD |
SHORT EXT. |
LONG EXT. |
WATCHDOG |
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RESET |
RESET |
RESET |
RESET |
RUN |
RUN |
RUN |
RUN |
RUN |
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DELAY |
DELAY |
DELAY |
DELAY |
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tw(RSTL)out |
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th(RSTL)in |
th(RSTL)in |
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tw(RSTL)out |
EXTERNAL |
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RESET |
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SOURCE |
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RESET PIN |
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WATCHDOG |
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RESET |
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INTERNAL RESET (4096 TCPU) |
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FETCH VECTOR |
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29/150 |
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
The main clock of the ST7 can be generated by four different source types coming from the multioscillator block:
■an external source
■4 crystal or ceramic resonator oscillators
■an external RC oscillator
■an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 4. Refer to the ELECTRICAL CHARACTERISTICS section for more details.
External Clock Source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.
External RC Oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is dependent on VDD, TA, process variations and the accuracy of the discrete components used. This option should not be used in applications that require accurate timing.
Internal RC Oscillator
The internal RC oscillator mode is based on the same principle as the external RC oscillator including the resistance and the capacitance of the device. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz. This option should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied to ground.
Table 4. ST7 Clock Sources
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Hardware Configuration |
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External Clock |
ST7 |
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OSC1 |
OSC2 |
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EXTERNAL |
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SOURCE |
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Resonators |
ST7 |
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OSC1 |
OSC2 |
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Crystal/Ceramic |
CL1 |
CL2 |
LOAD |
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CAPACITORS |
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RC Oscillator |
ST7 |
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OSC1 |
OSC2 |
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External |
REX |
CEX |
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Internal RC Oscillator |
ST7 |
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OSC1 |
OSC2 |
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30/150