ST ST72260G1, ST72262G1, ST72262G2, ST72264G1, ST72264G2 User Manual

8-BIT MCU WITH FLASH OR ROM MEMORY,

ADC, TWO 16-BIT TIMERS, I

■ Memories

– 4 K or 8 Kbytes Program memory: ROM or

Single voltage extended Flash (XFlash) with read-out protection write protection and InCircuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55°C.

– 256 bytes RAM

■ Clock, Reset and Supply Management

– Enhanced reset system – Enhanced low voltage supply supervisor

(LVD) with 3 programmable levels and auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures

– Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator and bypass for

external clock – PLL for 2x frequency multiplication – Clock-out capability – 4 Power Saving Modes: Halt, Active Halt,Wait

and Slow

■ Interrupt Management

– Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 22 external interrupt lines (on 2 vectors)

■ 22 I/O Ports

– 22 multifunctional bidirectional I/O lines – 20 alternate function lines – 8 high sink outputs

■ 4 Timers

– Main Clock Controller with Real time base and

Clock-out capabilities – Configurable watchdog timer

ST72260Gx, ST72262Gx,

ST72264Gx

C, SPI, SCI INTERFACES

SDIP32

LFBGA 6x6mm

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one timer, PWM and Pulse generator modes

■ 3 Communication Interfaces

– SPI synchronous serial interface

C multimaster interface (SMBus V1.1 Com-

–I

pliant)

– SCI asynchronous serial interface

■ 1 Analog peripheral

– 10-bit ADC with 6 input channels

■ Instruction Set

– 8-bit data manipulation – 63 basic instructions with illegal opcode de-

tection – 17 main addressing modes – 8 x 8 unsigned multiply instruction

■ Development Tools

– Full hardware/software development package

SO28

Device Summary

Features

Program memory - bytes 4K 4K 8K 4K 8K RAM (stack) - bytes 256 (128)

Peripherals

Operating Supply 2.7 V to 5.5 V CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 MHz

Operating Temperature -40° C to +85° C -40° C to +85° C

Packages SO28 / SDIP32 SO28 / SDIP32 LFBGA

ST72260G1 ST72262G1 ST72262G2 ST72264G1 ST72264G2

Watchdog timer, RTC,

Two16-bit timers, SPI

Watchdog timer, RTC,

Two 16-bit timers, SPI, ADC

Watchdog timer, RTC,

Two 16-bit timers, SPI, SCI, I2C, ADC

0° C to +70° C /

-40° C to +85° C

Rev. 3

June 2005 1/172

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.5 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.8 I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

172

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10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53

11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

11.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 153

13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

14.3 LEAD-FREE PACKAGE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 162

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 164

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

16.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

16.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

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ST72260Gx, ST72262Gx, ST72264Gx

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet Please note that the list of known limitations can be found at the end of this document on page 168.

4/172

1 INTRODUCTION

ST72260Gx, ST72262Gx, ST72264Gx

The ST72260Gx, ST72262Gx and ST72264Gx devices are members of the ST7 microcontroller family. They can be grouped as follows :

– ST72264Gx devices are designed for mid-range

applications with ADC, I

C and SCI interface ca-

pabilities.

– ST72262Gx devices target the same range of

applications but without I

– ST72260Gx devices are for applications that do

not need ADC, I

C peripherals or SCI.

C interface or SCI.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.

The ST72F260G, ST72F262G, and ST72F264G versions feature single-voltage FLASH memory with byte-by-byte In-Circuit Programming (ICP) capabilities.

Figure 1. General Block Diagram

Internal CLOCK

OSC1

OSC2

RESET

MULTI OSC

MCC/RTC

LVD

POWER SUPPLY

CONTROL

8-BIT CORE

ALU

Under software control, all devices can be placed in WAIT, SLOW, Active-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data is located in Section 13 on page 126.

2 PIN DESCRIPTION

Figure 2. 28-Pin SO Package Pinout

RESET

OSC1 OSC2

/PB7

SCK/PB6

MISO/PB5

MOSI/PB4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

/OCMP2_B/PC4

AIN4

AIN3

/ICAP2_B/PC3

Configurable by option byte

Alternate function not available on ST72260

Alternate function not available on ST72260 and ST72262

Figure 3. 32-Pin SDIP Package Pinout

RESET

OSC1 OSC2

/PB7

SCK/PB6 MISO/PB5 MOSI/PB4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5

/EXTCLK_A/PC5

/OCMP2_B/PC4

AIN4

/ICAP2_B/PC3

AIN3

Configurable by option byte

Alternate function not available on ST72260

Alternate function not available on ST72260 and ST72262

ei1 ei0

ei0 or ei1

ei1

ei0

ei1

ei0 or ei1

ICCSEL

PA0 (HS)/ICCCLK

PA1 (HS)/ICCDATA

PA2 (HS)

PA3 (HS)

PA4 (HS)/SCLI

PA5(HS)/RDI

PA6 (HS)/SDAI PA7 (HS)/TDO

PC0/ICAP1_B/AIN0

PC1/OCMP1_B/AIN1

PC2/MCO/AIN2

(HS) 20mA high sink capability eiX associated external interrupt vector

ICCSEL PA0 (HS)/ICCCLK PA1 (HS)/ICCDATA

PA2 (HS) PA3 (HS)

NC NC

PA4 (HS)/SCLI

PA5 (HS)/RDI

PA6 (HSI/SDAI PA7 (HS)/TDO PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1

PC2/MCO/AIN2

(HS) 20mA high sink capability eiX associated external interrupt vector

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PIN DESCRIPTION (Cont’d)

Figure 4. TFBGA Package Pinout (view through package)

123456

ST72260Gx, ST72262Gx, ST72264Gx

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ST72260Gx, ST72262Gx, ST72264Gx

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page

126.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

– Output: OD = open drain Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

Table 1. Device Pin Description

= CMOS 0.3 VDD/0.7 VDD with input trigger

, PP = push-pull

, ana = analog

Pin n°

Pin Name

BGA

SO28

SDIP32

1 1 A3 RESET I/O C

2 2 C4 OSC1

3 3 B3 OSC2

4 4 A2 PB7/SS

5 5 A1 PB6/SCK I/O C

6 6 B1 PB5/MISO I/O C

7 7 B2 PB4/MOSI I/O C

8 C1 NC

D1 NC

10 8 C3 PB3/OCMP2_A I/O C

11 9 D2 PB2/ICAP2_A I/O C

12 10 E1 PB1 /OCMP1_A I/O C

13 11 F1 PB0 /ICAP1_A I/O C

14 12 F2 PC5/EXTCLK_A/AIN5 I/O C

I/O C

Level Port / Control

Type

Input

Main

Input Output

Output

float

X ei1 X X Port B7 SPI Slave Select (active low)

X ei1 X X Port B6 SPI Serial Clock

X ei1 X X Port B5 SPI Master In/ Slave Out Data

X ei1 X X Port B4 SPI Master Out / Slave In Data

X ei1 X X Port B3 Timer A Output Compare 2

X ei1 X X Port B2 Timer A Input Capture 2

X ei1 X X Port B1

X ei1 X X Port B0

X ei0/ei1 X X X Port C5

int

wpu

ana

Function

(after

reset)

Top priority non maskable interrupt (active low)

External clock input or Resonator oscillator inverter input or resistor input for RC oscillator

Resonator oscillator inverter output or capacitor input for RC oscillator

Not Connected9 C2 NC

Alternate Function

Timer A Output Compare 1

Caution: Negative current injection not allowed on this pin

Timer A Input Capture 1

Caution: Negative current injection not allowed on this pin

Timer A Input Clock or ADC Analog Input 5

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ST72260Gx, ST72262Gx, ST72264Gx

Pin n°

Level Port / Control

Pin Name

Type

BGA

SO28

SDIP32

15 13 E2 PC4/OCMP2_B/AIN4 I/O C

16 14 F3 PC3/ ICAP2_B/AIN3 I/O C

17 15 E3 PC2/MCO/AIN2 I/O C

18 16 F4 PC1/OCMP1_B/AIN1 I/O C

19 17 D3 PC0/ICAP1_B/AIN0 I/O C

20 18 E4 PA7/TDO I/O C

21 19 F5 PA6/SDAI I/O C

22 20 F6 PA5 /RDI I/O C

23 21 E6 PA4/SCLI I/O C

24 E5 NC

D5 NC

26 22 C6 PA3 I/O C

27 23 D4 PA2 I/O C

C5 NC

B6 NC

28 24 A6 PA1/ICCDATA I/O C

29 25 A5 PA0/ICCCLK I/O C

30 26 B5 ICCSEL I C

31 27 A4 V

32 28 B4 V

S Ground

S Main power supply

Main

Function

(after

reset)

Alternate Function

Timer B Output Compare 2 or ADC Analog Input 4

Timer B Input Capture 2 or ADC Analog Input 3

Main clock output (f

CPU

) or

ADC Analog Input 2 Timer B Output Compare 1 or

ADC Analog Input 1 Timer B Input Capture 1 or

ADC Analog Input 0

Input Output

Input

Output

float

X ei0/ei1 X X X Port C4

X ei0/ei1 X X X Port C3

X ei0/ei1 X X X Port C2

X ei0/ei1 X X X Port C1

X ei0/ei1 X X X Port C0

wpu

int

ana

HS X ei0 X X Port A7 SCI output

HS X ei0 T Port A6 I2C DATA

HS X ei0 X X Port A5 SCI input

HS X ei0 T Port A4 I2C CLOCK

Not Connected25 D6 NC

HS X ei0 X X Port A3

HS X ei0 X X Port A2

Not Connected

HS X ei0 X X Port A1 In Circuit Communication Data

HS X ei0 X X Port A0

In Circuit Communication Clock

X ICC mode pin, must be tied low

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt input, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V are not implemented). See Section 9 "I/O PORTS" on page 38 for more details.

3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSCILLATOR (MO)" on

page 21 for more details.

4: For details refer to Section 13.8 on page 144

9/172

ST72260Gx, ST72262Gx, ST72264Gx

3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see Fig-

ure 5) mapped in the upper part of the ST7 ad-

Figure 5. Memory Map

0000h

007Fh 0080h

017Fh

0180h

HW Registers

(see Table 2)

RAM

(256 Bytes)

Reserved

dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte (refer to Sec-

tion 15.1 on page 162).

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming.

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming)

■ IAP (In-Application Programming)

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Sector 0 size configurable by option byte

■ Read-out and write protection against piracy

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways:

– Insertion in a programming tool. In this mode,

FLASH sectors 0 and 1 and option byte row can be programmed or erased.

– In-Circuit Programming. In this mode, FLASH

sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board.

– In-Application Programming. In this mode,

sector 1 can be programmed or erased without removing the device from the application

board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

– Download ICP Driver code in RAM from the

ICCDATA pin

– Execute ICP Driver code in RAM to program

the FLASH memory

Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

14/172

FLASH PROGRAM MEMORY (Cont’d)

ST72260Gx, ST72262Gx, ST72264Gx

4.4 ICC interface

ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These pins are:

– RESET –V

: device reset

: device power supply ground

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input serial data pin – ICCSEL: ICC selection (not required on devic-

es without ICCSEL pin)

– OSC1: main clock input for external source

(not required on devices without OSC1/OSC2 pins)

: application board power supply (option-

–V

al, see Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming

Figure 6. Typical ICC Interface

Tool documentation for recommended resistor values.

2. During the ICP session, the programming tool must control the RESET

pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

APPLICATION POWER SUPPLY

(See Note 3)

VDD

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

HE10 CONNECTOR TYPE

OPTIONAL (See Note 4)

OSC1

OSC2

ST7

975 3

10kΩ

VSS

ICCSEL

246810

RESET

ICCCLK

ICCDATA

APPLICATION BOARD

APPLICATION RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

15/172

ST72260Gx, ST72262Gx, ST72264Gx

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In flash devices, this protection is removed by reprogramming the option. In this case the program memory is automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

AN1477: Emulated data EEPROM with XFlash memory

AN1576: IAP drivers for ST7 HDFlash or XFlash MCUs

AN1575: On Board Programming methods for ST7 HDFlash or XFlash MCUs

AN1070: Checksum self checking capability

4.7 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)

00000OPTLATPGM

Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

16/172

5 CENTRAL PROCESSING UNIT

ST72260Gx, ST72262Gx, ST72264Gx

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 7. CPU Registers

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

RESET VALUE = XXh

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

1C1I1HI0NZ

1X11X1XX

PCL

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

17/172

ST72260Gx, ST72262Gx, ST72264Gx

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

11I1HI0NZ

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re-

sult 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

18/172

CENTRAL PROCESSING UNIT (Cont’d)

ST72260Gx, ST72262Gx, ST72264Gx

Stack Pointer (SP)

Read/Write Reset Value: 01 7Fh

15 8

00000001

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 128 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack

tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

higher address.

Figure 8. Stack Manipulation Example

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 0100h

@ 017Fh

X PCH PCL

PCH PCL

Stack Higher Address = 017Fh Stack Lower Address =

PCH PCL

0100h

X PCH PCL PCH PCL

X PCH PCL PCH

PCL

PCH

PCL

19/172

ST72260Gx, ST72262Gx, ST72264Gx

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10.

For more details, refer to dedicated parametric section.

Main Features

■ Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 4 Crystal/Ceramic resonator oscillators – 1 Internal RC oscillator

■ System Integrity Management (SI)

– Main supply Low Voltage Detector (LVD) – Auxiliary Voltage Detector (AVD) with inter-

rupt capability for monitoring the main supply

Figure 10. Clock, Reset and Supply Block Diagram

OSC2

OSC1

RESET

MULTI-

OSCILLATOR

(MO)

RESET SEQUENCE

MANAGER

(RSM)

OSC

PLL

(option)

SYSTEM INTEGRITY MANAGEMENT

AVD Interrupt Request

SICSR

AVD AVD

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the 2 to 4 MHz range, the PLL can be used to multiply the frequency by two to obtain an f

of 4 to 8 MHz.

OSC2

The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2 = fOSC

/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 139.

Figure 9. PLL Block Diagram

PLL OPTION BIT

SLOW MODE

SELECTION

MAIN CLOCK

CONTROLLER

WATCHDOG

TIMER (WDG)

OSC2

CPU

to CPU and Peripherals

LVD

OSC

PLL x 2

/ 2

MISCR1 Register

OSC2

WDG

WITH REALTIME

CLOCK (MCC/RTC)

20/172

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

6.2 MULTI-OSCILLATOR (MO)

ST72260Gx, ST72262Gx, ST72264Gx

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block:

■ an external source

■ 5 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 3. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effects Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an f

clock fre-

OSC

quency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 15.1 on page 162 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 12:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases

as shown in Figure 11:

■ Active Phase depending on the RESET source

■ 4096 CPU clock cycle delay (selected by option

byte)

■ RESET vector fetch

The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application.

Figure 12. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. RESET Sequence Phases

RESET

Active Phase

INTERNAL RESET

4096 CLOCK CYCLES

6.3.2 Asynchronous External RESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

FETCH

VECTOR

This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

RESET

Filter

PULSE

GENERATOR

INTERNAL RESET

WATCHDOG RESET

LVD RESET

22/172

RESET SEQUENCE MANAGER (Cont’d)

The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V level specified for the selected f

A proper reset signal for a slow rising V

is over the minimum

frequency.

OSC

supply can generally be provided by an external RC network connected to the RESET

pin.

Figure 13. RESET Sequences

ST72260Gx, ST72262Gx, ST72264Gx

6.3.4 Internal Low Voltage Detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 13.

The LVD filters spikes on V avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

pin acts as an output that is pulled

w(RSTL)out

IT+(LVD)

IT-(LVD)

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

RUN

LVD

RESET

ACTIVE PHASE

RUN

h(RSTL)in

EXTERNAL

RESET

ACTIVE PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (4096 T VECTOR FETCH

WATCHDOG

RESET

ACTIVE PHASE

w(RSTL)out

CPU

)

23/172

ST72260Gx, ST72262Gx, ST72264Gx

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains group the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1 on page 123 for further details.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the V below a V

reference value. This means that it

IT-

supply voltage is

secures the power-up as well as the power-down keeping the ST7 in reset.

The V than the V

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

is below:

–V

when VDD is rising

IT+

when VDD is falling

–V

IT-

The LVD function is illustrated in Figure 14. The voltage threshold can be configured by option

byte to be low, medium or high.

Provided the minimum V the oscillator frequency) is above V

value (guaranteed for

, the MCU

IT-

can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. The LVD is an optional function which can be se-

lected by option byte. Use of LVD with capacitive power supply: with this

type of power supply, if power cuts occur in the application, it is recommended to pull V

down to

0V to ensure optimum restart conditions. Refer to circuit example in Figure 91 on page 151 and note

6. It is recommended to make sure that the V

supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Figure 14. Low Voltage Detector vs Reset

IT+

IT-

RESET

24/172

hys

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a V erence value and the V

main supply. The V

IT-

and V

IT+

ref-

IT-

reference value for falling voltage is lower than the

reference value for rising voltage in order to

IT+

avoid parasitic detection (hysteresis). The output of the AVD comparator is directly read-

able by the application software through a real time status bit (VDF) in the SICSR register. This bit is read only.

Caution: The AVD functions only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the V

Main Supply

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 15.1 on page 162).

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V V

IT-(AVD)

threshold (AVDF bit toggles).

IT+(AVD)

ST72260Gx, ST72262Gx, ST72264Gx

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 15.

The interrupt on the rising edge is used to inform the application that the V

If the voltage rise time t CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V

is greater than 256 or 4096 cycles then:

If t

IT+(AVD)

is reached.

– If the AVD interrupt is enabled before the

IT+(AVD)

threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached.

– If the AVD interrupt is enabled after the V

threshold is reached then only one AVD interrupt will occur.

warning state is over.

is less than 256 or 4096

IT+(AVD)

Figure 15. Using the AVD to Monitor V

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

IT+(AVD)

IT-(AVD)

IT+(LVD)

IT-(LVD)

AVDF bit 0 0RESET VALUE

AVD INTERRUPT REQUEST

IF AVDIE bit = 1

LVD RESET

hyst

INTERRUPT PROCESS

VOLTAGE RISE TIME

INTERRUPT PROCESS

25/172

ST72260Gx, ST72262Gx, ST72264Gx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Low Power Modes

Mode Description

WAIT

HALT The SICSR register is frozen.

6.4.3.1 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

set and the interrupt mask in the CC register is reset (RIM instruction).

Flag

Enable

Control

Bit

Interrupt Event

AVD event AVDF AVDIE Yes No

Event

Exit from Wait

Exit

from

Halt

26/172

ST72260Gx, ST72262Gx, ST72264Gx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write Reset Value: 000x 000x (00h)

AVDIEAVDFLVD

000

WDG

Bit 7 = Reserved, always read as 0.

Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. 0: V 1: V

over V

under V

IT+(AVD)

IT-(AVD)

threshold

Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See

WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

Bit 3:1 = Reserved, must be kept cleared.

Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET

Watchdog 0 1

LVD 1 X

pin 0 0

Application Notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

Address

(Hex.)

0025h

Label

SICSR

Reset Value 0

76543210

AVDIE0AVDF0LVDRF

x000

WDGRF

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ST72260Gx, ST72262Gx, ST72264Gx

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non-maskable events: RESET and TRAP

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 4). The processing flow is shown in Figure 16

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 4. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main) Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

Low

High

Figure 16. Interrupt Processing Flowchart

RESET

RESTORE PC, X, A, CC

FROM STACK

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PENDING

INTERRUPT

FETCH NEXT

INSTRUCTION

“IRET”

EXECUTE

INSTRUCTION

THE INTERRUPT STAYS PENDING

Interrupt has the same or a

lower software priority

than current one

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

I1:0

software priority

than current one

Interrupt has a higher

INTERRUPTS (Cont’d)

ST72260Gx, ST72262Gx, ST72264Gx

Servicing Pending Interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 17 describes this decision process.

Figure 17. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET and TRAP are non-maskable and they can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET and TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 16). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart on Figure 16 as a TLI.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the Miscellaneous registers (MISCRx). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt vector request an interrupt simultaneously, the interrupt vector will be serviced. Software can read the pin levels to identify which pin(s) are the source of the interrupt.

If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

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ST72260Gx, ST72262Gx, ST72264Gx

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 17.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 18. Concurrent Interrupt Management

IT1

IT3

TLI

IT0

TLI

IT1

RIM

IT2

IT1

IT4

HARDWARE PRIORITY

MAIN

11 / 10

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 18 and Figure 19 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in

Figure 19. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

Note: TLI (Top Level Interrupt) is not available in this product.