ST ST72260G, ST72262G, ST72264G User Manual

Download

查询ST72260G1供应商

ST72260G, ST72262G,

ST72264G

8-BIT MCU WITH FLASH OR ROM MEM ORY,

ADC, TWO 16-BIT TIMERS, I

■ Memories

– 4 K or 8 Kby tes Program memory: ROM or

Single voltage extended Flash (XFlash) with read-out protection write protection and InCircuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55°C.

– 256 bytes RAM

■ Clock, Re set and Supp ly Managem ent

– Enhanced reset system – Enhanced low voltage supply supervisor

(LVD) with 3 programmable levels and auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures

– Clock sources: crystal/ceramic resonat or os-

cillators , internal RC os cillator, clock se curity

system and bypass for external clock – PLL for 2x frequency multiplication – Clock-out capability – 4 Power Saving Modes: Halt, Active Halt,Wait

and Slow

■ Interrupt Management

– Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 22 external interrupt lines (on 2 vectors)

■ 22 I/ O P o rts

– 22 multifunctional bidirectional I/O lines – 20 alternate function lines – 8 high sink outputs

■ 4 Timers

– Main Clock Controller with Real time base and

Clock-out capabilities – Configurable watchdog timer

Device Summary

Features

Program memory - bytes 4K 4K 8K 4K 8K RAM (stack) - bytes 256 (128)

Periphe rals

Operating Supply 2.4 V to 5.5 V CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 Mhz Operating Temperature -40° C to +85° C 0° C to +70° C Packages SO28 / SDIP32 LFBGA

ST72260G1 ST72262G1 ST72262G2 ST72264G1 ST72264G2

Watchdog timer,

RTC,

Two16-bit timers,

SPI

Watchdog timer, RTC

Two 16-bit timers,

SPI, ADC

C, SPI, SCI INTERFACES

SDIP32

LFBGA 6x6mm

SO28

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one timer, PWM and Pulse generator modes

■ 3 Communications Interfaces

– SPI synchronous serial interface

C multimaster interface

–I – SCI asynchronous serial interface (LIN com-

patible)

■ 1 Analog peripheral

– 10-bit ADC with 6 input channels

■ Instruction Set

– 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction

■ Development Tools

– Full hardware/software development package

Watchdog timer, RT C

Two 16-bit timers ,

SPI, SCI, I

C, ADC

Rev. 1.7

August 2003 1/171

Table of Contents

ST72260G, ST72262G,

ST7226 4G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.5 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

171

2/171

Table of Contents

9.8 I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53

11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

11.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149

13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 157

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 159

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

3/171

ST72260G, ST72262G, ST72264G

17 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

18 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19.2 I/O PORT B AND C CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19.3 16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.4 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.5 MINIMUM OPERATING VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.6 CSS FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.7 INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD . . . . . . . . . . . . . . . . . . . . 167

19.8 EXTERNAL CLOCK WITH PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.9 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . 168

19.10 ACTIVE HALT WAKE-UP BY EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 168

19.11 A/D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . . 168

19.12 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 168

19.13 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

19.14 FUNCTIONAL EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

20 DEVICE MARKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

21 ERRATA SHEET REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet Please note that an errata sheet can be found at the end of this document on page 166.

4/171

1 INTRODUCTION

ST72260G, ST72262G, ST72264G

The ST72260G, ST72262G and ST72264G devices are members of the ST7 microcontroller family. They can be grouped as follows :

– ST72264G devices are designed for mid-range

applications with ADC, I

C and SCI interface ca-

pabilities.

– ST72262G devices target the same range of ap-

plications but without I

– ST72260G devices are for applications that do

not need ADC, I

C interface or SCI.

C peripherals or SCI.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.

The ST72F260G, ST72F262G, and ST72F264G versions feature single-voltage FLASH memory

Figure 1. General Block D iagram

Internal

OSC1 OSC2

RESET

MULTI OSC

CLOCK F ILTE R

MCC/RTC

LVD

POWER SUPPLY

CONTROL

8-BIT CO RE

ALU

CLOCK

with byte-by-byte In-Circuit Programming (ICP) capabilities.

Under software control, all devices can be placed in WAIT, SLOW, Ac tive-HALT or H ALT mode, reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data is locat ed in Section 13 on page 122.

I2C*

SCI*

PA7:0

PORT A

ICD

ADDRESS AND DATA BUS

SPI

PORT B

16-BIT TIMER A

(8 bits)

PB7:0

(8 bits)

PROGRAM

MEMORY

(4 or 8K Bytes)

RAM

(256 Bytes)

*Not avai l abl e on some de vices, see devi ce summar y on page 1.

PORT C

10-BIT ADC*

16-BIT TIMER B

WATCHDOG

PC5:0

(6 bits)

5/171

ST72260G, ST72262G, ST72264G

2 PIN DESCRI PTION

Figure 2. 28-Pin SO Package Pinout

RESET

OSC1 OSC2

/PB7

SCK/PB6 MISO/PB5 MOSI/PB4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

/OCMP2_B/PC4

AIN4

AIN3

/ICAP2_B/PC3

Configur abl e by optio n byte

Alternate function not available on S T 72260

Alternate function not available on S T 72260 and ST72262

Figure 3. 32-Pin SDIP Package Pinout

RESET

OSC1 OSC2

/PB7

SCK/PB6 MISO/PB5 MOSI/PB4

NC NC

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN52/EXTCLK_A/PC5

/OCMP2_B/PC4

AIN4

/ICAP2_B/PC3

AIN3

Confi gu rable by option byte

Alternate function not available on ST72260

Alternate function not available on ST72260 and ST72262

1 2 3 4 5 6 7 8 9 10 11 12 13

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ei1 ei0

ei0 or ei1

ei1

ei0

ei1

ei0 or ei1

ICCSEL

(HS)/ICCCLK

PA0

(HS)/ICCDATA

PA1

PA2

23 22 21 20 19 18 17

16 15

32 31 30 29 28 27 26 25 24 23 22 21 20 19

18 17

(HS) PA3 (HS) PA4 (HS)/SCLI PA5(HS)/RDI PA6 (HS)/SDAI PA7 (HS)/TDO PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/MCO/AIN2

(HS) 20mA high sink capability eiX associated external interrupt vector

ICCSEL PA0 (HS)/ICCCLK PA1 (HS)/ICCDATA PA2 (HS) PA3 (HS) NC

PA4 (HS)/SCLI PA5 (HS)/RDI PA6 (HSI/SDAI

PA7 (HS)/TDO PC0/ICAP1_B/A IN0 PC1/OCMP1_B /AIN1

PC2/MCO/AIN2

(HS) 20mA high sink capability eiX associated external interrupt vector

6/171

Figure 4. TFBGA Package Pinout (view through package)

123456

ST72260G, ST72262G, ST72264G

7/171

ST72260G, ST72262G, ST72264G

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page

122.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output lev e l: C Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

– Output: OD = open drain Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET confi g ur at ion of each pin is sho wn in b o ld. This configura ti o n is valid as long as t h e device is

in reset state.

Table 1. Device Pin Description

= CMOS 0.3 VDD/0.7 VDD with input trigger

, PP = push-pull

, ana = analog

Pin n°

Level Port / Control

Pin Name

Type

BGA

SO28

SDIP32

1 1 A3 RESET I/O C

2 2 C4 OSC1

3 3 B3 OSC2 4 4 A2 PB7/SS

I/O C

5 5 A1 PB6/SCK I/O C 6 6 B1 PB5/MISO I/O C 7 7 B2 PB4/MOSI I/O C 8 C1 NC

D1 NC 10 8 C3 PB3/OCMP2_A I/O C 11 9 D2 PB2/ICAP2_A I/O C 12 10 E1 PB1 /OCMP1_A I/O C 13 11 F1 PB0 /ICAP1_A I/O C

14 12 F2 PC5/EXTCLK_A/AIN5 I/O C

15 13 E2 PC4/OCMP2_B/AIN4 I/O C

16 14 F3 PC3/ ICAP2_B/AIN3 I/O C

Input

Main

Function

(after

reset)

Alternate Function

Top priority non maskable interrupt (active low)

Input Output

Output

float

wpu

int

ana

External clock input or Resonator oscillator inverter input or resistor input for RC oscillator

Resonator oscillator inverter output or capacitor input for RC oscillator

X ei1 X X Port B7 SPI Slave Select (active low)

X ei1 X X Port B6 SPI Serial Clock

X ei1 X X Port B5 SPI Master In/ Slave Out Data

X ei1 X X Port B4 SPI Master Out / Slave In Data

Not Connected9 C2 NC

X ei1 X X Port B3 Timer A Output Compare 2

X ei1 X X Port B2 Timer A Input Capture 2

X ei1 X X Port B1 Timer A Output Compare 1

X ei1 X X Port B0 Timer A Input Capture 1

X ei0/ei1 X X X Port C5

X ei0/ei1 X X X Port C4

X ei0/ei1 X X X Port C3

Timer A Input Clock or ADC Analog Input 5

Timer B Output Compare 2 or ADC Analog Input 4

Timer B Input Capture 2 or ADC Analog Input 3

8/171

ST72260G, ST72262G, ST72264G

Pin n°

SDIP32

SO28

Pin Name

BGA

Level Port / Control

Type

17 15 E3 PC2/MCO/AIN2 I/O C

18 16 F4 PC1/OCMP1_B/AIN1 I/O C

19 17 D3 PC0/ICAP1_B/AIN0 I/O C 20 18 E4 PA7/TDO I/O C

21 19 F5 PA6/SDAI I/O C 22 20 F6 PA5 /RDI I/O C 23 21 E6 PA4/SCLI I/O C

T T T T

24 E5 NC

D5 N C 26 22 C6 PA3 I/O C 27 23 D4 PA2 I/O C

T T

C5 NC

B6 NC 28 24 A6 PA1/ICCDATA I/O C

29 25 A5 PA0/ICCCLK I/O C 30 26 B5 ICCSEL I C

31 27 A4 V 32 28 B4 V

SS DD

S Ground S Main power supply

Main

Input

Input Output

Output

float

X ei0/ei1 X X X Port C2

X ei0/ei1 X X X Port C1

X ei0/ei1 X X X Port C0

wpu

int

ana

Function

(after

reset)

Alternate Function

Main clock output (f

CPU

) or

ADC Analog Input 2 Timer B Output Compare 1 or

ADC Analog Input 1 Timer B Input Capture 1 or

ADC Analog Input 0

HS X ei0 X X Port A7 SCI output HS X ei0 T Port A6 I2C DATA HS X ei0 X X Port A5 SCI input HS X ei0 T Port A4 I2C CLOCK

Not Connected25 D6 NC

HS X ei0 X X Port A3 HS X ei0 X X Port A2

Not Connected

HS X ei0 X X Port A1 In Circuit Communication Data HS X ei0 X X Port A0

In Circuit Communication Clock

X ICC mode pin, must be tied low

Notes:

1. In the interrupt input column, “eiX ” define s the asso ciated exte rnal interrupt vec tor. If the weak pul l-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt input, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V are not implemented). See Section 9 "I/O PORTS" on page 38 for more details.

3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see S ection 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSC ILLA-

TOR (MO)" on page 21 for more details.

9/171

ST72260G, ST72262G, ST72264G

3 REGISTER & MEMORY MAP

As sho wn in Figure 5, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the sta ck from 0100h to 017Fh.

The highest address b ytes contain the user reset and interrupt vectors.

The Flash memory c on tains tw o sectors (s ee Fig-

ure 5) mapped i n the upper part of the ST7 ad-

Figure 5. Me m ory Map

0000h

007Fh 0080h

017Fh

0180h

HW Registers

(see Table 2)

RAM

(256 Bytes)

Reserved

dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte (refer to Sec-

tion 15.1 on page 157).

IMPORTANT: Memory locations marked as “Reserved” must neve r be ac cess ed. A cce ssing a reseved area c an have unpredictable effects on t he device.

0080h

00FFh 0100h

017Fh

Short Addressing RAM

Zero page

(128 Bytes)

Stack or

16-bit Addressing RAM

(128 Bytes)

8K FLASH

PROGRAM MEMORY

10/171

DFFFh

E000h

FFDFh

FFE0h

FFFFh

Program Memory

(4K, 8 KBytes)

Interrupt & Reset Vectors

(see Table 5 on page 32)

E000h

EFFFh

F000h

FFFFh

4 Kbytes

SECTOR 1

4 Kbytes

SECTOR 0

Table 2. Hardware Register Map

ST72260G, ST72262G, ST72264G

Address Block

0000h 0001h

Port C

0002h

Label

PCDR PCDDR PCOR

Port C Data Register Port C Data Direction Register

Port C Option Register 0003h Reserved (1 Byte) 0004h

0005h 0006h

Port B

PBDR PBDDR PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register 0007h Reserved (1 Byte)

0008h 0009h 000Ah

Port A

PADR PADDR PAOR

Port A Data Register

Port A Data Direction Register

Port A Option Register 000Bh

Reserved (17 Bytes)

001Bh 001Ch

001Dh 001Eh 001Fh

ITC

ISPR0 ISPR1 ISPR2 ISPR3

Interrupt software priority register0

Interrupt software priority register1

Interrupt software priority register2

Interrupt software priority register3

Reset

Status

xx000000h

00h 00h

00h

00h 00h

00h

00h 00h

FFh FFh FFh FFh

Remarks

R/W

R/W R/W R/W.

R/W R/W

R/W

R/W R/W R/W

R/W 0020h MISCR1 Miscellanous register 1 00h R/W 0021h

0022h 0023h

SPI

SPIDR SPICR SPICSR

SPI Data I/O Register SPI Control Register SPI Status Register

xxh 0xh 00h

R/W

R/W 0024h WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

0025h SICSR System Integrity Control / Status Register 000x 000x R/W 0026h MCC MCCSR Main Clock Control / Status Register 00h R/W 0027h Reserved (1 Byte)

0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh

002Fh 0030h

I2CCR I2CSR1

I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR

C Control Register

C Status Register 1

C Status Register 2

C Clock Control Register

C Own Address Register 1

C Own Address Register2

C Data Register

00h 00h 00h 00h 00h 40h 00h

Reserved (2 Bytes)

R/W Read Only Read Only R/W R/W R/W R/W

11/171

ST72260G, ST72262G, ST72264G

Address Block

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h

TIMER A 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

Label

TACR2 TACR1 TASCSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

Reset

Status

00h 00h xxh xxh xxh 80h 00h

FFh FCh FFh FCh

xxh

80h

00h

0040h MISCR2 Miscellanous register 2 00h R/W 0041h

0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

TIMER B

TBCR2 TBCR1 TBSCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

00h

xxh

80h

00h FFh FCh FFh FCh

xxh

80h

00h

Remarks

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0050h 0051h 0052h 0053h 0054h 0055h 0056h

SCI

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register1 SCI Control Register2 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register

C0h

xxh

00h

x000 0000h

00h

Read Only R/W R/W R/W R/W R/W R/W

0057h

Reserved (24 Bytes)

006Eh 006Fh

0070h 0071h

ADC

ADCDRL ADCDRH ADCCSR

Data Register Low Data Register High Control/Status Register

00h

Read Only Read Only

R/W 0072h FLASH FCSR F lash Contr ol Register 00h R/W 0073h

Reserved (13 Bytes)

007Fh

12/171

ST72260G, ST72262G, ST72264G

Legend: x=Unde fined, R/W=R e ad/Write Notes:

1. The contents of the I/O p ort DR registers are readable only i n out put c onf iguration. I n i nput c onf iguration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. For compatibility with the ST72C254, the ADCDRL and ADCDRH data registers are located with the LSB on the lower address (6Fh) and the MSB on the higher address (70h). As this scheme is not little Endian, the ADC data registers cannot be treated by C programs as an integer, but have to be treated as two char registers.

13/171

ST72260G, ST72262G, ST72264G

4 FLASH PROGRAM MEMO RY

4.1 In troduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a by te-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming.

The array matrix organ isation allows each sector to be erased and reprogrammed wi thout affecting other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming)

■ IAP (In-Application Programming)

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Sector 0 size configurable by option byte

■ Read-out and write protection against piracy

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways:

– Insertion in a programming tool. In this mode,

FLASH sectors 0 and 1 and op tion byte row can be programmed or erased.

– In-Circuit Programming. In this mode, FLAS H

sectors 0 and 1 and op tion byte row can be programmed or erased without removing the device from the application board.

– In-Application Programming. In this mode,

sector 1 can be programme d or erased without removing the device from the application

board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP us es a pr ot o c ol c al l e d I CC ( I n- Ci r c ui t C om mu nication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

– Download ICP Driver cod e in RAM from the

ICCDATA pin

– Execute ICP Driver code in RAM to program

the FLASH memory

Depending on the ICP Driver code downloaded in RAM, FLASH memo ry programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of c om mun ications protoc ol used t o fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

14/171

FLASH PROGRAM MEMORY (Cont’d)

ST72260G, ST72262G, ST72264G

4.4 ICC interface

ICP needs a minimum of 4 and u p to 7 pins to be connected to the programming tool. These pins are:

– RESET –V

: device reset

: device power supply ground

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input serial data pin – ICCSEL: ICC selection (not required on devic-

es without ICCSEL pin)

– OSC1: main clock input for external source

(not required on devices without OSC1/OSC2 pins)

: application board power supply (option-

–V

al, see Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only use d as outputs in the application, no sign al iso lation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming

Figure 6. Typical ICC Interface

Tool documentation for recommended resistor values.

2. During the ICP session, the programming tool must contr o l the RESET

pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be u sed to isolate t he application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain outpu t and pull-up resistor>1K, no additional com ponents are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connec tor depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not avai lable in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

APPLICATION POWER SUPPLY

OPTIONAL (See Note 3)

VDD

OSC2

OPTIONAL (See Note 4)

OSC1

ST7

PROGRAMMING TOOL

ICC CONNECTOR

ICC Ca ble

ICC CONNECTOR

HE10 CONNECTOR TYPE

975 3

10kΩ

VSS

RESET

ICCSEL

ICCCLK

1 246810

ICCDATA

APPL ICATION BOARD

APPLICATION RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

15/171

ST72260G, ST72262G, ST72264G

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read out Protection

Read out protection, when selected, makes it impossible to extract the m emory content from the microcontroller, thus preventing piracy.

In flash devices, this protection is removed by reprogramming the option. In this case the program memory is automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent a ny change bei ng mad e to the memory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)

00000OPTLATPGM

Note: This register is reserved for programming using ICP, IAP or other program ming methods. It controls the XFlash p ro grammin g and erasing operations. For details on XFlash programming, refer to the ST7 Flash Programming Reference Manual.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS k eys are sent automatically.

16/171

5 CENTRAL PRO CESSING UNIT

ST72260G, ST72262G, ST72264G

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 7. CPU Registers

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specifi c ins t r uc tions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operan ds and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as tempora ry storage areas f or dat a manipulation. (The Cross-A ssembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Cou nt er (P C )

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

RESET VALUE = XXh

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

70 1C1I1HI0NZ

1X11X1XX 70

PCL

ACCUMULA T OR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

17/171

ST72260G, ST72262G, ST72264G

CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

11I1HI0NZ

The 8-bit Condition Code register c ontains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or ADC instructions. It is reset by hardware during the same instruction s.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines .

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. I t’s a copy of the re-

sult 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z

Zero

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions. Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Managem ent B i ts

Bit 5,3 = I1, I0

Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priorit y I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared b y hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

18/171

CENTRAL PROCESSING UNIT (Cont’d)

ST72260G, ST72262G, ST72264G

Stack Pointer (SP)

Read/Write Reset Value: 01 7Fh

15 8

00000001

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, wi thout indicating the s tack overflow. The previously stored information is then o verwritten and therefore lost. The stack also wraps in case of an underflow.

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The stack is used to save the retu rn address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 128 bytes deep, the 8 most significant bits are forced by hardw are. Following a n MCU Reset, or after a Reset Stack Pointe r instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack

tions. In the case of an interrupt, the PCL is stored at the first location point ed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locat ions i n the sta ck ar ea.

higher address.

Figure 8. Stack Manipulation Example

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 0100h

@ 017Fh

X PCH PCL

PCH PCL

Stack Higher Address = 017Fh Stack Lower Address =

PCH

PCL

0100h

A X

PCH

PCL PCH PCL

X PCH PCL PCH

PCL

PCH PCL

19/171

ST72260G, ST72262G, ST72264G

6 SUPPLY, RESET AND CLOCK M ANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10.

For more details, refer to dedicated parametric section.

Main Features

■ Optional PLL for multiplying th e frequency by 2

(not to be used with internal RC oscillator)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 4 Crystal/ C e ra m ic res on ator oscilla t or s – 1 Internal R C os c illa t or

■ System Integrity Management (SI)

– Main supply Low Voltage Detector (LVD) – Auxiliary Voltage Detector (AVD) with inter-

rupt capability for monitori ng the main s upply

– Clock Security System (CSS) wi th Clo ck Filter

and Backup Safe Oscillator (enabled by option byte)

Figure 10. Clock, Reset and Supply Block Diagram

SYSTEM INTEGRITYMANAGEMENT

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the 2 to 4 MHz range, the P LL can be used to mu ltiply the frequency by two to obtain an f

of 4 to 8 MHz.

OSC2

The PLL is enable d by option byte. If the PLL is disabled, then f

OSC2 = fOSC

/2.

Caution: T he PLL is not recom mended for applications where timing accuracy is required. See “PLL Characteristics” on page 134.

Figure 9. PLL Block Diagram

OSC

PLL x 2

/ 2

PLL OPTION BIT

OSC2

OSC1

RESET

MULTI-

OSCILLATOR

(MO)

RESET SEQUENCE

MANAGER

(RSM)

OSC

PLL

(option)

OSC2

CLOCK SECURITYSYSTEM

CLOCK FILTER

SICSR

AVD AVD

(CSS)

AVD Interrupt Requ est

LVD

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

SAFE

OSC

CSS

IEIE

CSS Interrupt Request

OSC2

CSSDWDG

MAIN CLOCK

CONTRO LLER

WITH REALTIME

CLOCK ( MCC/RTC)

WATCHDOG

TIMER (WDG )

CPU

20/171

6.2 MULTI-OSCILLATOR (MO)

ST72260G, ST72262G, ST72264G

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block:

■ an external source

■ 5 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequenc y range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 3. Refer to the electrical characteristics section for more details.

Caution: The OS C1 and/or OSC2 pins must not be left unconnected. For th e purposes of Failure Mode and Effects Analysis, it should be noted that if the OSC1 and/or OSC2 pin s are left unconnec ted, the ST7 main oscillat or may start and, in this configuration, could generate an f

clock fre-

OSC

quency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The select ion within a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce c onsumption (refer to Se ction 15.1 on page 157 for more details o n the frequency ranges). In this mode of the m ultioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscilla tor .

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacit or. Int er nal R C os cillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing .

In this mode, the two oscillator pins have to be tied to ground.

Table 3. ST7 Clock Sources

Hardware Configur ation

ST7

OSC1 OSC2

External ClockCrystal/Cera mic ResonatorsInternal RC Oscillator

EXTERNAL

SOURCE

OSC1 O SC2

CAPACITORS

OSC1 OSC2

ST7

LOAD

ST7

21/171

ST72260G, ST72262G, ST72264G

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introd uct i on

The reset sequence manager in cludes three RESET sources as shown in Figure 12:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET s eque nc e cons i sts o f 3 p has es

as shown in F igure 11:

■ Active Phase depending on the RESET source

■ 4096 CPU clock cycle delay (selected by option

byte)

■ RESET vector fetch

The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabiliza tion time of the external oscillator used in the appl icat ion.

Figure 12. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. RESET Sequence Phases

RESET

Active Phase

INTERNAL RESET

4096 CLOCK CYCLES

6.3.2 Async hronous External R ESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

FETCH

VECTOR

This pull-up has no f ixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

RESET

Filter

PULSE

GENERATOR

INTERNAL RESET

WATCHDOG RESE T LVD RESET

22/171

RESET SEQUENCE MANAGER (Cont’d) The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electr ical characteristics section.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up t he microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V level specified for the selected f

A proper reset signal for a slow rising V

is over the m inimum

frequency.

OSC

supply

can generally be provide d by an ex ternal RC network connected to the RESET

pin.

Figure 13. RESET Sequences

ST72260G, ST72262G, ST72264G

6.3.4 Internal Low Voltage Detector (LVD) RESET

Two differen t RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 13.

The LVD filters spikes on V avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

pin acts as an output that is pulled

w(RSTL)out

IT+(LVD)

IT-(LVD)

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

RUN

LVD

RESET

ACTIVE PHASE

RUN

h(RSTL)in

EXTERNAL

RESET

ACTIVE PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (4096 T VECTOR FETCH

WATCHDO G

RESET

ACTIVE PHASE

w(RSTL)out

CPU

)

23/171

ST72260G, ST72262G, ST72264G

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Managem ent block contains group the Low voltage Detector (LVD), Auxiliary Voltage Detector (AVD) and Clock Security System (CSS) functions. It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector funct ion (LVD) generates a static reset when the V below a V

reference value. This means that it

IT-

supply voltage is

secures the power-up as well as the power-down keeping the ST7 in reset.

The V than the V

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

is below:

when VDD is rising

–V

IT+

–V

when VDD is falling

IT-

The LVD func t ion is illustrated in F igure 14.

Figure 14. Low Voltage Detector vs Reset

The voltage threshold can be configured by option byte to be low, medium or high.

Provided the minimum V the oscillator frequency) is above V

value (guaranteed for

, the MCU

IT-

can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus p ermitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. The LVD is an optional function whi ch can be se-

lected by option byte.

V V

RESET

IT+

IT-

hys

24/171

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a V erence value and the V

main supply. The V

and V

IT-

IT+

ref-

IT-

reference value for falling voltage is lower than the V

reference value for rising voltage in order to

IT+

avoid parasitic detection (hysteresis). The output of the AVD comparator is directly read-

able by the application software through a real time status bit (VDF) in the SICSR register. This bit is read only.

Caution: The AVD functions only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the V

Main Su pply

The AVD voltage threshold value is relative to the selected LVD threshold configured by opt ion byte (see Section 15.1 on page 157).

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V V

IT-(AVD)

threshold (AVDF bit toggles).

IT+(AVD)

ST72260G, ST72262G, ST72264G

In the case of a drop in voltage, the AVD i nterrupt acts as an early warning, allowing software to shut down safely before the LVD re sets the microcontroller. See Figure 15 .

The interrupt on the rising edge is used to inform the application that the V

If the voltage rise time t CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V

is greater than 256 or 4096 cycles then:

If t

IT+(AVD)

is reached.

– If the AVD interrupt is enabled before the

IT+(AVD)

threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached.

– If the AVD interrupt is enabled after the V

threshold is reached then only one AVD interrupt will occur.

warning state is over.

is less than 256 or 4096

IT+(AVD)

Figure 15. Using the AVD to Monitor V

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

IT+(AVD)

IT-(AVD)

IT+(LVD)

IT-(LVD)

AVDF bit 0 0RESET VALUE

AVD INTERRUPT REQUEST IF AVDIE bit = 1

LVD RESET

hyst

INTERRUPT PROCESS

VOLTAGE RISE TIME

INTERRUPT PROCESS

25/171

ST72260G, ST72262G, ST72264G

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and overfrequencies occurring on the main clock source (f is based on a clock filter and a clock detection control with an internal safe oscillator (f

SFOSC

6.4.3.1 Clock Filter Control

The PLL has an integrated glitch filtering capability making it possible to protect the internal clock from overfrequencies created by individual spikes. This feature is available only when the P LL is enabled. If glitches occur on f

(for example, due to loose

OSC

connection or noise), the CSS filters these automatically, so the internal CPU frequency (f continues deliver a glitch-free signa l (see Figure

16).

6.4.3.2 Clock detection Control

If the clock signal disappears (due to a broken or disconnected resona tor...), the safe osc illator delivers a low frequency clock signal (f

SFOSC

allows the ST7 to perform some rescue operations.

Automatically, the ST7 clock source switches back from the safe o scillator (f source (f

) recovers.

OSC

When the internal clock (f oscillator (f

), the application software is noti-

SFOSC

) if the main clock

SFOSC

) is driven by the safe

CPU

fied by hardware setting the CSSD bit i n the SICSR register. An interrupt can be generated if the

OSC

CPU

) whi c h

). It

CSSIE bit has been previously set. These two bits are described in the SICSR register description.

6.4.4 Low Power Modes

Mode Description

WAIT

HALT

)

No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.

The SICSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

6.4.4.1 Interrupts

The CSS or AVD i nterrupt events generat e an interrupt if the corresponding Enable Control Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

Flag

Enable

Control

Bit

Interrupt Event

CSS event detection (safe oscillator activated as main clock)

AVD event AVDF AVDIE Yes No

Event

CSSD CSSIE Yes No

Exit from Wait

Exit

from

Halt

Figure 16. Clock Filter Function

Clock Filter Function

OSC2

PLL ON

CPU

Clock Detection Function

OSC2

SFOSC

CPU

26/171

ST72260G, ST72262G, ST72264G

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.5 Register Description SYSTEM INTEGRITY (SI) CONTROL/ STATUS REGISTER (SICSR)

Read/Write Reset Value: 000x 000x (00h)

AVDIEAVDFLVD

CSSIECSSDWDG

Bit 7 = Reserved, always read as 0.

Bit 6 = AVDIE

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled

Bit 5 = AVDF

Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value.

over V

0: V

under V

1: V

Bit 4 = LV DRF

IT+(AVD)

threshold

IT-(AVD)

threshold

LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE

Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance is detected by the Clock Security System (CSSD

bit set). It is set and cleared by software. 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled When the CSS is di sabled by O PTIO N B YTE, t he CSSIE bit has no effect.

Bit 1 = CSSD

Clock security system detecti o n

This bit indicates that the safe oscillator of the Clock Security System block has been selected by hardware due to a dist urbance on the main clock signal (f

). It is set by hardware and c lea red by

OSC

reading the SICSR register when the original oscillato r recove rs. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the CSS is di sabled by O PTIO N B YTE, t he CSSD bit value is forced to 0.

Bit 0 = WDGRF

Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog p eripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET pin 0 0

Watchdog 0 1

LVD 1 X

Application Notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep t race of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

Address

(Hex.)

0025h

Label

SICSR

Reset Value 0

76543210

AVDIE0AVDF0LVDRF

CSSIE0CSSD0WDGRF

27/171

ST72260G, ST72262G, ST72264G

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non-maskable events: RESET and TRAP

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

7.2 MASKI NG AN D PROC ESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 4). The proc essing flow is shown in Figure 17

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the cont ents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 4. Interrupt Software Priority Levels

Interrupt software priority Le vel I1 I0

Level 0 (main) Low Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

High

Figure 17. Inte rru pt P rocessing Flowchart

RESET

RESTORE PC, X, A, CC

FROM STACK

28/171

PENDING

INTERRUPT

FETCH NEX T

INSTRUCTION

“IRET”

EXECUTE

INSTRUCTION

THE INTERRUPT STAYS PENDING

Interrupt has the same or a

lower software priority

than current one

STACK PC, X, A, CC

LOA D I1:0 FROM IN TERR UPT SW REG .

LOAD PC FROM INTERRUPT VECTOR

I1:0

softwarepriorit y

than current one

Interrupt has a higher

INTERRUPTS (Cont’d)

ST72260G, ST72262G, ST72264G

Servicing Pe nding Interrup t s

As several interrupts can b e pending at the sam e time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 18 describes this decision process.

Figure 18. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previ ous process to succeed with only one interrupt. Note 2: RESET and TRAP are non-maskable and they can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET and TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 17). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding vector is loaded in the PC re gister and the I 1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart on Figure 17 as a TLI.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vect or sourc es can be serviced if the corresponding interrupt is e nabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC regist er). If any of these two conditions is false, the interrupt is la tched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the Miscellaneous registers (MISCRx). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a grou p connected to the same interrupt vector request an interrupt simultaneously, the interrupt vector w ill be se rv iced. Software can read the pin levels to identify which pin(s) are the source of the interrupt.

If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if o ne of the interrupt pins i s tied low, it masks the other ones.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

29/171

ST72260G, ST72262G, ST72264G

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 18.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 19. Concurren t Int errupt Management

IT1

TLI

IT3

IT0

TLI

IT1

RIM

IT2

IT1

IT4

IT2

HARDWARE PRIORITY

MAIN

11 / 10

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in

Figure 20. The interrupt hardware priority is given

in this order from the l owest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

Note: TLI (Top Level Interrupt) is not available in thi s product.

SOFTWARE PRIORITY LEVEL

IT0

IT3

IT4

MAIN

3 3 3 3 3 3 3/0

11 11 11 11 11 11

USED STACK = 10 BYTES

Figure 20. Nested Interrupt Management

IT2

IT1

IT4

IT1

IT2

RIM

HARDWARE PRIORITY

MAIN

TLI

IT3

IT4 IT4

IT0

TLI

11 / 10

30/171

IT0

IT3

IT1

SOFTWARE PRIORITY LEVEL

IT2

MAIN

I1 I0

3 3 2 1 3 3 3/0

11 11 00 01 11 11

USED STACK = 20 BYTES

ST72260G, ST72262G, ST72264G

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS

Read/Write Reset Value: 111x 1010 (xAh)

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

Read/Write (bits 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

11I1 H I0 NZC

Bit 5, 3 = I1, I0

Software Interr u p t Priority

These two bits indicate the current interrupt software priority.

Interrupt Software Priority Level I1 I0

Level 0 (main) Low Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1

High

These two bits are set/cleared by ha rdware whe n entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by sof tw are wi th th e RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

*Note: TRAP and RESET events are non maskable sources and can interrupt a level 3 program.

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt ve ctor (except R ESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

Vector Address ISPRx Bits

FFFBh-FFFAh ei0

FFF9h-FFF8h ei1

... ...

FFE1h-FFE0h Not used

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h )

The RESET and TRA P vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

31/171

ST72260G, ST72262G, ST72264G

Table 5. Interrupt Mapping

N°

Source

Block

Description

RESET Reset

TRAP Soft ware Interr upt no FFFCh-FFFDh 0 ei0 External Interrupt Port A7..0 (C5..0 1 ei1 External Interrupt Port B7..0 (C5..0

Label

Priority

Order

Highest

Priority

)

) FFF8h-FFF9h

N/A

Exit

from

HALT

Address

Vector

yes FFFEh-FFFFh

yes

FFFAh-FFFBh

2 CSS Clock Filter Interrupt CRSR no FFF6h-FFF7h 3 SPI SPI Peripheral Interrupts SPISR yes FFF4h-FFF 5h 4 TIMER A TIMER A Peripheral Interrupts TASR no FFF2h-FFF3h 5 MCC Time base interrupt MCCSR yes FFF0h-FFF1h 6 TIMER B TIMER B Peripheral Interrupts TBSR 7 AVD Auxiliary Voltage Detector interrupt SICSR FFECh-FFEDh

FFEEh-FFEFh

8 Not used FFEAh-FFEBh 9 Not used FFE8h-FFE9h

10 SCI SCI Peripheral Interrupt SCISR no FFE6h-FFE7h 11 I

C I 12 Not Used FFE2h-FFE3h 13 Not Used FFE0h-FFE1h

C Peripheral Interrupt I2CSRx no FFE4h-FFE5h

Lowest Priority

Note 1. Configurable by option byte.

Table 6. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

001Ch

001Dh

001Eh

001Fh

Label

76543210

SPI CSS EI1 EI0

ISPR0

Reset Value

I1_3

I0_3

I1_2

I0_2

AVD TIMERB MCC TIMERA

ISPR1

Reset Value

ISPR2

Reset Value

I1_7

I1_11

I0_7

C SCI Not Used Not Used

I0_11

I1_6

I1_10

I0_6

I0_10

ISPR3

Reset Value 1 1 1 1

I1_1

I1_5

I1_9

I0_1

I0_5

I0_9

I0_1

I1_4

I1_8

Not Used Not Used

I1_13

I0_13

I1_12

I0_0

I0_4

I0_8

I0_12

32/171

8 POWER SAVIN G MO DES

ST72260G, ST72262G, ST72264G

8.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 21).

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f

CPU

From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 21. Power Savin g Mode Transi t io ns

High

RUN

SLOW

WAIT

8.2 SLOW MODE

This mode has two targets: – To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the MISR1 register: the SMS bit which enables or disables Slow mode a nd two CPx bits which sel ect the internal slow frequency (f

CPU

In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in norm al ope ra ting mode. The CPU and peripherals are clocked at this lower frequency.

Note: SLOW-WAIT mode is activated when enterring the WAIT mode while the device is already in SLOW mode.

Figure 22. SLOW Mode Clock Transitions

CPU

OSC2

CP1:0

/2 f

OSC2

00 01

OSC2

/4 f

OSC2

SLOW WAIT

HALT

Low

POWER CONSUMPTION

SMS

MISCR1

NORMAL RUNMODE

NEW SLOW

FREQUENCY

REQUEST

33/171

ST72260G, ST72262G, ST72264G

POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This pow er s av in g mode is s elected b y calling th e “WFI” ST7 software instruction. All peripherals remain active. During WAIT mode, the I [1:0] bits i n the CC regi ster are forced to

‘10b’

to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to th e starting address of the interrupt or Reset service routine. The MCU will r e main in W AIT mod e unt il a Rese t or an Interrupt occurs, causing it to wake up.

Refer to Figure 23.

Figure 23. WAIT Mode Flowchart

WFI INSTRUCTION

INTERRUPT

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

RESET

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

ON ON

OFF

ON ON ON

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC register are set during the interrupt routine and cleared when the CC register is popped.

34/171

ST72260G, ST72262G, ST72264G

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MC U. They are both entered by executing the ‘HALT’ in struction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

0 HALT mode 1 ACTIVE-HALT mode

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a rea l time clock available. It is entered by exec uting the ‘HALT’ instruction when the OIE bit of t he M ain Clock Controller Status register (MCCSR) is set.

The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 5, “Interrupt M appi ng,” on pag e

32) or a RESET. When exiting ACTIVE-HALT

mode by means of an inte rrupt, no 4096 CPU cy cle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25).

When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked exc ept t hos e w hich get their clock supply from another clock generator (such as external o r a ux iliary oscilla t or ) .

The safeguard against staying l ocked in ACT IVEHALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

Figure 24. ACTIVE-HALT Timing Overview

ACTIVE

HALTRUN RUN

HALT

INSTRUCTION

[MCCSR.OIE=1]

4096 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

Figure 25. ACT IV E - HA LT Mode Flowchart

HALT INSTRUCTION

(MCCSR.OIE= 1)

INTERRUPT

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

RESET

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

4096 CPU CLOCK

CYCLE DELAY

ON OFF OFF

ON OFF

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock source can still be active.

3. Only the MCC/RTC i nterrupt a nd som e spec ific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table

5, “Interrupt Mapping,” on page 32 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

35/171

ST72260G, ST72262G, ST72264G

POWER SAVING MODES (Cont’d)

8.5 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 27).

The MCU can exit HALT m ode on reception of either a specific interrupt (see Table 5, “Interrupt

Mapping,” on page 32) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the i nterrupt or by fetching the reset vector which woke it up (see Figure 26).

When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately.

In the HALT mode the m ain oscillator is t urned o ff causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by t he “WD GHA LT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see

Section 15.1 "OPTION BYTES" on page 157 for

more details).

Figure 26. HA L T Mode Timi ng Overview

HALTRUN RUN

4096 CPU CYCLE

DELAY

Figure 27. HALT Mode Flowchart

HALT INSTRUCTION

WDGHALT

WATCHDOG

RESET

INTERRUPT

ENABLE

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

4096 CPU CLOCK CYCLE

OSCILLATOR PERIPHERALS

CPU I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

WATCHDOG

RESET

DELAY

DISABLE

OFF

OFF OFF

ON OFF

HALT

INSTRUCTION

36/171

RESET

INTERRUPT

FETCH

VECTOR

Notes:

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some sp ecific int errupts can exit the MCU from HALT mode (su ch as ex ternal i nterrupt). Refer to Table 5, “Interrupt Mapping,” on page 32 for more details.

4. Before servicing an interrupt, the CC register is pushed on the s tac k. The I [1:0]

bits in the CC reg-

ister are set during the interrupt routine and cleared when the CC register is popped.

POWER SAVING MODES (Cont’d)

8.5.0.1 Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up t he

microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precautionary measure.

ST72260G, ST72262G, ST72264G

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

37/171

ST72260G, ST72262G, ST72264G

9 I/O PORTS

9.1 INTRODUCTION

The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin c an be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for onchip peripherals or analog input.

9.2 FUNCTIONAL DESCRIPTION

A Data Register (DR) and a Data Direction Register (DDR) are always associated with each port. The Option Register (OR), which allows input/output options, may or may not be implemen ted. Th e following description takes into account the OR register. Refer to the Port Configuration table for device specific information.

An I/O pin is programmed using the corresponding bits in the DDR, DR an d OR registers: bit x corresponding to pin x of the port.

Figure 28 shows the generic I/O block diagram.

9.2.1 Input Modes

Clearing the DDRx bit selects input mode. In this mode, reading its DR bit retu rns the digital value from that I/O pin.

If an OR bit is available, different input modes can be configured by software: floating or pull-up. Refer to I/O Port Implementation section for co nfiguration.

Notes:

1. Writing to the DR modifies the latch val ue but does not change the state of the input pin.

2. Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.

External Interru pt Function

Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O gene rates an interrupt request via the corresponding interrupt vector (eix).

Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control Register (EICR) or the Miscellaneous Register controls this sensitivity, depending on the device.

A device may have up to 7 external interrupts. Several pins may be tied to on e external interrupt vector. Refer to Pin Description to see which ports have external interrupts.

If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are l ogically combined. For this reason if one of the in terrupt pins is tied low, it may mask the others.

External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Modifying the sensitivity bits will clear any pending interrupts.

9.2.2 Output Modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value.

If an OR bit is available, different output modes can be selected by software: push-pull or opendrain. Refer to I/O Port Implementation section for configuration.

DR Value and Output Pin Status

DR Pus h-Pull Open-Drain

0V 1VOHFloating

9.2.3 Alternate Functions

Many ST7s I/Os have one or more alternate functions. These may include output signals from , or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports.

A signal coming from an on-chip peripheral can be output on an I/O. To do this, enabl e the on-chip peripheral as an output (enable bit in the peripheral’s control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O’s state is readable by addressing the corresponding I/O data register.

Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before usin g an I/O as a n alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.

Configure an I/O as input floating for an on-chip peripheral signal which can be input and output.

Caution: I/Os which can b e configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.

38/171

I/O PORTS (Cont’d) Figure 28. I/O Por t Ge nera l Blo ck Diagram

ST72260G, ST72262G, ST72264G

DATA BUS

DDR SEL

DDR

OR SEL

DR SEL

ALTERNATE OUTPUT

From on-chi p periphe r al

ALTERNATE ENABLE BIT

If implemented

P-BUFFER (see table below)

PULL-UP (see table below)

PULL-UP CONDITION

N-BUFFER

DIODES

PAD

(see table below)

ANALOG

CMOS

INPUT

SCHMITT TRIGGER

EXTERNAL

Combinational

INTERRUPT REQUEST (eix)

SENSITIVITY SELECTION

Table 7. I/O Port Mode Options

Configuration Mode Pull-Up P-Buffer

Input

Floating with/without Interrupt Off Pull-up with/withou t Interrupt On Push-pull

Output

Open Drain (logic level) Off True Open Drain NI NI NI (see note)

Legend: NI - not implemented

Off - implemented not activated On - implemented and activated

Logic

FROM OTHER BITS

Note: Refer to the Port Configurati on table for device spec i fic informa tion.

Off

Note: The diode t o V true open drain pads. A local protection between the pad and V vice against positive stress.

ALTERNATE

To on-chip periphe ral

Diodes

to V

Off On

is implemented to protect the de-

is not implem ent ed i n the

INPUT

to V

39/171

ST72260G, ST72262G, ST72264G

I/O PORTS (Cont’d) Table 8. I/O C onfi gurations

Hardware Configu ration

PAD

INPUT

PAD

NOTE 3

PULL-UP CONDITION

INTERRUPT CONDITION

FROM

OTHER

PINS

COMBINATIONAL

DR REGISTER ACCESS

LOGIC

POLARITY SELECTION

DR REGISTER ACCESS

DAT A BUS

ALTERNATE INPUT To on-chip peripheral

EXTERNAL INTERRUPT SOURCE (ei

ANALOG INPUT

R/W

DATA BUS

)

OPEN-DRAIN OUTP UT

DR REGISTER ACCESS

ALTERNATEALTERNATE

R/W

DAT A BUS

PUSH-PULL OUT PUT

PAD

NOTE 3

ENABLE OUTPUT

BIT Fr om on-chi p peripheral

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

3. For true open drain, these elements are not implemented.

40/171

I/O PORTS (Cont’d) Analog alternate function

Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input.

Analog Recommendations

Do not change the voltage level or load ing on any I/O while conversion is in progress. Do no t have clocking pins located c lose to a selected analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum r a tings .

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port depends on the settings in the DDR and OR regi sters and specific I/O port features such as ADC input or open drain.

Switching these I/O ports from one state to anot her should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustr ate d in Figure 29. Ot her transitions are potentially risky and shou ld be avoide d, since they may present unwanted side-effects such as spurious interrupt generation.

ST72260G, ST72262G, ST72264G

9.4 UNUSED I/O PINS

Unused I/O pins mus t be connected to fixed v oltage levels. Refer to Section 13.8.

9.5 LOW POWER MODES

Mode Description

WAIT

HALT

9.6 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).

Interrupt Event

External interrupt on selected external event

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

Event

Flag

Enable

Control

Bit

DDRx

ORx

Exit

from

Wait

Yes Yes

Exit

from

Halt

Figure 29. Inte rru pt I/O P ort S tate Tra ns iti ons

INPUT

floating/pull-up

interrupt

INPUT

floating

(reset state)

OUTPUT

open-drain

OUTPUT push-pull

= DDR, OR

41/171

ST72260G, ST72262G, ST72264G

I/O PO R T S (Cont’d)

9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION

The I/O port register configurations are summarised as follows.

True Open D rai n In te rru pt Po rts PA6, PA4 (without pull-up)

Interrupt Ports PA7, PA5, PA3:0, PB7:0, PC5:0 (with pu ll-u p)

MODE DDR OR

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

floating input 0 0 floating interrupt input 0 1 open drain (high sink ports) 1 X

MODE DDR OR

Table 9. Port Configuration

Port Pin Name

PA7 floating pull-up interrupt open drain push-pull PA6 floating floating interrupt true open-drain

Port A

Port B PB7:0 floating pull-up interrupt open drain push-pull

Port C PC5:0 floating pull-up interrupt open drain push-pull

PA5 floating pull-up interrupt open drain push-pull PA4 floating floating interrupt true open-drain PA3:0 floating pull-up interrupt open drain push-pull

Input (DDR = 0) Output (DDR = 1)

OR = 0 OR = 1 OR = 0 OR = 1 High-Sink

Yes

42/171

I/O PO R T S (Cont’d)

ST72260G, ST72262G, ST72264G

9.8 I/O PORT REGISTER DESCRIPTION

DATA REGISTER (DR)

Port x Data Register PxDR with x = A, B or C.

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:0 = DD[7:0] The DDR register gives the input /output direction

configuration of the pins. Each bit is set and cleared by software.

0: Input mode 1: Output mode

OPTION REGISTER (OR)

Port x Option Register

Data direction register 8 bits.

PxOR with x = A, B or C.

D7 D6 D5 D4 D3 D2 D1 D0

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:0 = D[7:0]

Data register 8 bits.

The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account

O7 O6 O5 O4 O3 O2 O1 O0

even if the pin is configured as an input; this allows always having the expected le ve l on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I /O pin (pin configured as i nput ).

Bits 7:0 = O[7:0]

Option register 8 bits.

For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration.

The OR register allows to distinguish: in input

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register PxDDR with x = A, B or C.

Read/Write Reset Value: 0000 0000 (00h)

mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected.

Each bit is set and cleared by software. Input mode:

0: Floating input

1: Pull-up input with or without interrupt Output mode:

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

0: Output open drain (with P-Buffer unactivated) 1: Output push-pull (when available)

43/171

ST72260G, ST72262G, ST72264G

I/O PORTS (Cont’d) Table 10. I/O Port Register Map and Reset Values

Address

(Hex.)

Reset Value

of all I/O port registers

0000h PCDR

0002h PCOR 0004h PBDR

0006h PBOR 0008h PADR

000Ah PAOR

Label

76543210

00000000

MSB LSB0001h PCDDR

MSB LSB0005h PBDDR

MSB LSB0009h PADDR

44/171

10 MISCELLANEOUS REGISTERS

ST72260G, ST72262G, ST72264G

The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions.

10.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register and the OPTION BYTE. This control allows you to have two fully independent external interrupt source sensitivities with configurable sources (using the EXTIT option bit) as shown in Fig ure 30 and Fig-

ure 31.

Each external interrupt source can be gen erated on four different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

To guarantee correct functiona lity, the sensitivity bits in the MISCR1 register must be mo dified on ly when the I[1:0] bits in the CC register are set to 1 (interrupt masked). See Section 9.8 "I/O PORT

REGISTER DESCRIPTION" on page 43 and Sec- tion 10.3 "MISCELLANEOUS REGISTER DESCRIPTION" on page 46 for more details on the

programming.

Figure 30. Ext. Interrupt Sensitivity (EXTIT=0)

PA7

PA0

PC5

PC0

PB7

PB0

ei0

INTERRUPT

SOURCE

ei1

INTERRUPT

SOURCE

MISCR1

IS00 IS01

SENSITIVITY

CONTROL

MISCR1

IS10 IS11

SENSITIVITY

CONTROL

Figure 31. Ext. Interrupt Sensitivity (EXTIT=1)

MISCR1

IS00 IS01

SENSITIVITY

CONTROL

PA7

PA0

ei0

INTERRUPT

SOURCE

10.2 I/O PORT ALTERNATE FUNCTIONS

The MISCR registers manage four I/O port miscellaneous alternate functions:

■ Main clock signal (f

■ SPI pin configuration:

–SS

pin internal control to use the PB7 I/O port

) output on PC2

CPU

function while the SPI is active.

– Master output capability on the MOSI pin

(PB4) deactivated while the SPI is active.

– Slave output capability on the MISO pin (PB5)

deactivated while the SPI is active.

These functions are described in detail in the Sec-

tion 10.3 "MISCELLANEOUS REGISTER DESCRIPTION" on page 46.

PB7

PB0 PC5

PC0

ei1

INTERRUPT

SOURCE

MISCR1

IS10 IS11

SENSITIVITY

CONTROL

45/171

ST72260G, ST72262G, ST72264G

MISCELLANE OUS REGISTERS (Cont’ d)

10.3 MISCELLANEOUS REGISTER DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write Reset Value: 0000 0000 (00h)

Bits 2:1 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the various slow modes. Th eir action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software

in SLOW mode CP1 CP0

CPU

IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS

Bits 7:6 = IS1[1:0]

ei1 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

/ 2 0 0

OSC2

/ 4 1 0

OSC2

/ 8 0 1

OSC2

/ 16 1 1

OSC2

bits, is applied to the ei1 external interrupts. These two bits can be written only when the I[1:0] bits i n the CC register are set to 1 (interrupt masked).

ei1: Port B (C optional)

External Interrupt Sensit ivity IS11 IS10

Falling edge & low level 0 0 Rising edge only 0 1 Falling edge only 1 0 Rising and falling edge 1 1

Bit 5 = MCO

Main clock out selection

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software. 0: Normal mode. f 1: Slow mode. f

= f

CPU

OSC2

is given by CP1, CP0 See low power consumption mode and MCC chapters for more details.

This bit enables the MCO alternate function on the PC2 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

port)

CPU

on I/O

Bits 4:3 = IS0[1:0]

ei0 sensitivity

The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts. These two bits can be written only when the I[1:0] bits inthe CC register are set to 1 (interrupt masked).

ei0: Port A (C optional)

External Interrupt Sensitivity IS01 IS00

Falling edge & low level 0 0 Rising edge only 0 1 Falling edge only 1 0 Rising and falling edge 1 1

46/171

ST72260G, ST72262G, ST72264G

MISCELLANE OUS REGISTERS (Cont’ d) MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write Reset Value: 0000 0000 (00h)

0000MODSODSSMSSI

Caution: This register has been provided for compatibility with the ST72254 family only. The same bits are available in the SPICSR register. New applications must use the SPI CSR register. Do not use both r egisters, this will c ause t he SPI to malfunction.

Bits 7:4 = Reserved

always read as 0

Bits 3 = MOD

SPI Master Output Disable

This bit is set and cleared by software. When set, it disables the SPI Master (MOSI) output signal. 0: SPI Master Output enabled. 1: SPI Master Output disabled.

Bit 2 = SOD

SPI Slave Output Disable

This bit is set and cleared by software. When set it disable the SPI Slave (MISO) output signal. 0: SPI Slave Output enabled. 1: SPI Slave Output disabled.

Bit 1 = SSM

SS mode selection

This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS

input from the external SS

pin.

1: I/O mode, the level of the SPI SS

signal is

signal is read

from the SSI bit.

Bit 0 = SSI

SS internal mode

This bit replaces the SS pin of the SPI when the SSM bit is set to 1. (see SPI description). It is set and cleared by software.

Table 11. Miscellaneous Register M ap and Reset Value s

Address

(Hex.)

0020h

0040h

Label

MISCR1

Reset Value

MISCR2

Reset Value 0 0 0 0

76543210

IS11

IS10

MCO

IS01

IS00

MOD

CP1

SOD

CP0

SSM

SMS

SSI

47/171

ST72260G, ST72262G, ST72264G

11 ON-CHIP PER IPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

The Watchdog tim er is used to detect t he occurrence of a software fault, usually generated by external interference or by unforeseen logi cal conditions, which causes the application program to abandon its normal seque nce. The W atchdog circuit generates an MCU reset o n expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

11.1.2 Main Features

■ Programmable free-running downcount er

■ Programmable reset

■ Reset (if watchdog activate d) when the T6 bit

reaches zero

■ Optional reset on HALT instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte

11.1.3 Functional Description

The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 f

cycles (approx.), and the

OSC2

length of the timeout period can be programme d by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becom es cleared), it initia tes a reset cycle pulling low the reset pin for typically 500ns.

The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h:

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the watchdog produces a reset (see Figure 33. Ap-

proximate Timeout Duration). The timing varies

between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 34).

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used to gen erate a s oftware reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

Figure 32. Wa t chdog Bl ock Diagr am

OSC2

MCC/RTC

DIV 64

12-BIT MCC

RTC COUNTER

48/171

MSB

LSB

TB[1:0] bits (MCCSR

WDGA

RESET

WATCHDOG CONTROL REGISTER (WDGCR)

T6 T0

6-BIT DOWNCOUNTER (CNT)

WDG PRESCALER

DIV 4

WATCHD OG TI M E R (Cont’d)

11.1.4 How to Program the Watchdog Timeout

Figure 3 3 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If

Figure 33. Ap proximate Time out Dura t i on

ST72260G, ST72262G, ST72264G

more precision is needed, use the formulae in Fig-

ure 34.

Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.

CNT Value (hex.)

1.5 65

503418 82 98 114

Watchdog timeout (ms) @ 8 MHz. f

128

OSC2

49/171

ST72260G, ST72262G, ST72264G

WATCHD OG TI M E R (Cont’d) Figure 34. Exact Timeout Duration (t

min

and t

max

)

WHERE:

= (LSB + 128) x 64 x t

min0

= 16384 x t

max0

OSC2

= 125ns if f

OSC2

=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values f rom th e t able b elow d ependi ng on the timebase selected by the TB[1:0] bits

in the MCCSR register

TB1 Bit

(MCCSR Reg.)

0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54

To calculate the m i ni m um Wat chdog Tim eout (t

IF THEN

CNT

MSB

------------4

To calculate the maximum Watchdog Timeout (t

TB0 Bit

(MCCSR Reg.)

ELSE

mintmin0

Selected MCCSR

Timebase

mintmin0

MSB LSB

min

16384 C NT t



× 192 LS B+()64

16384 CNT



max

××

–

osc2

4CNT

---------------- MSB

4CNT

××

---------------- MSB

×+=

osc2

IF THEN

CNT

MSB

-------------

≤ t

ELSE

maxtmax0

16384 C NT t



× 192 LSB+()64

16384 CNT



××

–

osc2

4CNT

---------------- MSB

4CNT

××

---------------- MSB

Note: In the above formulae, division results must be rounded down to the next integer value. Example:

With 2ms timeout selected in MCCSR register

Value of T[5:0] Bits in

WDGCR Register (Hex.)

00 1.496 2.048

3F 128 128.552

Min. Watchdog

Timeout (ms)

min

Max. Watchdog

Timeout (ms)

max

×+=

osc2

50/171

WATCHD OG TI M E R (Cont’d)

11.1.5 Low Power Modes Mode Description

SLOW No effect on Watchdog.

WAIT No effect on Watchdog.

OIE bit in

MCCSR register

WDGHALT bit

in Option

Byte

HALT

0 1 A reset is generated.

ST72260G, ST72262G, ST72264G

No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.

If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 11.1.7 below.

No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.

11.1.6 Hardware Watchdog Option

If Hardware Watchdog is selected by option b yte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Opt ion Byt e description.

11.1.7 Using Halt Mode with the WDG

(WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

11.1.8 Interrupts

None.

11.1.9 Register Description CONTROL REGISTER (WDGCR)

Read/Write Reset Value: 0111 1111 (7Fh)

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA

Activation bit

. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

Bit 6:0 = T[6:0]

7-bit counter (MSB to LSB).

These bits contain the value of the watchdog counter. It is decremented every 16384 f

OSC2

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

51/171

ST72260G, ST72262G, ST72264G

Table 12. Watchdog Time r Register Map and Rese t Values

Address

(Hex.)

0024h

Label

WDGCR

Reset Value

76543210

WDGA

52/171

11.2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC)

ST72260G, ST72262G, ST72264G

The Main Clock Con troller consists of a real time clock timer with interrupt capability

11.2.1

Real Time Clock Timer (RTC)

The counter of the real time clock time r allows an interrupt to be generated based on an accurate

When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 8.4

"ACTIVE-HALT AND HALT M ODES" on page 35

for more details.

real time clock. Four differe nt time bas es depending directly on f

are available. The whole

OSC2

functionality is controlled by four bits of the M CCSR register: TB[1:0], OIE and OIF.

Figure 35. Main Clock Controller (MCC/RTC) Block Diagram

OSC2

MCCSR

RTC

COUNTER

TB1 TB0 OIE OIF

TO WATCHDOG

MCC/RTC INTERRUPT

53/171

ST72260G, ST72262G, ST72264G

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

11.2.2

Low Power Mo des

Bit 7:4 = reserved

Mode Description

No effect on MCC/RTC peripheral.

WAIT

ACTIVEHALT

HALT

11.2.3

MCC/RTC interrupt cause the device to exit from WAIT mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode.

MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from HALT” capability.

Interrupts

The MCC/RTC interrupt even t generat es an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active

Bit 3:2 = TB[1:0] These bits select the programm able divider time

base. They are set and cleared by software.

Counter

Prescaler

16000 4 ms 2ms 0 0 32000 8 ms 4ms 0 1 80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

A mod ificatio n of th e time bas e is taken into ac count at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock.

Time base control

Time Base

=4MHz f

OSC2

(RIM instruction).

Oscillator interrupt enable

.MAIN CLOCK CONTROLLE R WITH REAL

Oscillator interrupt flag

Interrupt Event

Time base overflow event

Event

Enable

Control

Flag

OIF OIE Yes No

Bit

Exit

from

Wait

Exit

from

Halt

Note: The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

11.2.4

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write Reset Value: 0000 0000 (00h

)

Bit 1 = OIE This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode TIME CLOCK (Cont’d)

Bit 0 = OIF This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached

CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid

0 0 0 0 TB1 TB0 OIE OIF

unintentionally clearing the OIF bit.

=8MHz

TB1 TB0

Table 13. Main Clock Controller Regi ster Ma p and Reset Values

Address

(Hex.)

0025h

0026h

54/171

Label

SICSR

Reset Value

MCCSR

Reset Value 0 0 0 0

76543210

VDS

VDIE

VDF0LVDRF

TB1

CFIE

TB0

CSSD0WDGRF

OIE

OIF

11.3 16-BIT TIMER

ST72260G, ST72262G, ST72264G

11.3.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input signals (

input capture

put waveforms (

) or generation of up to two out-

output compare

and

PWM

Pulse lengths and waveform perio ds c an be m odulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized a fter a MCU reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two timers, regi ster names are prefixed with TA (Timer A) or TB (Timer B).

11.3.2 Main Features

■ Programmable prescaler: f

■ Overflow status flag and maskable interrupt

■ External clock inpu t (must be at least 4 times

slower than the CPU

clock speed) with the choice

divided by 2, 4 or 8.

CPU

of active edge

■ 1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ 1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

11.3.3 Functional Descri ption

11.3.3.1 Counter

The main block of the Programmab le Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nific a nt by te ( MS Byte ).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Count er Hi gh Regi ster ( ACHR) is th e

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byt e (LS Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the cloc k control bits of the CR2 register, as illustrated in Table 14 Clock

Control Bits. The value in t he counter register re-

peats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency c an be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

The Block Diagram is shown in Figure 36. *Note: Some timer pins may not available (not

bonded) in some ST7 devices. Refer to the device pin out description.

55/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d) Figure 36. Timer Block Diagram

CPU

ST7 INTERNAL BUS

MCU-PERIPHERAL INTERFACE

EXTCLK

EXEDG

1/2 1/4 1/8

CC[1:0]

8 high

COUNTER

ALTERNATE

COUNTER

OVERFLOW

DETECT CIRCUIT

8 low

8-bit

buffer

high

OUTPUT

COMPARE

TIMER INTERNAL BUS

OUTPUT COMPARE

CIRCUIT

low

16 16

high

low

OUTPUT COMPARE REGISTER

88 8

high

INPUT

CAPTURE

EDGE DETECT

CIRCUIT1

EDGE DETECT

CIRCUIT2

8 8 8

low

high

low

INPUT

CAPTURE

ICAP1

ICAP2

56/171

(See note)

TIMER INTERRUPT

ICF2ICF1

OCF2OCF1 TOF

(Control/Status Register)

TIMD

CSR

(Control Register 1) CR1

LATCH1

LATCH2

OC2E

PWMOC1E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE

IEDG2CC0CC1

(Control Register 2) CR2

Note: If IC, OC and TO interrupt requests have separate vectors then the last O R is not presen t (See devic e In terrupt Vector Tabl e)

OCMP1

OCMP2

EXEDG

16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter

Beginning of the sequence

At t0

Read MS Byte

LS Byte

is buffered

Other

instructions

Returns the buffered

LS Byte value at t0

At t0 +∆t

Read LS Byte

Sequence completed

The user must read the MS Byte f irst, then the LS Byte value is buffered automatically.

This buffered value rem ains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, one pulse mode or P WM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these cond itions is false, the interrupt remains pending to be issued as soon as they are both true.

ST72260G, ST72262G, ST72264G

Clearing the overflow interrupt request is done in two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Count ing then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

11.3.3.2 External Clock

The external clock (wh ere available) is selected if CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronized with t he falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.

57/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d) Figure 37. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFD FFFE FFFF 0000 0001 0002 0003

Figure 38. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGI STER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

Figure 39. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD

0000

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

58/171

16-BIT TIMER (Cont’d)

11.3.3.3 Input Capture

In this section, the index, there are 2 input capture functions in the 16-bit timer.

The two 16-bit input capture registers (IC1R and IC2R) are used to latch the valu e of the free running counter after a transition is detected on the ICAP

pin (see figure 5).

MS Byte LS Byte

ICiR IC

R register is a read-only register.

The active transition is software programmable

through the IEDG Timing resolution is one count of the free running

counter: (

Procedure:

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 14

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is

available). And select the following in the CR1 register: – Set the ICI E bit to ge nerat e an in terrupt after an

input capture com ing from e ither the ICAP1 pin

or the ICAP2 pin – Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating inp ut or inp ut with pul l-

up without interrupt if this configuration is availa-

ble).

CPU

bit of Control Registers (CRi).

/CC[1:0]).

, may be 1 or 2 because

HR ICiLR

ST72260G, ST72262G, ST72264G

When an input capture occurs:

bit is set.

– ICF

– The IC

running counter on the active transition on the ICAP

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture in terrupt request (i.e. clearing the ICF

1. Reading the SR register while the ICF

2. An acc ess (read or write) to the IC

Notes:

1. After reading the IC input capture data is inhibited and ICF never be set until the IC read.

2. The IC counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In O ne pulse Mode and PWM mode only I nput Capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly connecte d to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAP as an input and the s econd one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the in put capture function

1).

6. The TOF bit can be used with interrupt generation in order to m easure events t hat go b eyond the timer range (FFFFh).

R register contains t he val ue of the free

pin (see Figure 41).

bit) is done in two steps:

bit is set.

iLR

HR register, transfer of

will

LR register is also

R register contains the free running

pins is configured

is disabled by reading the ICiHR (see note

59/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d) Figure 40. Input Capture Block Diagram

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

IC2R Register

16-BIT

16-BIT FREE RUNNING

COUNTER

EDGE DETECT

CIRCUIT1

IC1R Register

Figure 41. Input Capture Timing Diagram

TIMER CLOCK

ICIE

(Control Register 1) CR1

IEDG1

(Status Register) SR

ICF2ICF1 000

(Control Register 2) CR2

IEDG2

CC0

CC1

COUNTER REGISTER

ICAPi FLAG

ICAPi REGISTER

Note: The rising edge is the active edge.

60/171

FF01 FF02 FF03

ICAPi PIN

FF03

16-BIT TIMER (Cont’d)

11.3.3.4 Output Compare

In this section, the index,

, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer .

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found bet ween the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be com pared to the counter register each timer clock cycle.

MS Byte LS Byte

ROC

HR OCiLR

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

R value to 8000h.

Timing resolution is one count of the free running counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMP

pin is dedicated to the output com pare

signal.

– Select the timer clock (CC[1:0]) (see Table 14

Clock Control Bits).

And select the following in the CR1 register:

– Select the OLVL

bit to applied to the OCMPi pins

after the match occurs.

– Set the OCIE bit to generate an interrupt i f it is

needed.

When a match is found between OCRi register and CR register:

– OC F

bit is set.

ST72260G, ST72262G, ST72264G

– The OCMP

pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in the CC register (CC).

The OC

R register value required for a specific timing application can be c alcul ated using the following f ormula:

∆t * f

∆ OC

R =

CPU

PRESC

Where:

∆t = Output compare period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 14

Clock Control Bits)

If the timer clock is an external clock, the formula is:

∆ OC

R = ∆t

* fEXT

Where:

∆t = Output compare period (in seconds)

= External timer clock frequency (in hertz)

EXT

Clearing the output compare interrupt request (i.e. clearing the OCF

1. Reading the SR register while the OCF

set.

2. An access (read or write) to the OC The following procedure is recommended to pre-

vent the OCF it is read and the write to the OC

– Write to the OC

are inhibited).

– Read the SR register (first step of the clearance

of the OCF

– Write to the OC

compare function and clears the OCF

bit) is done by:

bit from being set between the time

R register:

HR register (further compares

bit, which may be already set).

LR register (enables the output

bit is

LR register.

bit).

61/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d) Notes:

1. After a proces sor write cycle to the OC ister, the output compare function is inhibited until the OC

2. If the OC

iLR

E bit is not set, the OCMPi pin is a general I/O port and the OLVL appear when a match is f ound but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f OCMP the OC

are set while the counter value equals

R register value (see Figure 43 on page

CPU

63). This behaviour is the same in OPM or

PWM mode. When the timer clock is f external clock mode, O CF

/4, f

CPU

and OCMPi are set while the counter value equals the OC ter value plus 1 (see Figure 44 on page 63).

4. The output compare functions can be used both for generating external events on the OCMP pins even if the input capture mode is also used.

5. The value in the 16-bit OC

bit should be changed after each suc-

OLV

R register and the

cessful comparison in order to control an output waveform or establish a new elapsed timeout.

iHR

reg-

bit will not

/2, OCFi and

/8 or in

CPU

R regis-

Forced Compare Output capabili ty

When the FOLV

bit is set by software, the OLVL bit is copied to the OCMPi pin. The OLVi bit has to be toggled in ord er to t oggle th e OCMP it is enabled (OC

E bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVL

bits have no effect in both one pulse

mode and PWM mode.

pin when

Figure 42. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit

OC1R Register

16-bit

OC2R Register

OC1E CC0CC1

OC2E

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1

(Status Register) SR

OLVL1OLVL2OCIE

000OCF2OCF1

Latch

OCMP1

OCMP2

62/171

16-BIT TIMER (Cont’d) Figure 43. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

TIMER

CPU

ST72260G, ST72262G, ST72264G

COUNTER REGISTER

OUTPUT COMPARE REGISTER

OUTPUT COMPARE FLAG

OCMP

PIN (OLVLi=1)

(OCRi)

(OCFi)

Figure 44. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER

OUTPUT COMPARE FLAG

OCMPi PIN (OLVLi=1)

(OCRi)

LATCH

(OCFi)

2ED0 2ED1 2ED2

TIMER

CPU

2ED0 2ED1 2ED2

2ED3

2ED42ECF

63/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d)

11.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the op po s ite column).

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the a ctive trans ition o n th e

ICAP1 pin with the IEDG1 bit must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (s ee Table 14

Clock Control Bits).

(the ICAP1 pin

Clearing the Input Capture in terrupt request (i.e. clearing the ICF

1. Reading the SR register while the ICF

2. An acc ess (read or write) to the IC

bit) is done in two steps:

iLR

bit is set.

The OC1R register value required for a specific timing application can be calculated usi ng the following formula:

R Value =

CPU

PRESC

- 5

Where: t = Pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 14

Clock Control Bits)

If the timer clock is an external clock the formula is:

OCiR = t

* fEXT

-5

Wher e: t = Pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

When the value of the counter is equal to the value of the contents of t he OC1R register, the OLV L1 bit is output on the OCMP1 pin, (See Figure 45).

One pulse mode cycle

When

event occurs

on ICAP1

ICR1 = Counter

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

When

Counter = OC1R

OCMP1 = OLVL1

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

Notes:

1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can gen erate an Output Compare interrupt.

2. W hen the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used t o perfo rm input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge o ccurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. W hen one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but canno t generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.

64/171

16-BIT TIMER (Cont’d) Figure 45. One Pulse Mode Timing Example

ST72260G, ST72262G, ST72264G

IC1R

COUNTER

ICAP1

OCMP1

01F8

FFFC FFFD FFFE 2ED0 2ED1 2ED2

01F8

OL VL2

2ED3

FFFC FFFD

OL VL2OLVL1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 46. Pul s e W i dth Modulat io n Mo de Ti m in g E xa m p le wi t h 2 Out put Compa re Fun c ti ons

COUNTER

OCMP1

FFFC FFFD FFF E

34E2

2ED0 2ED1 2ED2

OLVL2

34E2 FFFC

OLVL2OLVL1

compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated us-

ing the output compare and the counter overflow to define the pulse length.

65/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d)

11.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal wi th a frequency a nd pul se length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation mode uses the complete Output Compare 1 fu nction plus the OC2R register, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only a t the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column.

3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC2R register.

4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 14

Clock Control Bits).

Pulse Width Modulation cycle

When

Counter = OC1R

When Counter = OC2R

OCMP1 = OLVL1

OCMP1 = OLVL2

Counter is reset

to FFFCh

If OLVL1=1 and OLVL2=0 the lengt h of the positive pulse is the difference between the OC2R and OC1R registers.

If OLVL1=OLV L2 a c ont inuo us signal will be seen on the OCMP1 pin.

The OC

R register value required for a specific timing application can be c alcul ated using the following f ormula:

R Value =

CPU

PRESC

- 5

Where: t = Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 14 Clock

Control Bits)

If the timer clock is an external clock the formula is:

OCiR = t

* fEXT

-5

Wher e: t = Signal or pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 46)

Notes:

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the OC

LR register is also written.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output Compare interrupt is inhibited.

3. The ICF 1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

4. In P WM mode the ICA P1 pin can not be used

to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set.

5. W hen the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

66/171

ICF1 bit is set

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d)

11.3.4 Low Power Modes

Mode Description

WAIT

HALT

11.3.5 Interrupts

Input Capture 1 event/Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No

No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF the counter value present when exiting from HALT mode is captured into the IC

Interrupt Event

pin, the input capture detection circuitry is armed. Consequent-

bit is set, and

R register.

Event

Flag

Enable

Control

Bit

ICIE

OCIE

Exit from Wait

Yes No

Exit

from

Halt

Note: The 16-bit Timer interrupt events are connec ted to the same i nterrupt vector (s ee Interrupts chap-

ter). These events generate an interrupt if the correspo nding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

11.3.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse Mode No Not Recommended PWM Mode No Not Recommended

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

TIMER RESOURCES

No Partially No No

1) See note 4 in Section 11.3.3.5 "One Pulse Mod e" on page 64

2) See note 5 in Section 11.3.3.5 "One Pulse Mod e" on page 64

3) See note 4 in Section 11.3.3.6 "Pulse Widt h Modu lation Mode" on page 66

67/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d)

11.3.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the count er and the a lternate counter.

Bit 4 = FOLV2

Forced Output Compare 2.

This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC 2E bit is set and even if there is no successful compariso n.

CONTROL REGISTER 1 (CR1)

Read/Write Reset Value: 0000 0000 (00h)

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 3 = FOLV1 This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and e ven if there i s no successful comparison.

Bit 2 = OLVL2

Bit 7 = ICIE

Input Capture Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE

Output Compare Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

This bit is copied to the OCMP2 pin whenev er a successful compa rison occurs with t he OC2R reg ister and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.

Bit 1 = IEDG1 This bit determines wh ich type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture.

Forced Output Compare 1.

Output Level 2.

Input Edge 1.

1: A rising edge triggers the capture.

Bit 5 = TOIE 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Timer Overflow Interrupt Enable.

Bit 0 = OLVL1

Output Level 1.

The OLVL1 bi t is c opied to t he OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC 1E bit is s et in the CR2 register.

68/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2)

Read/Write Reset Value: 0000 0000 (00h)

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 4 = PWM 0: PWM mode is not active. 1: PWM mode is active, the OCMP 1 pin outputs a

programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Pulse Width Modulation.

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to outp ut the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate f unction disa bled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Pin Enable.

This bit is used only to outp ut the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate f unction disa bled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM

One Pulse Mode.

0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the active transition is g iven by the I EDG1 bit. Th e length of the generated pulse depends on the contents of the OC1R register.

Bit 3, 2 = CC[1:0]

Clock Control.

The timer clock mode depends on these bits:

Table 14. Clock Control Bits

Timer Clock CC1 CC 0

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

CPU

External Clock (where

available)

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

Bit 1 = IEDG2

Input Edge 2.

This bit determines wh ich type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines wh ich type of level transition on the external clock pin EXTCLK wi ll trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

69/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR)

Read Only (except bit 2 R/W) Reset Value: xxxx x0xx (xxh)

ICF1 OCF1 TOF ICF2 O CF2 TIMD 0 0

Bit 7 = ICF1

Input Capture Flag 1.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin

or the counter has reached th e OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the lo w byte of the IC1R (IC1LR) register.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC1R register. To clear this bit, first read the SR register, t hen read or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF

Timer Overflow Flag.

0: No timer overflow (reset value). 1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value). 1: The content of the free running counter has

matched the cont ent of the OC2R register. T o clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Bit 2 = TIMD

Timer disable.

This bit is set and cleared by software. When set, it freezes the timer prescaler an d counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the count er reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

70/171

16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

ST72260G, ST72262G, ST72264G

OUTPUT COMPARE 1 HIGH REGISTER (OC1HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit re gister tha t co ntains t he hi gh part of the value to be compared to the CHR register.

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER (OC1LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

71/171

ST72260G, ST72262G, ST72264G

16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that cont ains the high part of the value to be compared to the CHR register.

ALTERNATE COUNTER HIGH REGISTER (ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit re gister tha t co ntains t he hi gh part of the counter value.

MSB LSB

OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does no t clear the TOF bit i n the CSR register.

MSB LSB

COUNTER HIGH REGISTER (CHR)

MSB LSB

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that cont ains the high part of the counter value.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only

Reset Value: Undefined This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

MSB LSB

Input Capture 2 event).

COUNTER LOW REGISTER (CLR)

MSB LSB

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).

MSB LSB

72/171

MSB LSB

16-BIT TIMER (Cont’d) Table 15. 16-Bit Timer Register Map and Reset Values

ST72260G, ST72262G, ST72264G

Address

(Hex.)

Timer A: 32 Timer B: 42

Timer A: 31 Timer B: 41

Timer A: 33 Timer B: 43

Timer A: 34 Timer B: 44

Timer A: 35 Timer B: 45

Timer A: 36 Timer B: 46

Timer A: 37 Timer B: 47

Timer A: 3E Timer B: 4E

Timer A: 3F Timer B: 4F

Timer A: 38 Timer B: 48

Label

CR1

Reset Value

CR2

Reset Value

CSR

Reset Value

IC1HR

Reset Value

IC1LR

Reset Value

OC1HR

Reset Value

OC1LR

Reset Value

OC2HR

Reset Value

OC2LR

Reset Value

CHR

Reset Value

76543210

ICIE

OC1E

ICF1

MSB

1111111

OCIE

OC2E

OCF1

------

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

OPM

TOF

PWM

ICF2

CC1

OCF2

CC0

TIMD

IEDG20EXEDG

LSB

Timer A: 39 Timer B: 49

Timer A: 3A Timer B: 4A

Timer A: 3B Timer B: 4B

Timer A: 3C Timer B: 4C

Timer A: 3D Timer B: 4D

CLR

Reset Value

ACHR

Reset Value

ACLR

Reset Value

ICHR2

Reset Value

ICLR2

Reset Value

MSB

1111110

MSB

1111111

MSB

1111110

MSB

------

LSB

73/171

ST72260G, ST72262G, ST72264G

11.4 SERIAL PER IPHERAL INTERFACE (SPI)

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.

11.4.2 Main Features

■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines)

■ Master or slave operation

■ Six master mode frequencies (f

■ f

■ SS Management by software or hardware

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■ Write collis ion, Master Mo de Fault and Ove rru n

/2 max. slave mode frequency

CPU

/4 max.)

flags

Figure 47. Serial Peripheral Interface Block Diagram

Data/Address Bus

SPIDR

Read Buffer

Read

11.4.3 General Desc ription

Figure 47 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR)

The SPI is connect ed to external d evices through 3 pins:

– MISO: Master In / Slave Out data – M OSI: Master Out / Slave In data – SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

–SS

: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS ard I/O ports on the master

inputs can be driven by stand-

Device.

Interrupt

request

MOSI

MISO

SCK

74/171

SOD

bit

8-Bit Shift Register

Write

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

SPIF WCOL MODF 0OVR SSISSMSOD

SPI

STATE

CONTROL

SPIE SPE

SPR2

MSTR

CPOL

CPHA SPR0SPR1

SPICSR

SPICR

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 48.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device re-

Figure 48. Single Master/ Single Slave Application

ST72260G, ST72262G, ST72264G

sponds by sending da ta to the master device via the MISO pin. This implies full duplex communication with both data out an d data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communicati on is possib le).

Four possible data/clock timing relationship s may be chosen (s ee Figure 51) b ut master and s lave must be programmed with the same timing mode.

MASTER

MSBit LS Bit MSBit LSBit 8-BIT SHIFT REGISTE R

SPI

CLOCK

GENERATO R

MISO

MOSI

SCK

+5V

MISO

MOSI

SCK

8-BIT SHIFT REGISTE R

SLAVE

Not used if SS is managed by software

75/171

ST72260G, ST72262G, ST72264G

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.2 Slave Select Management

As an alternative to using the SS Slave Select signal, the appli c ation can c ho os e to manage the Slave Select signal by software. This is configured by the SSM bit in the SP I CSR register (see Figure 50)

In software management, the external SS free for other application uses and t he i nte rnal SS signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

–SS

internal must be held high continuously

pin to control the

pin is

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Figure 49 ):

If CPHA=1 (data latched on 2nd clock edge):

–SS

internal must be held low during the entire transmission. This implies that in s in gle s lave applications the SS V

, or made free for standard I/O by manag-

ing the SS

function by software (SSM= 1 and

pin either can be tied to

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

–SS

internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS

is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.4.5.3).

Figure 49. Generic SS

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Timing Dia gram

Byte 1 Byte 2

Figure 50. Hardware/Software Slave Select Management

SSM bit

external pin

SSI bit

SS internal

Byte 3

76/171

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The clock fr equen cy, polarity and ph ase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must corres pond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

To operate the SPI in master mode, perform the following two steps in order (if t he SPICSR register is not written first, the SPICR register setting may be not taken into account):

1. Write to the SPICSR register: – Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity a nd clock phase by

configuring the CPOL a nd CPHA bits. Fig ure

51 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

– Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS

pin high for

the complete byte transmit sequence.

2. Write to the SPICR register: – Set the MSTR and SPE bits

Note: MST R and SP E bits remain set only if SS

is high).

The transmit sequence begins when software writes a byte in the SPIDR register.

11.4.3.4 Master Mode Transmit Sequen ce

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware – An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CC R register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A read to the SPIDR register.

Note: While t he SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read .

ST72260G, ST72262G, ST72264G

11.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

1. W rite to the SPIC SR register to perform the f ollowing actions:

– Select the clock po larity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 51).

Note: T he slave must have the same CPOL and CPHA settings as the master.

– Manage the SS

11.4.3.2 and Figure 49. If C PHA=1 SS

be held low continuously. If CPHA=0 SS be held low during byte transmission and pulled up between each b yte to let the slave write in the shift register.

2. W rite to the SP ICR register to c lear the M STR bit and set the SPE bit to enable the SPI I/O functions.

11.4.3.6 Slave Mode Transmit Sequen ce

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin m ost significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most signifi cant bit of the data on its MOSI pin.

When data transfer i s complete :

– The SPIF bit is set by hardware – An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF b it is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.4.5.2).

pin as described in Section

must

77/171

ST72260G, ST72262G, ST72264G

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chose n by software, using the CPOL and CP HA bits (See

Figure 51).

Note: The idle state of SCK mus t correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

The combination of the CPOL clock pol arity and CPHA (clock phase) bits selects the data capture clock edge

Figure 51. Data Clo c k Ti m in g Di a gram

SCK (CPOL = 1)

SCK (CPOL = 0)

Figure 51, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly conne cted between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI mus t be disabled by resetting the SPE bit.

CPHA =1

MISO

(from master)

MOSI

(from slav e)

(to slave)

CAPTURE STROBE

SCK (CPOL = 1)

SCK (CPOL = 0)

MISO

(from master)

MOSI

(from slav e)

(to slave)

CAPTURE STR OB E

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

CPHA =0

Bit 4 Bit3 Bit 2 Bi t 1 LSBit

Bit 4 Bit3 Bit 2 B it 1 LSBit

78/171

Note:

This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5 Error Flags

11.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device has its SS

pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the Device and disables the SPI peripheral.

– The MSTR bit is reset, thus forcing the Device

into slave mode.

Clearing the MODF bit is done through a software sequence:

1. A read acc ess to the SPICSR register while the MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS

pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but in a multi master configuration the

Device can be in

slave mode with the MODF bit set. The MODF bit indicates that there might have

been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset o r return to an application default state .

ST72260G, ST72262G, ST72264G

11.4.5.2 Overrun Condit ion (OV R)

An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun o ccurs: – The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the rec eiver buffer contains the b yte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

11.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Section 11.4.3.2 "Slave Select

Management" on page 76.

Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the CPU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 52).

Figure 52. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

2nd Step

Read SPICSR

Read SPIDR

RESULT

SPIF =0 WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

Read SPICSR

Read SPIDR

RESULT

WCOL=0

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit

79/171

ST72260G, ST72262G, ST72264G

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5.4 Single Master and Multimaster Configurations

There are two types of SPI systems: – Single Master System – Multimaster System

Single Master System

A typical single master system may be configured, using a

device as the master and four devices as

slaves (see Figure 53). The master device selects the individual slave de-

vices by using four pins of a parallel port to control the four SS

The SS

pins of the slave devices.

pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: T o prevent a b us conflict on the MISO line the master allows only one active slave device during a transmission.

Figure 53. Single Master / Multiple Slave Configuration

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has n ot written to its S PIDR register.

Other transmission security methods can use ports for handshake lines or data by tes with command fields.

Multi-Master System

A multi-master system may al so be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system.

The multi-master system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register.

SCK

Device

MOSI

SCK

Master Device

SS SS

SCK

Slave

MOSI MOSI MOSIMISO MISO MISOMISO

MISO

Ports

Slave

Device

SCK SCK

Slave

Device

Slave

80/171

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.6 Low Power Modes

Mode Description

No effect on SPI.

WAIT

HALT

SPI interrupt events cause the Device to exit from WAIT mode.

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the Device is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device.

11.4.6.1 Using the S PI to wake-up the De vice from Halt mode

In slave configuration, the SPI is able to wake-up

Device from HALT mode th rough a SPIF inter-

the rupt. The data received is subsequen tly read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears th e SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mo de, if the SPI remains in Slave mode, it is recommended to perform an extra comm unications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake-up the

Device from

Halt mode only if the Slave Select signal (external

ST72260G, ST72262G, ST72264G

pin or the SSI bit in the SPICSR register) is low when the lection is configured as external (see Section

11.4.3.2), make sure the master drives a low level

on the SS

11.4.7 Interrupts

Interrupt Event

SPI End of Transfer Event

Master Mode Fault Event

Overrun Error OVR Yes No

Note: The SPI interrupt event s are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the in terrupt mas k in the CC register is reset (RIM instruction).

Device enters Halt mode. So if Slave se-

pin when the slave enters Halt mode.

Event

Flag

SPIF

MODF Yes N o

Enable

Control

Bit

SPIE

Exit from Wait

Yes Yes

Exit

from

Halt

81/171

ST72260G, ST72262G, ST72264G

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.8 Register Description CONTROL REGISTER (SPICR)

Read/Write Reset Value: 0000 xxxx (0xh)

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 3 = CPOL This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication

Bit 7 = SPIE

Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

byte boundaries, the SPI mus t be disabled by resetting the SPE bit.

0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End

of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register)

Bit 2 = CPHA This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

Bit 6 = SPE

Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

edge.

Note: The slave must hav e the same CPOL and

CPHA settings as the master. (see Section 11.4.5.1 "Master Mode Fault

(MODF)" on page 79). The SPE bit is cleared by

reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2

Divider Enable

This bit is set and cleared by software and is

Bits 1:0 = SPR[1:0]

These bits are set and c leared by software. Used

with the SPR2 bit, they select the baud rate o f the

SPI serial clock SCK out put by the SPI in ma ster

mode.

Note: These 2 bits have no effect in slave mode.

Table 16 . SPI Master mode S C K Fr equency

cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Ref er to Table 16 SPI Mast er

Serial Clock SPR2 SPR1 SPR0

mode SCK Frequency.

0: Divider by 2 enabled 1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

Master Mode.

=0 (see Section 11.4.5.1 "Master Mode Fault

(MODF)" on page 79).

0: Slave mode 1: Master mode. The function of the SCK pin

changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Clock Polarity.

Clock Phase.

Serial Clock Frequency.

/4 1 0 0

CPU

/8 0 0 0

CPU

/16 0 0 1

CPU

/32 1 1 0

CPU

/64 0 1 0

CPU

/128 0 1 1

CPU

82/171

ST72260G, ST72262G, ST72264G

SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)

SPIF WCOL OVR MODF - SOD SSM SSI

Bit 7 = SPIF

Serial Peripheral Data Transfer Flag

(Read only).

This bit is set by hardware when a trans fer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the

Device and an exter-

nal device has been completed.

Note: While t he SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read .

Bit 6 = WCOL

Write Collision status (Read only).

This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see

Figure 52).

0: No write collision occurred 1: A write collision has been detected

Bit 5 = OVR S

PI Overrun error (Read only).

This bit is set by hardware when the byte currently being received in the shift register is ready to b e transferred into the SPIDR register while SPIF = 1 (See Section 11.4.5.2). An interrupt is generated if SPIE = 1 in SPICSR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected

Bit 4 = MODF

Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11. 4.5.1

"Master Mode Fault (MODF)" on page 79). An SPI

interrupt can be generated if SPIE=1 in the SPICSR register. This bit is cleared by a software sequence (An access to the SP ICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD

SPI Output Disable.

This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled

Bit 1 = SSM

SS Management.

This bit is set and cleared by software. When set, it disables the alternate funct ion of the SPI SS and uses the SSI bit value instead. See Section

11.4.3.2 "Slave Select Management" on page 76.

0: Hardware management (SS

nal pin)

1: Software management (internal SS

trolled by SSI bit. External SS al-purpose I/O)

Bit 0 = SSI

SS Internal Mode.

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of t he SS select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write Reset Value: Undefined

D7 D6 D5 D4 D3 D2 D1 D0

The SPIDR register is used to t ransmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte.

Notes: During the last cloc k cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPI CSR register is read.

Warning: A write to the SPIDR register places data directly into the shift register f or transmission.

A read to the SPIDR register returns the value located in the buffer and not the conten t of the shift register (see Figure 47).

managed by exter-

signal con-

pin free for gener-

slave

83/171

ST72260G, ST72262G, ST72264G

SERIAL PERIPHERAL INTERFACE (Cont’d) Table 17. SPI Register Map and Reset Values

Address

(Hex.)

0021h

0022h

0023h

Label

SPIDR

Reset Value

SPICR

Reset Value

SPICSR

Reset Value

76543210

MSB

xxxxxxx

SPIE

SPIF

SPE

WCOL

SPR20MSTR0CPOL

MODF

CPHA

SOD

SPR1

SSM

LSB

SPR0

SSI

84/171

11.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

ST72260G, ST72262G, ST72264G

11.5.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an indust ry stand ard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

11.5.2 Main Features

■ Full duplex, asynchronous communi cations

■ NRZ standard format (Mark/Space)

■ Dual baud rate generator systems

■ Independently programmable transmit and

receive baud rates up to 500K baud.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB) – Idle line

■ Muting function for multiprocessor configurations

■ Separate enable bits for Transmitter and

Receiver

■ Four error detection flags:

– Overrun error – Noise error – Frame error – Parity error

■ Five interrupt sources with flags:

– Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected

■ Parity control:

– Transmits parity bit – Checks parity of received data byte

■ Reduced power consumption mode

11.5.3 General Desc ription

The interface is externally connected to another device by two pins (see Figure 55):

– TDO: Transmit Data Output. When the transmit-

ter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as frames comprising:

– An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: – A conventiona l type for common ly-used baud

rates,

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard oscillator frequencies.

85/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 54. SCI Block Diagram

TDO

RDI

Write

Transmit Data Register (TDR)

Transmit Shift Register

TRANSMIT

CONTROL

CR2

Read

(DATA REGISTER) DR

Received Data Register (RDR)

Received Shift Register

R8 T8 SCID M WAKE PCE PS PIE

WAKE

UNIT

SBKRWURETEILIERIETCIETIE

RECEIVER

CONTROL

TDRE TC RDRF IDLE OR NF FE PE

CR1

RECEIVER

CLOCK

86/171

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

CPU

/16

/PR

TRANSMITTER RATE

CONTROL

BRR

SCP1

SCP0 SCT2

CONVENTIONAL BAUD RATE GENERATOR

SCT1SCT0SCR2SCR1SCR0

RECEI VE R RATE CONTRO L

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4 Functional Description

The block diagram of the S erial Control Interface, is shown in Figure 54. It contains 6 dedicated reg- isters:

– Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR) – An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in Section

11.5.7for the definitions of each bit.

Figure 55. Word Length Programming

ST72260G, ST72262G, ST72264G

11.5.4.1 Serial Data Format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 54).

The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame

of “1”s followed by t he start bit of the n ext frame which contains data.

A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transm itter inserts an extra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their own baud rate generator.

9-bit Word length (M bit is set)

Data Frame

Start

Bit

Bit0 Bit1

Bit2

Bit3 Bit4

Idle Frame

Break Frame

8-bit Word length (M bit is reset)

Data Frame

Start

Bit

Bit0 Bit1

Bit2

Bit3 Bit4 Bit5

Idle Frame

Break Fr ame

Bit5 Bit6

Bit6

Possible

Parity

Bit

Bit7 Bit8

Possible

Parity

Bit

Bit7

Stop

Bit

Next Data Frame

Next Start

Stop

Bit

Start

Bit

Extra

’1’

Next Data Frame

Start

Bit

Start

Bit

Start

Extra

’1’

Bit

Start

Bit

87/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. W hen the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register.

Character Transmission

During an SCI transmission, data shifts out least significant bit first on t he TDO pin. In this m ode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 54).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first transmission.

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is a lways perf ormed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in th e SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.

When a transmission is taking place, a write instruction to the SCIDR regi ster stores the data i n the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is ta king place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.

When a frame trans mission is com plete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register.

Clearing the TC bit is pe rformed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 55).

As long as the SBK bit is set, the SCI send break frames to the T DO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI t o send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.

Note: Resetting an d set ting t he TE bi t c auses the data in the TDR register to be lost . Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR.

88/171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit i s set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 54).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register. – The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception. Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register. The RDRF bit must be cleared before the end of t he

reception of the next character to avoid an overrun error.

Break Character

When a break character is received, the SPI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

ST72260G, ST72262G, ST72264G

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared.

When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recovery by discriminating between v alid inc oming dat a and noise.

When noise is detected in a frame: – The NF is set at the rising edge of the RDRF bit. – Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself generates an interrupt.

The NF bit is reset by a SCISR register read operation followed by a SCIDR register read operation.

Framing E rror

A framing error is detected when: – The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the

SCIDR register. – No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt. The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

89/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 56. SCI Baud Rate and Extended Prescaler Block Diagram

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

SCIETPR

EXTENDED TRANSMITTER PRESCAL ER REGISTER

SCIERPR

EXTENDED RECEIVER PRESCALER REGISTE R

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

TRANSMITTER

CLOCK

RECEIVER

CLOCK

CPU

90/171

/16

/PR

TRANSMITTER RATE

CONTROL

SCIBRR

SCP1

SCP0

SCT2

SCT1SCT0SCR2SCR1SCR0

RECEI VE R RAT E

CONTROL

CONVENT IONAL BAUD RATE GENERAT O R

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4.4 Conventional Baud Rate Generation

The baud rate for the receiver a nd trans mitter (Rx and Tx) are set independent ly and calculated as follo ws:

(16

CPU

PR)*RR

Tx =

(16

CPU

PR)*TR

Rx =

with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If f

is 8 MHz (normal mode) and if

CPU

PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud.

Note: the baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled.

11.5.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.

The extended baud rat e generator block diagram is described in the Figure 56.

The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register.

Note: the extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. T he baud rates are calculated as follows:

CPU

ERPR*(PR*RR)

Tx =

CPU

ETPR*(PR*TR)

Rx =

ST72260G, ST72262G, ST72264G

with: ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,.. 255 (see SCIERPR register)

11.5.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often des irable that only the intended message recipient should actively receive the f ull me ssag e cont ents, thus reducing redundant SCI service overhead for all non addressed receivers.

The non addressed devices may be placed in sleep mode by means of the muting function.

Setting the RWU b it by software puts the SCI in sleep mode:

All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the

following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.

Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RW U bit and sets the RDRF bit, which allows the receiver to receiv e thi s word normally and to use it as an address word.

Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event o ccurs (RWU is reset) before t he write operation, the RW U bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode.

91/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4.7 Parity Control

Parity control (generation of parity bit in trasmission and and parity chencking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 18.

Table 18. Frame Formats

M bit PCE bit SCI frame

0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB |

Legend: SB = Start Bit, STB = Sto p Bi t, PB = Pa ri ty Bit

Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit

Even pa rity: the p arity bit is calculated to ob tain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on w hether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).

Odd par it y: t he pari ty bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected

(PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt i s generated if PIE is set in the SCICR1 register.

11.5.5 Low Power Mo de s

Mode Description

No effect on SCI.

WAIT

SCI interrupts cause the device to exit from Wait mode.

SCI registers are frozen.

HALT

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

11.5.6 Interrupts

Enable

Interrupt Event

Transmit Data Register Empty

Transmission Complete

Received Data Ready to be Read

Overrun Error Detected OR Yes No Idle Line Detected IDLE ILIE Yes No Parity Error PE PIE Yes No

Event

Control

Flag

TDRE TIE Yes No

TC TCIE Yes No

RDRF

Bit

RIE

Exit from Wait

Exit

from

Halt

Yes No

The SCI interrupt events are connected to the same interrupt vect or .

These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

92/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.7 Register Description STATUS REGISTER (SCISR)

Read Only Reset Value: 1100 0000 (C0h)

TDRE TC RDRF IDLE OR NF FE PE

Bit 7 = TDRE

Transmit data register empty.

This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit=1 in the SCICR2 register. It is cleared b y a sof tw are sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register

Note: Data will not be transferred to the s hift register unless the TDRE bit is cleared.

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generat ed if TCIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

Bit 5 = R DRF

Received data ready flag.

This bit is set by hardware when the content of the RDR register has been transferred to the SCI DR register. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read

Note: The IDLE bit will not be set agai n until the RDRF bit has been set itself (i.e. a new idle line occurs).

Bit 3 = OR

Overrun error.

This bit is set by hardware when the word currently being received in the s hift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software seque nce (an access to the SCISR register followed by a read to the SCIDR register). 0: No Overrun error 1: Overrun error is detected

Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.

Bit 1 = FE

Framing error.

This bit is set by hardware when a de-synchronization, excessive noise or a b reak character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Framing error is detected 1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be se t.

Bit 4 = IDLE

Idle line detect.

This bit is set by hardware when a I dle Line is detected. An interrupt is generated if the ILIE=1 i n the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected

Bit 0 = PE

Parity error.

This bit is set by hardware when a parity error occurs in receiver mode . It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR da ta register). An interrupt is generated if PIE=1 in the SCICR1 register. 0: No parity error 1: Parity error

93/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1)

Read/Write Reset Value: x000 0000 (x0h)

R8 T8 SCID M WAKE PCE PS PIE

Bit 7 = R8

Receive data bit 8.

This bit is used t o store the 9t h bit o f the rec ei ved word when M=1.

Bit 6 = T8

Transmit data bit 8.

This bit is used to store the 9th bit of the transmitted word when M=1.

Bit 5 = SCID

Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled

Bit 4 = M

Word length.

This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and reception).

Bit 3 = WAKE

Wake-Up method.

This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark

Bit 2 = PCE

Parity control enable.

This bit selects the hardware parity control (generation and detection). When the parity control i s enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled

Bit 1 = PS

Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by sof tware. The parity will be selected after the current byte. 0: Even parity 1: Odd parity

Bit 0 = PIE

Parity interrupt enable.

This bit enables the interrupt capability of the hardware parity control when a parity error is de tected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled.

94/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2)

Read/Write Reset Value: 0000 0000 (00h)

TIE TCIE RIE ILIE TE RE RWU

Bit 7 = TIE

Transmitter interrupt enable

SBK

. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE

Transmission complete interrupt ena-

ble

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in

the SCISR register

Bit 5 = RIE

Receiver interrupt enable

. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Bit 4 = ILIE

Idle line interrupt enable.

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Bit 3 = TE

Transmitter enable.

This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled

Notes: – During transmission, a “0” pulse on the TE bit

(“0” followed by “1”) sends a preamble (idle line) after the current word.

– When TE is set there is a 1 bit-time delay before

the transmission starts.

Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set).

Bit 2 = RE

Receiver enable.

This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a

start bit

Bit 1 = RWU

Receiver wake-up.

This bit determines if the SCI is in mut e mode or not. It is set and cleared by so ftware and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in Active mode 1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some da ta first, otherwise it cannot function in Mute mode with wakeup by idle line detection.

Bit 0 = SBK

Send break.

This bit set is used to se nd break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word.

95/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR)

Read/Write Reset Value: Undefined Contains the Received or Transmitted dat a char-

acter, depending on whether it is read from or written to.

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

The Data register performs a double function (read and write) since it is composed of two reg isters, one for transmission (T DR) and one for recep tion (RDR). The TDR register provides the parallel interface between the internal bus and the out put shift register (see Figure 54). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 54).

Bits 5:3 = SCT[2:0]

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.

TR dividing factor SCT2 SCT1 SCT0

1000 2001 4010

8011 16 1 0 0 32 1 0 1 64 1 1 0

128 1 1 1

Bits 2:0 = SCR[2:0]

SCI Receiver rate divisor.

These 3 bits, in conjunc tion with t he SC P[ 1:0 ] bits define the total division applied to the bus clock to yield the receive rate clock in conventional B aud Rate Generator mode.

BAUD RATE REGISTER (SCIBRR)

Read/Write Reset Value: 0000 0000 (00h)

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

Bits 7:6= SCP[1:0]

First SCI Prescaler

These 2 prescaling bits allow several standard

RR Dividing factor SCR2 SCR1 SCR0

1000

2001

4010

8011 16 1 0 0 32 1 0 1 64 1 1 0

128 1 1 1

clock division ranges:

PR Prescaling factor SCP1 SCP0

100 301 410

13 1 1

96/171

SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION

Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi-

sion factor for the receive circuit.

ST72260G, ST72262G, ST72264G

EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIET PR )

Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate divi-

sion factor for the transmit circuit.

ERPR7ERPR6ERPR5ERPR4ERPR3ERPR2ERPR1ERPR

Bits 7:0 = ERPR[7:0]

8-bit Extended Receive

Prescaler Register.

The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 56) is divided by the b inary fa ctor set i n the SCI ERPR registe r (in the range 1 to 255).

The extended baud rat e generator is no t used af ter a reset.

ETPR7ETPR6ETPR5ETPR4ETPR3ETPR2ETPR1ETPR

Bits 7:0 = ETPR[7:0]

8-bit Extended Transmit

Prescaler Register.

The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 56) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255).

The extended baud rate generator is not used after a reset.

Table 19. Baudrate Selection

Conditions

Symbol Parameter

Communication freque ncy 8MHz

CPU

Accuracy

vs. Standard

~0.16%

~0.79%

Prescaler

Conventional Mode TR (or RR)=128, PR=13 TR (or RR)= 32, PR=13 TR (or RR)= 16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 16, PR= 3 TR (or RR)= 2, PR=13 TR (or RR)= 1, PR=13

Extended Mode ETPR (or ERPR) = 35, TR (or RR)= 1, PR=1

Standard

1200 2400 4800

9600 10400 19200 38400

14400 ~14285.71

300

Baud

Rate

~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38

~10416.67 ~19230.77 ~38461.54

Unit

97/171

ST72260G, ST72262G, ST72264G

SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 20. SCI Register Map and Reset Values

Address

(Hex.)

Name

SCISR

Reset Value

SCIDR

Reset Value

SCIBRR

Reset Value

SCICR1

Reset Value

SCICR2

Reset Value

SCIERPR

Reset Value

SCIETPR

Reset Value

76543210

TDRE

DR7

SCP1

TIE

ERPR70ERPR60ERPR50ERPR40ERPR30ERPR20ERPR10ERPR0

ETPR70ETPR60ETPR50ETPR40ETPR30ETPR20ETPR10ETPR0

DR6

SCP0

TCIE

RDRF0IDLE

DR5

SCT20SCT1

SCID

RIE

DR4

ILIE

DR3

SCT00SCR20SCR10SCR0

WAKE

DR2

PCE

DR1

RWU

DR0

PIE

SBK

98/171

11.6 I2C BUS INTERFACE (I2C)

ST72260G, ST72262G, ST72264G

11.6.1 Introduction

The I

C Bus Interface serves as an interface between the microcontroller and the serial I provides both multimaster and slave functions, and controls all I

C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I

C bus. It

mode (400 k Hz).

11.6.2 Main Features

■ Parallel-bus/I

■ Multi-master capability

■ 7-bit/10-bit Addressing

■ Transmitter/Receiver flag

■ End-of-byte transmission flag

■ Transfer problem detection

C Master Features:

■ Clock generation

■ I

C bus busy flag

■ Arbitration Lost Flag

■ End of byte transmission flag

■ Transmitter/Receiver Flag

■ Start bit detection flag

■ Start and Stop generation

C Slave Features:

■ Stop bit detection

■ I

C bus busy flag

■ Detection of misplaced start or stop condition

■ Programmable I

■ Transfer problem detection

■ End-of-byte transmission flag

■ Transmitter/Receiver flag

C protocol converter

C Address detection

11.6.3 General Description

In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled

Figure 57. I

C BUS Protocol

handshake. The interrupts are enabled or disabled by software. The int erfac e is c onnect ed t o the I bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I and a Fast I ware.

C bus. This selection is made by soft-

Mode Selection

The interface can operate in the four following modes:

– Slave transm itter/receiver – Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to

master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability.

Communication Flow

In Master mode, it initiates a data transfer and generates the clock signal. A serial data tran sfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.

In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), an d the General Call address. The General Call address detection may be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes, MSB first. The f irst by te(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode.

A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Fig -

ure 57.

C bus

SDA

SCL

CONDITION

START

MSB

ACK

12 89

STOP

CONDITION

VR02119B

99/171

ST72260G, ST72262G, ST72264G

I2C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by software.

The I

C interface address and/or general call address can be selected by software.

The speed of the I between Standard (0-100KHz) and Fast I 400KHz).

SDA/SCL Line Control

Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register.

Figure 58. I

C Interface Block Diagram

C interface may be selected

C (100-

The SCL frequency (F grammable clock divider which depends on the

C bus mode.

When the I

C cell is enabled, the SDA a nd SCL

) is controlled by a pro-

scl

ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application.

When the I

C cell is disabled, the S DA and SCL

ports revert to being standard I /O port pins.

DATA REGISTER (DR)

SDA or SDAI

SCL or SCLI

DATA CON T ROL

CLOCK CONTROL

CLOCK CONTROL REGIS T ER (CCR)

CONTRO L REGISTE R (C R)

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2)

CONTROL LOGIC

100/171

INTERRUPT

ST ST72260G, ST72262G, ST72264G User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual