ST M48T02, M48T12 User Manual
5.0 V, 16 Kbit (2 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated, ultra low power SRAM, real-time
clock, and power-fail control circuit
■ BYTEWIDE
■ BCD coded year, month, day, date, hours,
minutes, and seconds
■ Typical clock accuracy of ±1 minute a month,
at 25 °C
■ Software controlled clock calibration for high
accuracy applications
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
(V
PFD
–M48T02: V
4.5 V ≤ V
–M48T12: V
4.2 V ≤ V
■ Self-contained battery and crystal in the
CAPHAT
■ Pin and function compatible with JEDEC
standard 2 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
™
RAM-like clock access
= power-fail deselect voltage):
= 4.75 to 5.5 V;
CC
≤ 4.75 V
PFD
= 4.5 to 5.5 V;
CC
≤ 4.5 V
PFD
™
DIP package
M48T02
M48T12
24
1
PCDIP24
battery/crystal
CAPHAT™
June 2011 Doc ID 2410 Rev 9 1/25
www.st.com
1
Contents M48T02, M48T12
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 V
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25 Doc ID 2410 Rev 9
M48T02, M48T12 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 21
Table 13. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 2410 Rev 9 3/25
List of figures M48T02, M48T12
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 21
Figure 14. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4/25 Doc ID 2410 Rev 9
M48T02, M48T12 Description
1 Description
The M48T02/12 TIMEKEEPER® RAM is a 2 Kb x 8 non-volatile static RAM and real-time
clock which is pin and functional compatible with the DS1642.
A special 24-pin, 600 mil DIP CAPHAT
quartz crystal and a long life lithium button cell to form a highly integrated battery-backed
memory and real-time clock solution.
The M48T02/12 button cell has sufficient capacity and storage life to maintain data and
clock functionality for an accumulated time period of at least 10 years in the absence of
power over the operating temperature range.
The M48T02/12 is a non-volatile pin and function equivalent to any JEDEC standard
2 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed.
Figure 1. Logic diagram
™
package houses the M48T02/12 silicon with a
V
CC
11
A0-A10
W
E
G
Table 1. Signal names
A0-A10 Address inputs
DQ0-DQ7 Data inputs / outputs
E Chip enable
G Output enable
W WRITE enable
V
CC
V
SS
Supply voltage
Ground
M48T02
M48T12
V
SS
8
DQ0-DQ7
AI01027
Doc ID 2410 Rev 9 5/25
Description M48T02, M48T12
Figure 2. DIP connections
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ2
SS
1
2
3
4
5
6
7
8
9
10
11
12
M48T02
M48T12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI01028
Figure 3. Block diagram
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
POWER
V
PFD
BOK
8 x 8 BiPORT
SRAM ARRAY
2040 x 8
SRAM ARRAY
V
SS
A0-A10
DQ0-DQ7
E
W
G
AI01329
6/25 Doc ID 2410 Rev 9
M48T02, M48T12 Operation modes
2 Operation modes
As Figure 3 on page 6 shows, the static memory array and the quartz controlled clock
oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations
contain the year, month, date, day, hour, minute, and second in 24-hour BCD format.
Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made
automatically.
Byte 7F8h is the clock control register. This byte controls user access to the clock
information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T02/12 includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
CC
. As V
approximately 3 V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
is out of
CC
falls below
CC
Table 2. Operating modes
Mode V
Deselect
WRITE V
READ V
READ V
Deselect
Deselect ≤ V
1. See Table 11 on page 20 for details.
Note: X = V
or VIL; VSO = Battery backup switchover voltage.
IH
4.75 to 5.5 V
4.5 to 5.5 V
V
PFD
2.1 READ mode
The M48T02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E
the E
and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
CC
or
VSO to
(min)
SO
ELQV
E G W DQ0-DQ7 Power
X X High Z Standby
XVILD
V
IL
V
IH
(1)
(1)
V
IH
IL
IL
IL
X X X High Z CMOS standby
X X X High Z Battery backup mode
) or output enable access time (t
IN
V
IH
V
IH
D
OUT
High Z Active
) after the last
AVQ V
Active
Active
and G access times are also satisfied. If
).
GLQV
Doc ID 2410 Rev 9 7/25
Operation modes M48T02, M48T12
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the address inputs are changed while E
for output data hold time (t
, the data lines will be driven to an indeterminate state until t
AVQ V
and G remain active, output data will remain valid
) but will go indeterminate until the next address access.
AXQX
AVQ V
. If
Figure 4. READ mode AC waveforms
tAVAV
A0-A10
E
G
DQ0-DQ7
Note: WRITE enable (W
tAVQV tAXQX
tELQV
tELQX
tGLQV
tGLQX
) = High.
VAL ID
tEHQZ
tGHQZ
VAL ID
Table 3. READ mode AC characteristics
M48T02/M48T12
Symbol Parameter
t
AVAV
t
AVQ V
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
READ cycle time 70 150 200 ns
Address valid to output valid 70 150 200 ns
Chip enable low to output valid 70 150 200 ns
Output enable low to output valid 35 75 80 ns
Chip enable low to output transition 5 10 10 ns
Output enable low to output transition 5 5 5 ns
Chip enable high to output Hi-Z 25 35 40 ns
Output enable high to output Hi-Z 25 35 40 ns
Address transition to output transition 10 5 5 ns
(1)
Min Max Min Max Min Max
AI01330
Unit–70 –150 –200
8/25 Doc ID 2410 Rev 9
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